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Micromachines 2019, 10(1), 32; https://doi.org/10.3390/mi10010032

Design and Characterization of Semi-Floating-Gate Synaptic Transistor

1
Department of Electronics Engineering, Gachon University, Gyeonggi-do 13120, Korea
2
Department of Energy IT, Gachon University, Gyeonggi-do 13120, Korea
3
Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, Korea
*
Authors to whom correspondence should be addressed.
Received: 14 November 2018 / Revised: 31 December 2018 / Accepted: 2 January 2019 / Published: 7 January 2019
(This article belongs to the Special Issue Miniaturized Transistors)
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Abstract

In this work, a study on a semi-floating-gate synaptic transistor (SFGST) is performed to verify its feasibility in the more energy-efficient hardware-driven neuromorphic system. To realize short- and long-term potentiation (STP/LTP) in the SFGST, a poly-Si semi-floating gate (SFG) and a SiN charge-trap layer are utilized, respectively. When an adequate number of holes are accumulated in the SFG, they are injected into the nitride charge-trap layer by the Fowler–Nordheim tunneling mechanism. Moreover, since the SFG is charged by an embedded tunneling field-effect transistor existing between the channel and the drain junction when the post-synaptic spike occurs after the pre-synaptic spike, and vice versa, the SFG is discharged by the diode when the post-synaptic spike takes place before the pre-synaptic spike. This indicates that the SFGST can attain STP/LTP and spike-timing-dependent plasticity behaviors. These characteristics of the SFGST in the highly miniaturized transistor structure can contribute to the neuromorphic chip such that the total system may operate as fast as the human brain with low power consumption and high integration density. View Full-Text
Keywords: semi-floating gate; synaptic transistor; neuromorphic system; spike-timing-dependent plasticity (STDP); highly miniaturized transistor structure; low power consumption semi-floating gate; synaptic transistor; neuromorphic system; spike-timing-dependent plasticity (STDP); highly miniaturized transistor structure; low power consumption
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This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).
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Cho, Y.; Lee, J.Y.; Yu, E.; Han, J.-H.; Baek, M.-H.; Cho, S.; Park, B.-G. Design and Characterization of Semi-Floating-Gate Synaptic Transistor. Micromachines 2019, 10, 32.

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