Low-Voltage Integrated Circuits Design and Application

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: closed (30 September 2020) | Viewed by 93408

Special Issue Editor


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Guest Editor
Department of Information Engineering, University of Brescia, 25123 Brescia, Italy
Interests: electromagnetic interference analysis in integrated circuits; integrated voltage converters based on capacitors or inductors; design of ultra-low voltage analog circuits
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Special Issue Information

Dear Colleagues,

In recent years, the design of low-voltage and ultra-low power circuits has been of paramount importance. This is motivated by the power constraints and the advanced deep submicron technologies which require lower and lower supply voltages, less than 1V. Even lower supply voltage may be requested for low-power systems, especially those applied in biomedical implantable or wearable electronic devices, autonomous sensor nodes supplied with nonconventional energy sources, Internet of Things networks, and other similar applications.

One of the most challenging tasks for analogue and digital designers is to maintain the circuit performances by developing novel circuit structures capable of operating with a low supply voltage.

Moreover, the increasing demands for both low supply voltage and energy efficiency often have a detrimental effect on the robustness and the reliability of integrated circuits, especially analogue ones.

The topics to be covered in this Special Issue are as follows:

  • Theory, design, and new applications of low-voltage, low-power circuits;
  • Conventional and nonconventional low-voltage analog and digital design techniques;
  • Supply and energy harvesting blocks;
  • Implantable and wearable devices for biomedical monitoring applications;
  • Low-voltage circuits for Internet of Things (IoT) applications;
  • Low-voltage power-efficient analog-to-digital converters;
  • Design techniques to achieve high robustness and reliability against the electromagnetic pollution.
Prof. Dr. Anna Richelli
Guest Editor

Manuscript Submission Information

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Published Papers (22 papers)

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Editorial

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3 pages, 156 KiB  
Editorial
Low-Voltage Integrated Circuits Design and Application
by Anna Richelli
Electronics 2021, 10(1), 89; https://doi.org/10.3390/electronics10010089 - 5 Jan 2021
Cited by 3 | Viewed by 2509
Abstract
One of the most challenging tasks for analog and digital designers is to maintain the circuit performances by developing novel circuit structures, robust, reliable, and capable of operating with low supply voltage [...] Full article
(This article belongs to the Special Issue Low-Voltage Integrated Circuits Design and Application)

Research

Jump to: Editorial, Review

9 pages, 1358 KiB  
Article
High Speed Back-Bias Voltage (VBB) Generator with Improved Pumping Current
by Taegun Yim, Choongkeun Lee and Hongil Yoon
Electronics 2020, 9(11), 1835; https://doi.org/10.3390/electronics9111835 - 3 Nov 2020
Cited by 1 | Viewed by 2981
Abstract
Due to the advance of dynamic random access memory (DRAM) technologies with the steadfast increase of density with aggressively scaled storage capacitors, the supply voltage has been lowered to under 1 V to reduce power consumption. The above progress has been accompanied by [...] Read more.
Due to the advance of dynamic random access memory (DRAM) technologies with the steadfast increase of density with aggressively scaled storage capacitors, the supply voltage has been lowered to under 1 V to reduce power consumption. The above progress has been accompanied by the increasingly difficult task of sensing cell data reliably. One of the essential methods to preserve sustainable data retention characteristic is to curtail the sub-threshold leakage current by using a negative voltage bias for the bulk of access transistors. This negative back-bias is generated by a back-bias voltage generator. This paper proposes a novel high-speed back-bias voltage (VBB) generator with a cross-coupled hybrid pumping scheme. The conventional circuit uses one fixed voltage to control the gates of discharge of the p-channel metal oxide semiconductor (PMOS) and transfer n-channel metal oxide semiconductor (NMOS), respectively. However, the proposed circuit adds an auxiliary pump, thereby able to control more aptly with a lower negative voltage when discharging and a higher positive voltage when transferring. As a result, the proposed circuit achieves a faster pump-down speed and higher pumping current at a lower supply voltage compared to conventional circuits. The H-simulation program with integrated circuit emphasis (HSPICE) simulation results with the Taiwan semiconductor manufacturing company (TSMC) 0.18 um process technology indicates that the proposed circuit has about a 20% faster pump-down speed at a supply voltage of voltage common collector (VCC) = 1.2 V and about 3% higher pumping current at VBB from −0.6 V to −1 V with the ability to generate a near 3% higher ratio of |VBB|/VCC at VCC = 0.6 V compared to conventional circuits. Hence, the proposed circuit is extremely suitable and promising for future low-power and high-performance DRAM applications. Full article
(This article belongs to the Special Issue Low-Voltage Integrated Circuits Design and Application)
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11 pages, 2720 KiB  
Article
A Negative Charge Pump Using Enhanced Pumping Clock for Low-Voltage DRAM
by Choongkeun Lee, Taegun Yim and Hongil Yoon
Electronics 2020, 9(11), 1769; https://doi.org/10.3390/electronics9111769 - 26 Oct 2020
Cited by 4 | Viewed by 4939
Abstract
As the supply voltage decreases, there is a need for a high-speed negative charge pump circuit, for example, to produce the back-bias voltage (VBB) with high pumping efficiency at a low supply voltage (VDD). Beyond the basic negative charge [...] Read more.
As the supply voltage decreases, there is a need for a high-speed negative charge pump circuit, for example, to produce the back-bias voltage (VBB) with high pumping efficiency at a low supply voltage (VDD). Beyond the basic negative charge pump circuit with the small area overhead, advanced schemes such as hybrid pump circuit (HCP) and cross-coupled hybrid pump circuits (CHPC) were introduced to improve the pumping efficiency and pump down speed. However, they still suffer from pumping efficiency degradation, low level |VBB|, and small pumping currents at very low VDD. A novel negative charge pump using an enhanced pumping clock is proposed. The proposed cross-coupled charge pump consists of the enhanced pumping clock generator (ECG) having a pair of inverters and PMOS latch circuit to produce an enhanced control signal with a greater amplitude, thereby working efficiently especially at low supply voltages. The proposed scheme is validated with a HSPICE simulation using the TSMC 180 nm process. The proposed scheme can be operated down to VDD = 0.4 V, and |VBB|/VDD is obtained to be 86.1% at VDD = 0.5 V and Cload = 20 nF. Compared to the state-of-the-art CHPC scheme, the pumping efficiency is larger by 35% at VDD = 0.6 V and RL = 10 KΩ, and the pumping current is 2.17 times greater at VDD = 1.2 V and VBB = 0 V, making the circuit suitable for very low supply voltage applications in DRAMs. Full article
(This article belongs to the Special Issue Low-Voltage Integrated Circuits Design and Application)
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16 pages, 4959 KiB  
Article
A Novel Low-Power Synchronous Preamble Data Line Chip Design for Oscillator Control Interface
by Shih-Lun Chen, Tsun-Kuang Chi, Min-Chun Tuan, Chiung-An Chen, Liang-Hung Wang, Wei-Yuan Chiang, Ming-Yi Lin and Patricia Angela R. Abu
Electronics 2020, 9(9), 1509; https://doi.org/10.3390/electronics9091509 - 14 Sep 2020
Cited by 5 | Viewed by 2980
Abstract
In this paper, a novel low-power synchronous preamble data line protocol chip design for serial communication is proposed. The serial communication only uses two wires, chip select (CS) and secure digital (SD), to transmit and receive data between two devices. The proposed protocol [...] Read more.
In this paper, a novel low-power synchronous preamble data line protocol chip design for serial communication is proposed. The serial communication only uses two wires, chip select (CS) and secure digital (SD), to transmit and receive data between two devices. The proposed protocol aims to use a fewer number of wires for the interface, therefore reducing the complexity as well as the area of the chip design. Moreover, it increases the efficiency through a synchronous serial communication-controlled oscillator. The low-power synchronous preamble data line protocol design was successfully verified using a field-programmable gate array (FPGA) as a master device and a real chip as a slave device. The signals are checked through the use of a logic analyzer. The realized low-power synchronous preamble data line protocol chip design has a gate count of only 5.07 K gates, a low power dissipation of 12 mW, and a chip area of 453,260 μm2 using the Taiwan semiconductor manufacturing company (TSMC) 0.18 μm CMOS process. Compared with the three-wire serial peripheral interface (SPI) protocol, the proposed design has the advantages of having a lower cost and a lower power consumption. Full article
(This article belongs to the Special Issue Low-Voltage Integrated Circuits Design and Application)
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13 pages, 1226 KiB  
Article
PESL: System-Level Estimation of Power-Management Effect on Dynamic Energy Consumption
by Jaroslav Erdelyi, Dominik Macko and Katarina Jelemenska
Electronics 2020, 9(8), 1313; https://doi.org/10.3390/electronics9081313 - 15 Aug 2020
Cited by 3 | Viewed by 2790
Abstract
Power estimation is one of the key aspects that can help designers create digital circuits more effectively. If a designer is able to estimate circuit parameters during the early stages of development, correct decisions can be made that can significantly shorten the design [...] Read more.
Power estimation is one of the key aspects that can help designers create digital circuits more effectively. If a designer is able to estimate circuit parameters during the early stages of development, correct decisions can be made that can significantly shorten the design time. The early design stages are represented by modeling at the system level of abstraction. However, existing system-level power/energy estimation methods are either too complicated, or they do not consider power management when estimating power consumption, meaning they are inaccurate. Therefore, in this paper we propose a method for a more accurate system-level estimation of the dynamic energy consumption by considering the impact of power management. The SystemC description of a power-managed system and the simulation results (in the form of the value change dump (VCD)) are inputs to the estimation method. The proposed method is based on an activity profile using the modified Hamming distance computation. The method is especially useful for the exploration of alternative power-management strategies, and it helps the designer to select the most efficient strategy. Full article
(This article belongs to the Special Issue Low-Voltage Integrated Circuits Design and Application)
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14 pages, 4369 KiB  
Article
Ultra-Low-Voltage Inverter-Based Amplifier with Novel Common-Mode Stabilization Loop
by Giuseppe Manfredini, Alessandro Catania, Lorenzo Benvenuti, Mattia Cicalini, Massimo Piotto and Paolo Bruschi
Electronics 2020, 9(6), 1019; https://doi.org/10.3390/electronics9061019 - 19 Jun 2020
Cited by 24 | Viewed by 6033
Abstract
This work presents a single-stage, inverter-based, pseudo-differential amplifier that can work with ultra-low supply voltages. A novel common-mode stabilization loop allows proper differential operations, without impacting over the output differential performance. Electrical simulations show the effectiveness of this amplifier for supply voltages in [...] Read more.
This work presents a single-stage, inverter-based, pseudo-differential amplifier that can work with ultra-low supply voltages. A novel common-mode stabilization loop allows proper differential operations, without impacting over the output differential performance. Electrical simulations show the effectiveness of this amplifier for supply voltages in the range of 0.3–0.5 V. In particular, a dc voltage gain of 25.16 dB, a gain-bandwidth product of 131.9 kHz with a capacitive load of 10 pF, and a static current consumption of only 557 nA are estimated at VDD = 0.5 V. Moreover, the circuit behavior with respect to process and temperature variations was verified. Finally, the proposed amplifier is employed in a switched-capacitor integrator and in a sample-and-hold circuit to prove its functionality in case-study applications. Full article
(This article belongs to the Special Issue Low-Voltage Integrated Circuits Design and Application)
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21 pages, 7929 KiB  
Article
Regulated Charge Pumps: A Comparative Study by Means of Verilog-AMS
by Andrea Ballo, Michele Bottaro, Alfio Dario Grasso and Gaetano Palumbo
Electronics 2020, 9(6), 998; https://doi.org/10.3390/electronics9060998 - 15 Jun 2020
Cited by 25 | Viewed by 5649
Abstract
This paper proposes a comparative study of regulation schemes for charge-pump-based voltage generators using behavioral models in Verilog- Analog Mixed Signal (AMS) code. An accurate and simple model of the charge pump is first introduced. It allows reducing the simulation time of complex [...] Read more.
This paper proposes a comparative study of regulation schemes for charge-pump-based voltage generators using behavioral models in Verilog- Analog Mixed Signal (AMS) code. An accurate and simple model of the charge pump is first introduced. It allows reducing the simulation time of complex electronic systems made up by both analog and digital circuits while maintaining a good agreement with transistor-level simulations. Finally, a comprehensive comparative study of the different regulation schemes for charge pumps is reported which allows the designer to choose the most suitable topology for a given application and Charge Pump (CP) operative zone. Full article
(This article belongs to the Special Issue Low-Voltage Integrated Circuits Design and Application)
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15 pages, 3507 KiB  
Article
Dynamic and Static Calibration of Ultra-Low-Voltage, Digital-Based Operational Transconductance Amplifiers
by Pedro Toledo, Paolo Crovetti, Hamilton Klimach and Sergio Bampi
Electronics 2020, 9(6), 983; https://doi.org/10.3390/electronics9060983 - 12 Jun 2020
Cited by 15 | Viewed by 3514
Abstract
The calibration of the effects of process variations and device mismatch in Ultra Low Voltage (ULV) Digital-Based Operational Transconductance Amplifiers (DB-OTAs) is addressed in this paper. For this purpose, two dynamic calibration techniques, intended to dynamically vary the effective strength of critical gates [...] Read more.
The calibration of the effects of process variations and device mismatch in Ultra Low Voltage (ULV) Digital-Based Operational Transconductance Amplifiers (DB-OTAs) is addressed in this paper. For this purpose, two dynamic calibration techniques, intended to dynamically vary the effective strength of critical gates by different modulation strategies, i.e., Digital Pulse Width Modulation (DPWM) and Dyadic Digital Pulse Modulation (DDPM), are explored and compared to classic static calibration. The effectiveness of the calibration approaches as a mean to recover acceptable performance in non-functional samples is verified by Monte-Carlo (MC) post-layout simulations performed on a 300 mV power supply, nW-power DB-OTA in 180 nm CMOS. Based on the same MC post-layout simulations, the impact of each calibration strategy on silicon area, power consumption, and OTA performance is discussed. Full article
(This article belongs to the Special Issue Low-Voltage Integrated Circuits Design and Application)
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17 pages, 5328 KiB  
Article
A Novel 8T Cell-Based Subthreshold Static RAM for Ultra-Low Power Platform Applications
by Taehoon Kim, Sivasundar Manisankar and Yeonbae Chung
Electronics 2020, 9(6), 928; https://doi.org/10.3390/electronics9060928 - 2 Jun 2020
Cited by 5 | Viewed by 3895
Abstract
Subthreshold SRAMs profit various energy-constrained applications. The traditional 6T SRAMs exhibit poor cell stability with voltage scaling. To this end, several 8T to 16T cell designs have been reported to improve the stability. However, they either suffer one of disturbances or consume large [...] Read more.
Subthreshold SRAMs profit various energy-constrained applications. The traditional 6T SRAMs exhibit poor cell stability with voltage scaling. To this end, several 8T to 16T cell designs have been reported to improve the stability. However, they either suffer one of disturbances or consume large bit-area overhead. Furthermore, some cell options have a limited write-ability. This paper presents a novel 8T static RAM for reliable subthreshold operation. The cell employs a fully differential scheme and features cross-point access. An adaptive cell bias for each operating mode eliminates the read disturbance and enlarges the write-ability as well as the half-select stability in a cost-effective small bit-area. The bit-cell also can support efficient bit-interleaving. To verify the SRAM technique, a 32-kbit macro incorporating the proposed cell was implemented with an industrial 180 nm low-power CMOS process. At 0.4 V and room temperature, the proposed cell achieves 3.6× better write-ability and 2.6× higher dummy-read stability compared with the commercialized 8T cell. The 32-kbit SRAM successfully operates down to 0.21 V (~0.27 V lower than transistor threshold voltage). At its lowest operating voltage, the sleep-mode leakage power of entire SRAM is 7.75 nW. Many design results indicate that the proposed SRAM design, which is applicable to an aggressively-scaled process, might be quite useful in realizing cost-effective robust ultra-low voltage SRAMs. Full article
(This article belongs to the Special Issue Low-Voltage Integrated Circuits Design and Application)
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20 pages, 7139 KiB  
Article
Design and Realization of an Aviation Computer Micro System Based on SiP
by Hao Lv, Shengbing Zhang, Wei Han, Yongqiang Liu, Shuo Liu, Yaoqin Chu and Lei Zhang
Electronics 2020, 9(5), 766; https://doi.org/10.3390/electronics9050766 - 7 May 2020
Cited by 3 | Viewed by 4123
Abstract
In recent years, microelectronics technology has entered the era of nanoelectronics/integrated microsystems. System in Package (SiP) and System on Chip (SoC) are two important technical approaches for microsystems. The development of micro-system technology has made it possible to miniaturize airborne and missile-borne electronic [...] Read more.
In recent years, microelectronics technology has entered the era of nanoelectronics/integrated microsystems. System in Package (SiP) and System on Chip (SoC) are two important technical approaches for microsystems. The development of micro-system technology has made it possible to miniaturize airborne and missile-borne electronic equipment. This paper introduces the design and implementation of an aerospace miniaturized computer system. The SiP chip uses Xilinx Zynq® SoC (2ARM® + FPGA), FLASH memory and DDR3 memory as the main components, and integrates with SiP high-density system packaging technology. The chip has the advantages of small size and ultra-low power consumption compared with the traditional PCB circuit design. A pure software-based DDR3 signal eye diagram test method is used to verify the improvement inf the signal integrity of the chip without the need for probe measurement. The method of increasing the thermal conductive silver glue was used to improve the thermal performance after the test and analysis. The SiP chip was tested and analyzed with other mainstream aviation computers using a heading measurement of extended Kalman filter (EKF) algorithm. The paper has certain reference value and research significance in the miniaturization of the aviation computer system, the heat dissipation technology of SiP chip and the test method of signal integrity. Full article
(This article belongs to the Special Issue Low-Voltage Integrated Circuits Design and Application)
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13 pages, 3602 KiB  
Article
A 16 Gbps, Full-Duplex Transceiver over Lossy On-Chip Interconnects in 28 nm CMOS Technology
by Arash Ebrahimi Jarihani, Sahar Sarafi, Michael Koeberle, Johannes Sturm and Andrea M. Tonello
Electronics 2020, 9(5), 717; https://doi.org/10.3390/electronics9050717 - 26 Apr 2020
Cited by 2 | Viewed by 3649
Abstract
A high-speed full-duplex transceiver (FDT) over lossy on-chip interconnects is presented. The FDT employs a hybrid circuit to separate the inbound and outbound signals from each other and also performs echo-cancellation with the help of the main and the auxiliary drivers. A hybrid [...] Read more.
A high-speed full-duplex transceiver (FDT) over lossy on-chip interconnects is presented. The FDT employs a hybrid circuit to separate the inbound and outbound signals from each other and also performs echo-cancellation with the help of the main and the auxiliary drivers. A hybrid MOS device is utilized for impedance matching and conversion of the received voltage signal into a current signal for amplification. Moreover, a compensation capacitance ( C c ) is used at the output of the main driver to minimize the residual echo signal and achieve a higher data rate. The entire FDT architecture has been designed in TSMC 28 nm CMOS standard process with 0.9 V supply voltage. The performance results validate a 16 Gbps FD operation with a root-mean-square (RMS) jitter of 16.4 ps, and a power efficiency of 0.16 pJ/b/mm over a 5 mm on-chip interconnect without significant effect due to process-voltage-temperature (PVT) variations. To the best knowledge of the authors, this work shows the highest achievable full-duplex data rate, among the solutions reported in the literature to date, yet with low complexity, low layout area of 1581 μ m 2 and competitive power efficiency. Full article
(This article belongs to the Special Issue Low-Voltage Integrated Circuits Design and Application)
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16 pages, 3829 KiB  
Article
A Novel General Purpose Combined DFVF/VCII Based Biomedical Amplifier
by Vincenzo Stornelli, Gianluca Barile and Alfiero Leoni
Electronics 2020, 9(2), 331; https://doi.org/10.3390/electronics9020331 - 14 Feb 2020
Cited by 7 | Viewed by 2948
Abstract
We here present a 0.15 µm CMOS high input impedance and low noise AC coupled flipped voltage follower-based amplifier for high integration level in integrated circuits in a wide range of sensing applications. With such a circuit, it is possible to achieve a [...] Read more.
We here present a 0.15 µm CMOS high input impedance and low noise AC coupled flipped voltage follower-based amplifier for high integration level in integrated circuits in a wide range of sensing applications. With such a circuit, it is possible to achieve a high level of integration, thanks to the absence of passive resistors, and also to implement a very high input impedance without capacitive feedback thanks to bootstrap operation, thus offering a very low high-pass cutoff frequency. Simulated results with a proven and well modeled standard technology show a whole circuit input-referred noise of 5.4 µVrms. The bias voltage is ±0.6 V with a total power consumption of the single amplifier of 20 µW. The very low circuit complexity allows a very low estimated reduced area occupation giving, as a general example, the possibility of integrating an array of up to thousands of channels for biomedical applications. Detailed simulation results, PVT analysis and comparison tables are also presented in the paper. Full article
(This article belongs to the Special Issue Low-Voltage Integrated Circuits Design and Application)
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13 pages, 2912 KiB  
Article
A Power-Efficient Pipelined ADC with an Inherent Linear 1-Bit Flip-Around DAC
by Peiyuan Wan, Limei Su, Hongda Zhang and Zhijie Chen
Electronics 2020, 9(1), 199; https://doi.org/10.3390/electronics9010199 - 20 Jan 2020
Cited by 2 | Viewed by 4210
Abstract
An unity-gain 1-bit flip-around digital-to-analog converter (FADAC), without any capacitor matching issue, is proposed as the front-end input stage in a pipelined analog-to-digital converter (ADC), allowing an input signal voltage swing up to be doubled. This large input swing, coupled with the inherent [...] Read more.
An unity-gain 1-bit flip-around digital-to-analog converter (FADAC), without any capacitor matching issue, is proposed as the front-end input stage in a pipelined analog-to-digital converter (ADC), allowing an input signal voltage swing up to be doubled. This large input swing, coupled with the inherent large feedback factor (ideally β = 1) of the proposed FADAC, enables a power-efficient low-voltage high-resolution pipelined ADC design. The 1-bit FADAC is exploited in a SHA-less and opamp-sharing pipelined ADC, exhibiting 12-bit resolution with an input swing of 1.8 Vpp under a 1.1 V power supply. Fabricated in a 0.13-μm CMOS process, the prototype ADC achieves a measured signal-to-noise plus distortion ratio (SNDR) of 66.4 dB and a spurious-free dynamic range (SFDR) of 76.7 dB at 20 MS/s sampling rate. The ADC dissipates 5.2 mW of power and occupies an active area of 0.44 mm2. The measured differential nonlinearity (DNL) is +0.72/−0.52 least significant bit (LSB) and integral nonlinearity (INL) is +0.84/−0.75 LSB at a 3-MHz sinusoidal input. Full article
(This article belongs to the Special Issue Low-Voltage Integrated Circuits Design and Application)
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13 pages, 880 KiB  
Article
A Fast Transient Response Digital LDO with a TDC-Based Signal Converter
by Hongda Zhang, Peiyuan Wan, Jiarong Geng, Zhaozhe Liu and Zhijie Chen
Electronics 2020, 9(1), 132; https://doi.org/10.3390/electronics9010132 - 10 Jan 2020
Cited by 13 | Viewed by 4846
Abstract
The digital low drop-out regulator (LDO) has been used widely in digital circuits for its low supply voltage characteristics. However, as the traditional digital LDOs regulate the output voltage code at a rate of 1 bit per clock cycle, the transient response speed [...] Read more.
The digital low drop-out regulator (LDO) has been used widely in digital circuits for its low supply voltage characteristics. However, as the traditional digital LDOs regulate the output voltage code at a rate of 1 bit per clock cycle, the transient response speed is limited. This paper presents a digital LDO to improve transient response speed with a multi-bit conversion technique. The proposed technology uses a voltage sensor and a time-to-digital converter to convert the output voltage to digital codes. Based on a 65-nm CMOS process, the proposed DLDO reduces the settling time from 147.8 ns to 25.2 ns on average and the response speed is improved by about six times. Full article
(This article belongs to the Special Issue Low-Voltage Integrated Circuits Design and Application)
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13 pages, 794 KiB  
Article
Performance Profiling of Embedded ConvNets under Thermal-Aware DVFS
by Valentino Peluso, Roberto Giorgio Rizzo and Andrea Calimera
Electronics 2019, 8(12), 1423; https://doi.org/10.3390/electronics8121423 - 29 Nov 2019
Cited by 10 | Viewed by 3212
Abstract
Convolutional Neural Networks (ConvNets) can be shrunk to fit embedded CPUs adopted on mobile end-nodes, like smartphones or drones. The deployment onto such devices encompasses several algorithmic level optimizations, e.g., topology restructuring, pruning, and quantization, that reduce the complexity of the network, ensuring [...] Read more.
Convolutional Neural Networks (ConvNets) can be shrunk to fit embedded CPUs adopted on mobile end-nodes, like smartphones or drones. The deployment onto such devices encompasses several algorithmic level optimizations, e.g., topology restructuring, pruning, and quantization, that reduce the complexity of the network, ensuring less resource usage and hence higher speed. Several studies revealed remarkable performance, paving the way towards real-time inference on low power cores. However, continuous execution at maximum speed is quite unrealistic due to a fast increase of the on-chip temperature. Indeed, proper thermal management is paramount to guarantee silicon reliability and a safe user experience. Power management schemes, like voltage lowering and frequency scaling, are common knobs to control the thermal stability. Obviously, this implies a performance degradation, often not considered during the training and optimization stages. The objective of this work is to present the performance assessment of embedded ConvNets under thermal management. Our study covers the behavior of two control policies, namely reactive and proactive, implemented through the Dynamic Voltage-Frequency Scaling (DVFS) mechanism available on commercial embedded CPUs. As benchmarks, we used four state-of-the-art ConvNets for computer vision flashed into the ARM Cortex-A15 CPU. With the collected results, we aim to show the existing temperature-performance trade-off and give a more realistic analysis of the maximum performance achievable. Moreover, we empirically demonstrate the strict relationship between the on-chip thermal behavior and the hyper-parameters of the ConvNet, revealing optimization margins for a thermal-aware design of neural network layers. Full article
(This article belongs to the Special Issue Low-Voltage Integrated Circuits Design and Application)
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18 pages, 6527 KiB  
Article
Low Cost Autonomous Lock-In Amplifier for Resistance/Capacitance Sensor Measurements
by Paulina Maya, Belén Calvo, María Teresa Sanz-Pascual and Javier Osorio
Electronics 2019, 8(12), 1413; https://doi.org/10.3390/electronics8121413 - 26 Nov 2019
Cited by 19 | Viewed by 5777
Abstract
This paper presents the design and experimental characterization of a portable high-precision single-phase lock-in instrument with phase adjustment. The core consists of an analog lock-in amplifier IC prototype, integrated in 0.18 µm CMOS technology with 1.8 V supply, which features programmable gain and [...] Read more.
This paper presents the design and experimental characterization of a portable high-precision single-phase lock-in instrument with phase adjustment. The core consists of an analog lock-in amplifier IC prototype, integrated in 0.18 µm CMOS technology with 1.8 V supply, which features programmable gain and operating frequency, resulting in a versatile on-chip solution with power consumption below 834 µW. It incorporates automatic phase alignment of the input and reference signals, performed through both a fixed −90° and a 4-bit digitally programmable phase shifter, specifically designed using commercially available components to operate at 1 kHz frequency. The system is driven by an Arduino YUN board, thus overall conforming a low-cost autonomous signal recovery instrument to determine, in real time, the electrical equivalent of resistive and capacitive sensors with a sensitivity of 16.3 µV/Ω @ εrS < 3% and 37 kV/F @ εrS < 5%, respectively. Full article
(This article belongs to the Special Issue Low-Voltage Integrated Circuits Design and Application)
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15 pages, 4852 KiB  
Article
An FPGA-Based 16-Bit Continuous-Time 1-1 MASH ΔΣ TDC Employing Multirating Technique
by Ahmad Mouri Zadeh Khaki, Ebrahim Farshidi, Sawal Hamid MD Ali and Masuri Othman
Electronics 2019, 8(11), 1285; https://doi.org/10.3390/electronics8111285 - 5 Nov 2019
Cited by 4 | Viewed by 3389
Abstract
An all-digital voltage-controlled oscillator (VCO)-based second-order multi-stage noise-shaping (MASH) ΔΣ time-to-digital converter (TDC) is presented in this paper. The prototype of the proposed TDC was implemented on an Altera Stratix IV FPGA board. In order to improve the performance over conventional TDCs, a [...] Read more.
An all-digital voltage-controlled oscillator (VCO)-based second-order multi-stage noise-shaping (MASH) ΔΣ time-to-digital converter (TDC) is presented in this paper. The prototype of the proposed TDC was implemented on an Altera Stratix IV FPGA board. In order to improve the performance over conventional TDCs, a multirating technique is employed in this work in which higher sampling rate is used for higher stages. Experimental results show that the multirating technique had a significant influence on improving signal-to-noise ratio (SNR), from 43.09 dB without multirating to 61.02 dB with multirating technique (a gain of 17.93 dB) by quadrupling the sampling rate of the second stage. As the proposed design works in the time-domain and does not consist of any loop and calibration block, no time-to-voltage conversion is needed which results in low complexity and power consumption. A built-in oscillator and phase-locked loops (PLLs) of the FPGA board are utilized to generate sampling clocks at different frequencies. Therefore, no external clock needs to be applied to the proposed TDC. Two cases with different sampling rates were examined by the proposed design to demonstrate the capability of the technique. It can be implied that, by employing multirating technique and increasing sampling frequency, higher SNR can be achieved. Full article
(This article belongs to the Special Issue Low-Voltage Integrated Circuits Design and Application)
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13 pages, 1847 KiB  
Article
A Comprehensive Comparison of EMI Immunity in CMOS Amplifier Topologies
by Simone Becchetti, Anna Richelli, Luigi Colalongo and Zsolt Kovacs-Vajna
Electronics 2019, 8(10), 1181; https://doi.org/10.3390/electronics8101181 - 17 Oct 2019
Cited by 6 | Viewed by 3306
Abstract
This paper provides the results of a comprehensive comparison between complementary metal oxide semiconductor (CMOS) amplifiers with low susceptibility to electromagnetic interference (EMI). They represent the state-of-the-art in low EMI susceptibility design. An exhaustive scenario for EMI pollution has been considered: the injected [...] Read more.
This paper provides the results of a comprehensive comparison between complementary metal oxide semiconductor (CMOS) amplifiers with low susceptibility to electromagnetic interference (EMI). They represent the state-of-the-art in low EMI susceptibility design. An exhaustive scenario for EMI pollution has been considered: the injected interference can indeed directly reach the amplifier pins or can be coupled from the printed circuit board (PCB) ground. This is also a key point for evaluating the susceptibility from EMI coupled to the output pin. All of the amplifiers are re-designed in a United Microelectronics Corporation (UMC) 180 nm CMOS process in order to have a fair comparison. The topologies investigated and compared are basically derived from the Miller and the folded cascode ones, which are well-known and widely used by CMOS analog designers. Full article
(This article belongs to the Special Issue Low-Voltage Integrated Circuits Design and Application)
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12 pages, 1298 KiB  
Article
The Ultra-Low-k Dielectric Materials for Performance Improvement in Coupled Multilayer Graphene Nanoribbon Interconnects
by Peng Xu, Zhongliang Pan and Zhenhua Tang
Electronics 2019, 8(8), 849; https://doi.org/10.3390/electronics8080849 - 31 Jul 2019
Cited by 9 | Viewed by 4207
Abstract
The ultra-low-k dielectric material replacing the conventional SiO2 dielectric medium in coupled multilayer graphene nanoribbon (MLGNR) interconnects is presented. An equivalent distributed transmission line model of coupled MLGNR interconnects is established to derive the analytical expressions of crosstalk delay, transfer gain, and [...] Read more.
The ultra-low-k dielectric material replacing the conventional SiO2 dielectric medium in coupled multilayer graphene nanoribbon (MLGNR) interconnects is presented. An equivalent distributed transmission line model of coupled MLGNR interconnects is established to derive the analytical expressions of crosstalk delay, transfer gain, and noise output for 7.5 nm technology node at global level, which take the in-phase and out-of-phase crosstalk into account. The results show that by replacing the SiO2 dielectric mediums with the nanoglass, the maximum reduction of delay time and peak noise voltage are 25.202 ns and 0.102 V for an interconnect length of 3000 µm, respectively. It is demonstrated that the ultra-low-k dielectric materials can significantly reduce delay time and crosstalk noise and increase transfer gain compared with the conventional SiO2 dielectric medium. Moreover, it is found that the coupled MLGNR interconnect under out-of-phase mode has a larger crosstalk delay and a lesser transfer gain than that under in-phase mode, and the peak noise voltage increases with the increase of the coupled MLGNR interconnect length. The results presented in this paper would be useful to aid in the enhancement of performance of on-chip interconnects and provide guidelines for signal characteristic analysis of MLGNR interconnects. Full article
(This article belongs to the Special Issue Low-Voltage Integrated Circuits Design and Application)
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9 pages, 3336 KiB  
Article
Channel Length Biasing for Improving Read Margin of the 8T SRAM at Near Threshold Operation
by Ik Joon Chang, Yesung Kang and Youngmin Kim
Electronics 2019, 8(6), 611; https://doi.org/10.3390/electronics8060611 - 30 May 2019
Cited by 3 | Viewed by 3722
Abstract
Reducing a supply voltage in order to minimize power consumption in memory is a major design consideration in this field of study. In static random access memory (SRAM), optimum energy can be achieved by reducing the voltage near the threshold voltage level for [...] Read more.
Reducing a supply voltage in order to minimize power consumption in memory is a major design consideration in this field of study. In static random access memory (SRAM), optimum energy can be achieved by reducing the voltage near the threshold voltage level for near threshold voltage computing (NTC). However, lowering the operational voltage drastically degrades the stability of SRAM. Thus, in conventional 6T SRAM, it is almost impossible to read exact data, even when a small process variation occurs. To address this problem, an 8T SRAM structure is proposed which can be widely used for improving the read stability at lower voltage operation. In this paper, we investigate the channel length biasing effect on the read access transistor of the 8T SRAM in NTC and compare this with 6T SRAM. Read stability can be improved by suppressing the leakage current due to the longer channel length. Simulation results show that, in NTC, up to a 12× read-error reduction can be achieved by the 20 nm channel length biasing in the 8T SRAM compared to 6T SRAM. Full article
(This article belongs to the Special Issue Low-Voltage Integrated Circuits Design and Application)
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18 pages, 4713 KiB  
Article
Design and Analysis of Three-Stage Amplifier for Driving pF-to-nF Capacitive Load Based on Local Q-Factor Control and Cascode Miller Compensation Techniques
by Qi Cheng, Weimin Li, Xian Tang and Jianping Guo
Electronics 2019, 8(5), 572; https://doi.org/10.3390/electronics8050572 - 23 May 2019
Cited by 12 | Viewed by 6281
Abstract
This paper presents a new frequency compensation approach for three-stage amplifiers driving a pF-to-nF capacitive load. Thanks to the cascode Miller compensation, the non-dominant complex pole frequency is extended effectively, and the physical size of the compensation capacitors is also reduced. A local [...] Read more.
This paper presents a new frequency compensation approach for three-stage amplifiers driving a pF-to-nF capacitive load. Thanks to the cascode Miller compensation, the non-dominant complex pole frequency is extended effectively, and the physical size of the compensation capacitors is also reduced. A local Q-factor control (LQC) loop is introduced to alter the Q-factor adaptively when loading capacitance CL varies significantly. This LQC loop decides how much damping current should be injected into the corresponding parasitic node to control the Q-factor of the complex-pole pair, which affects the frequency peak at the gain plot and the settling time of the proposed amplifier in the closed-loop step response. Additionally, a left-half-plane (LHP) zero is created to increase the phase margin and a feed-forward transconductance stage is paralleled to improve the slew rate (SR). Simulated in 0.13-µm CMOS technology, the amplifier is verified to handle a 4-pF-to-1.5-nF (375× drivability) capacitive load with at least 0.88-MHz gain-bandwidth (GBW) product and 42.3° phase margin (PM), while consuming 24.0-µW quiescent power at 1.0-V nominal supply voltage. Full article
(This article belongs to the Special Issue Low-Voltage Integrated Circuits Design and Application)
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Review

Jump to: Editorial, Research

21 pages, 3084 KiB  
Review
Supply-Scalable High-Speed I/O Interfaces
by Woorham Bae
Electronics 2020, 9(8), 1315; https://doi.org/10.3390/electronics9081315 - 15 Aug 2020
Cited by 7 | Viewed by 6029
Abstract
Improving the energy efficiency of computer communication is becoming more and more important as the world is creating a massive amount of data, while the interface has been a bottleneck due to the finite bandwidth of electrical wires. Introducing supply voltage scalability is [...] Read more.
Improving the energy efficiency of computer communication is becoming more and more important as the world is creating a massive amount of data, while the interface has been a bottleneck due to the finite bandwidth of electrical wires. Introducing supply voltage scalability is expected to significantly improve the energy efficiency of communication input/output (I/O) interfaces as well as make the I/Os efficiently adapt to actual utilization. However, there are many challenges to be addressed to facilitate the realization of a true sense of supply-scalable I/O. This paper reviews the motivations, background theories, design considerations, and challenges of scalable I/Os from the viewpoint of computer architecture down to the transistor level. Thereafter, a survey of the state-of-the-arts fabricated designs is discussed. Full article
(This article belongs to the Special Issue Low-Voltage Integrated Circuits Design and Application)
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