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Open AccessArticle

A 16 Gbps, Full-Duplex Transceiver over Lossy On-Chip Interconnects in 28 nm CMOS Technology

1
Department of Engineering & IT, Carinthia University of Applied Sciences, 9524 Villach, Austria
2
Institute of Networked and Embedded Systems, Klagenfurt University, 9020 Klagenfurt, Austria
*
Author to whom correspondence should be addressed.
Electronics 2020, 9(5), 717; https://doi.org/10.3390/electronics9050717
Received: 6 April 2020 / Revised: 23 April 2020 / Accepted: 25 April 2020 / Published: 26 April 2020
(This article belongs to the Special Issue Low-Voltage Integrated Circuits Design and Application)
A high-speed full-duplex transceiver (FDT) over lossy on-chip interconnects is presented. The FDT employs a hybrid circuit to separate the inbound and outbound signals from each other and also performs echo-cancellation with the help of the main and the auxiliary drivers. A hybrid MOS device is utilized for impedance matching and conversion of the received voltage signal into a current signal for amplification. Moreover, a compensation capacitance ( C c ) is used at the output of the main driver to minimize the residual echo signal and achieve a higher data rate. The entire FDT architecture has been designed in TSMC 28 nm CMOS standard process with 0.9 V supply voltage. The performance results validate a 16 Gbps FD operation with a root-mean-square (RMS) jitter of 16.4 ps, and a power efficiency of 0.16 pJ/b/mm over a 5 mm on-chip interconnect without significant effect due to process-voltage-temperature (PVT) variations. To the best knowledge of the authors, this work shows the highest achievable full-duplex data rate, among the solutions reported in the literature to date, yet with low complexity, low layout area of 1581 μ m 2 and competitive power efficiency. View Full-Text
Keywords: bidirectional; CMOS; echo-cancellation; full-duplex; high-speed; low-voltage; on-chip interconnect; simultaneous; transceiver bidirectional; CMOS; echo-cancellation; full-duplex; high-speed; low-voltage; on-chip interconnect; simultaneous; transceiver
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MDPI and ACS Style

Ebrahimi Jarihani, A.; Sarafi, S.; Koeberle, M.; Sturm, J.; Tonello, A.M. A 16 Gbps, Full-Duplex Transceiver over Lossy On-Chip Interconnects in 28 nm CMOS Technology. Electronics 2020, 9, 717. https://doi.org/10.3390/electronics9050717

AMA Style

Ebrahimi Jarihani A, Sarafi S, Koeberle M, Sturm J, Tonello AM. A 16 Gbps, Full-Duplex Transceiver over Lossy On-Chip Interconnects in 28 nm CMOS Technology. Electronics. 2020; 9(5):717. https://doi.org/10.3390/electronics9050717

Chicago/Turabian Style

Ebrahimi Jarihani, Arash; Sarafi, Sahar; Koeberle, Michael; Sturm, Johannes; Tonello, Andrea M. 2020. "A 16 Gbps, Full-Duplex Transceiver over Lossy On-Chip Interconnects in 28 nm CMOS Technology" Electronics 9, no. 5: 717. https://doi.org/10.3390/electronics9050717

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