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Emerging Applications of Recent FPGA Architectures

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A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Microelectronics".

Deadline for manuscript submissions: closed (30 September 2020) | Viewed by 51643

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Prof. Dr. Luis Parrilla

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Universidad de Granada, Departamento de Electrónica y Tecnología de Computadores, Granada, Spain
Interests: FPGAs; cryptography; biosignal processing; computer arithmetic; hardware acceleration; smart instrumentation.
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Prof. Dr. Antonio García

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Departamento de Electrónica y Tecnología de Computadores, Universidad de Granada, 18071 Granada, Spain
Interests: reconfigurable instruments; biosignal processing; cryptography; computer arithmetic
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Prof. Dr. Encarnación Castillo

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Departamento de Electrónica y Tecnología de Computadores, Universidad de Granada, 18071 Granada, Spain
Interests: biosignal processing; FPGA; smart instrumentation; computer arithmetic; cryptography
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

In the IoT era, FGPAs are not only a prototyping platform but the final technology for multiple systems and applications. Nowadays there is a wide typology of FPGAs, from small and low-power devices with application to IoT solutions, to the new high-performance, high-density FPGAs including embedded microprocessors, high-speed memory and high-bandwidth communications, which are mainly intended for hardware acceleration and high-performance computing applications. This broad range of devices is leading to multiple applications, such as IoT systems, power control, hardware acceleration, cryptography, communications, high-performance computing, and so on. This special issue, entitled “Emerging applications of recent FPGA architectures”, is intended to present the latest advances in applications benefiting from new FPGA architectures and features, and to illustrate the wide range of applications where FPGAs can offer a competitive, if not the best, design option.

Prof. Dr. Luis Parrilla
Prof. Dr. Antonio García
Prof. Dr. Encarnación Castillo
Guest Editors

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Keywords

FPGA Architecture
FPGA Application
Programmable Logic Devices
System on Chip
Hardware acceleration
Embedded microprocessor
Digital power control using FPGAs
Cryptographic applications using FPGAs
High-performance computing
IoT systems based on FPGAs

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Published Papers (10 papers)

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Research

24 pages, 8309 KiB

Open AccessArticle

DALI Bridge FPGA-Based Implementation in a Wireless Sensor Node for IoT Street Lighting Applications

by Oscar Osvaldo Ordaz-García, Manuel Ortiz-López, Francisco Javier Quiles-Latorre, José Guadalupe Arceo-Olague, Roberto Solís-Robles and Francisco José Bellido-Outeiriño

Electronics 2020, 9(11), 1803; https://doi.org/10.3390/electronics9111803 - 30 Oct 2020

Cited by 9 | Viewed by 5126

Abstract

Smart lighting systems based on the Digital Addressable Lighting Interface (DALI) protocol are the most suitable for street lighting systems, allowing digital lighting control operations. Unfortunately, the microcontrollers, which are commonly used in the Wireless Sensor Network nodes to control the lamps, do not implement this protocol. The DALI protocol implemented by software in the microcontroller consumes hardware resources (timers), processing time and requires a precise temporal analysis of the application, due to the strict bit times and the Manchester coding that it uses. In this work, the design of a bridge is proposed to free the microcontroller from the implementation of the DALI protocol. The novelty of this work is the implementation of the DALI Bridge in a low-cost Field-Programmable Gate Array (FPGA) with low power consumption. The bridge has been described in the hardware description language following the 1076-93 and 1076.3-97 standards, to guarantee its portability. The results of the synthesis show that a minimum amount of logical and routing resources is used, that the power consumption is in the order of tens of mW, that it has a very small latency time and that it supports a high operating frequency, which allows adding new functions. Its operation is verified by implementing a wireless sensor node using an FPGA of the Lattice Semiconductor iCE40 family. Full article

(This article belongs to the Special Issue Emerging Applications of Recent FPGA Architectures)

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30 pages, 11651 KiB

Open AccessFeature PaperEditor’s ChoiceArticle

10 Clock-Periods Pipelined Implementation of AES-128 Encryption-Decryption Algorithm up to 28 Gbit/s Real Throughput by Xilinx Zynq UltraScale+ MPSoC ZCU102 Platform

by Paolo Visconti, Stefano Capoccia, Eugenio Venere, Ramiro Velázquez and Roberto de Fazio

Electronics 2020, 9(10), 1665; https://doi.org/10.3390/electronics9101665 - 13 Oct 2020

Cited by 12 | Viewed by 8314

Abstract

The security of communication and computer systems is an increasingly important issue, nowadays pervading all areas of human activity (e.g., credit cards, website encryption, medical data, etc.). Furthermore, the development of high-speed and light-weight implementations of the encryption algorithms is fundamental to improve and widespread their application in low-cost, low-power and portable systems. In this scientific article, a high-speed implementation of the AES-128 algorithm is reported, developed for a short-range and high-frequency communication system, called Wireless Connector; a Xilinx ZCU102 Field Programmable Gate Array (FPGA) platform represents the core of this communication system since manages all the base-band operations, including the encryption/decryption of the data packets. Specifically, a pipelined implementation of the Advanced Encryption Standard (AES) algorithm has been developed, allowing simultaneous processing of distinct rounds on multiple successive plaintext packets for each clock period and thus obtaining higher data throughput. The proposed encryption system supports 220 MHz maximum operating frequency, ensuring encryption and decryption times both equal to only 10 clock periods. Thanks to the pipelined approach and optimized solutions for the Substitute Bytes operation, the proposed implementation can process and provide the encrypted packets each clock period, thus obtaining a maximum data throughput higher than 28 Gbit/s. Also, the simulation results demonstrate that the proposed architecture is very efficient in using hardware resources, requiring only 1631 Configurable Logic Blocks (CLBs) for the encryption block and 3464 CLBs for the decryption one. Full article

(This article belongs to the Special Issue Emerging Applications of Recent FPGA Architectures)

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22 pages, 24801 KiB

Open AccessArticle

FPGA-Based Architecture for Sensing Power Consumption on Parabolic and Trapezoidal Motion Profiles

by Victor Montalvo, Adyr A. Estévez-Bén, Juvenal Rodríguez-Reséndiz, Gonzalo Macias-Bobadilla, Jorge D. Mendiola-Santíbañez and Karla A. Camarillo-Gómez

Electronics 2020, 9(8), 1301; https://doi.org/10.3390/electronics9081301 - 13 Aug 2020

Cited by 14 | Viewed by 4327

Abstract

The objective of this work is to design and implement a scalable Field-Programmable Gate Array (FPGA)-based motion control system for DC servo motors using a parabolic velocity profile for industrial applications. The implementation in this device allows the obtaining of a fast, flexible and low-cost system. The system is divided into control, communication and closed-loop coupling. The work also addresses a comparative analysis of the most used profiles, the trapezoidal and parabolic. The comparison is made considering the energy consumption of both profiles. As a consequence of the comparison made, the velocity profile can be selected to reduce production costs by saving energy and reducing wear on machinery. The discrete models of the velocity profiles are obtained through numerical methods that permit the control blocks to be implemented in an FPGA. To reduce maintenance costs and energy consumption in servo mechanisms, the derivation of the acceleration or jerk of the motor is shown. A Graphic User Interface (GUI) is presented, which allows monitoring the position, velocity and angular acceleration of the motor shaft. In addition, the developed interface supports modification of parameters of the final position and maximum velocity in the motor. The delivered current is compared, evaluating its decrease using a parabolic velocity profile. Finally, the experimental results are illustrated. Full article

(This article belongs to the Special Issue Emerging Applications of Recent FPGA Architectures)

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19 pages, 2537 KiB

Open AccessEditor’s ChoiceArticle

High-Level Synthesis Design for Stencil Computations on FPGA with High Bandwidth Memory

by Changdao Du and Yoshiki Yamaguchi

Electronics 2020, 9(8), 1275; https://doi.org/10.3390/electronics9081275 - 8 Aug 2020

Cited by 7 | Viewed by 4388

Abstract

Due to performance and energy requirements, FPGA-based accelerators have become a promising solution for high-performance computations. Meanwhile, with the help of high-level synthesis (HLS) compilers, FPGA can be programmed using common programming languages such as C, C++, or OpenCL, thereby improving design efficiency and portability. Stencil computations are significant kernels in various scientific applications. In this paper, we introduce an architecture design for implementing stencil kernels on state-of-the-art FPGA with high bandwidth memory (HBM). Traditional FPGAs are usually equipped with external memory, e.g., DDR3 or DDR4, which limits the design space exploration in the spatial domain of stencil kernels. Therefore, many previous studies mainly relied on exploiting parallelism in the temporal domain to eliminate the bandwidth limitations. In our approach, we scale-up the design performance by considering both the spatial and temporal parallelism of the stencil kernel equally. We also discuss the design portability among different HLS compilers. We use typical stencil kernels to evaluate our design on a Xilinx U280 FPGA board and compare the results with other existing studies. By adopting our method, developers can take broad parallelization strategies based on specific FPGA resources to improve performance. Full article

(This article belongs to the Special Issue Emerging Applications of Recent FPGA Architectures)

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13 pages, 3783 KiB

Open AccessArticle

A Parallel Timing Synchronization Structure in Real-Time High Transmission Capacity Wireless Communication Systems

by Xin Hao, Changxing Lin and Qiuyu Wu

Electronics 2020, 9(4), 652; https://doi.org/10.3390/electronics9040652 - 16 Apr 2020

Cited by 5 | Viewed by 3528

Abstract

In the past few years, parallel digital signal processing (PDSP) architectures have been intensively studied to fulfill the growing demand of channel capacity in coherent optical communication systems. However, to our knowledge, real-time timing synchronization in such architectures is until now not implemented on a Field Programmable Gate Array (FPGA). In this article, a parallel timing synchronization architecture is proposed. In the architecture, a parallel First In First Out (FIFO) structure based on an index associated rearranging method, and a dual feedback loop based on the Gardner’s algorithm, are adopted. Taking advantages of the FIFO structure, 67% Look Up Table (LUT) is saved in comparison with earlier results, meanwhile the Numerically Controlled Oscillator (NCO) is efficiently improved to meet the FPGA timing requirements for real-time performance. MATLAB simulations are run to evaluate the Bit Error Rate (BER) deterioration of the architecture. The float- and fixed-point simulation results have shown that, The BER deteriorations are less than 0.5 dB and 1 dB, respectively. Further, the implementation of the architecture on a Xilinx XC7VX485T FPGA chip is achieved. A 20 giga bit per second (Gbps) 16 Quadrature Amplitude Modulation (16QAM) real-time system is achieved at the system clock of 159.524 MHz. This work opens a new pathway to improve the transmission capacity in real-time wireless communication systems. Full article

(This article belongs to the Special Issue Emerging Applications of Recent FPGA Architectures)

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23 pages, 1261 KiB

Open AccessArticle

High Level Design of a Flexible PCA Hardware Accelerator Using a New Block-Streaming Method

by Mohammad Amir Mansoori and Mario R. Casu

Electronics 2020, 9(3), 449; https://doi.org/10.3390/electronics9030449 - 7 Mar 2020

Cited by 5 | Viewed by 4696

Abstract

Principal Component Analysis (PCA) is a technique for dimensionality reduction that is useful in removing redundant information in data for various applications such as Microwave Imaging (MI) and Hyperspectral Imaging (HI). The computational complexity of PCA has made the hardware acceleration of PCA an active research topic in recent years. Although the hardware design flow can be optimized using High Level Synthesis (HLS) tools, efficient high-performance solutions for complex embedded systems still require careful design. In this paper we propose a flexible PCA hardware accelerator in Field-Programmable Gate Arrays (FPGA) that we designed entirely in HLS. In order to make the internal PCA computations more efficient, a new block-streaming method is also introduced. Several HLS optimization strategies are adopted to create an efficient hardware. The flexibility of our design allows us to use it for different FPGA targets, with flexible input data dimensions, and it also lets us easily switch from a more accurate floating-point implementation to a higher speed fixed-point solution. The results show the efficiency of our design compared to state-of-the-art implementations on GPUs, many-core CPUs, and other FPGA approaches in terms of resource usage, execution time and power consumption. Full article

(This article belongs to the Special Issue Emerging Applications of Recent FPGA Architectures)

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15 pages, 3034 KiB

Open AccessArticle

LOCOFloat: A Low-Cost Floating-Point Format for FPGAs.: Application to HIL Simulators

by Alberto Sanchez, Angel de Castro, Maria Sofía Martínez-García and Javier Garrido

Electronics 2020, 9(1), 81; https://doi.org/10.3390/electronics9010081 - 1 Jan 2020

Cited by 5 | Viewed by 3775

Abstract

One of the main decisions when making a digital design is which arithmetic is going to be used. The arithmetic determines the hardware resources needed and the latency of every operation. This is especially important in real-time applications like HIL (Hardware-in-the-loop), where a real-time simulation of a plant—power converter, mechanical system, or any other complex system—is accomplished. While a fixed-point gets optimal implementations, using considerably fewer resources and allowing smaller simulation steps, its use is very restricted to very specific applications, as its design effort is quite high. On the other side, IEEE-754 floating-point may have resolution problems in case of the 32-bit version, and excessive hardware usage in case of the 64-bit version. This paper presents LOCOFloat, a low-cost floating-point format designed for FPGA applications. Its key features are soft normalization of the results, using significand and exponent fields in two’s complement. This paper shows the implementation of addition, subtraction and multiplication of the proposed format. Both IEEE-754 versions and LOCOFloat are compared in this paper, implementing a HIL model of a buck converter. Although the application example is a HIL simulator, other applications could take benefit from the proposed format. Results show that LOCOFloat is as accurate as 64-bit floating-point, while reducing the use of DSPs blocks by

84 %

. Full article

(This article belongs to the Special Issue Emerging Applications of Recent FPGA Architectures)

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18 pages, 2462 KiB

Open AccessFeature PaperArticle

Efficient Implementation on Low-Cost SoC-FPGAs of TLSv1.2 Protocol with ECC_AES Support for Secure IoT Coordinators

by Ahmed Mohamed Bellemou, Antonio García, Encarnación Castillo, Nadjia Benblidia, Mohamed Anane, José Antonio Álvarez-Bermejo and Luis Parrilla

Electronics 2019, 8(11), 1238; https://doi.org/10.3390/electronics8111238 - 30 Oct 2019

Cited by 6 | Viewed by 4093

Abstract

Security management for IoT applications is a critical research field, especially when taking into account the performance variation over the very different IoT devices. In this paper, we present high-performance client/server coordinators on low-cost SoC-FPGA devices for secure IoT data collection. Security is ensured by using the Transport Layer Security (TLS) protocol based on the TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 cipher suite. The hardware architecture of the proposed coordinators is based on SW/HW co-design, implementing within the hardware accelerator core Elliptic Curve Scalar Multiplication (ECSM), which is the core operation of Elliptic Curve Cryptosystems (ECC). Meanwhile, the control of the overall TLS scheme is performed in software by an ARM Cortex-A9 microprocessor. In fact, the implementation of the ECC accelerator core around an ARM microprocessor allows not only the improvement of ECSM execution but also the performance enhancement of the overall cryptosystem. The integration of the ARM processor enables to exploit the possibility of embedded Linux features for high system flexibility. As a result, the proposed ECC accelerator requires limited area, with only 3395 LUTs on the Zynq device used to perform high-speed, 233-bit ECSMs in 413 µs, with a 50 MHz clock. Moreover, the generation of a 384-bit TLS handshake secret key between client and server coordinators requires 67.5 ms on a low cost Zynq 7Z007S device. Full article

(This article belongs to the Special Issue Emerging Applications of Recent FPGA Architectures)

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12 pages, 1098 KiB

Open AccessArticle

Zi-CAM: A Power and Resource Efficient Binary Content-Addressable Memory on FPGAs

by Muhammad Irfan, Zahid Ullah and Ray C. C. Cheung

Electronics 2019, 8(5), 584; https://doi.org/10.3390/electronics8050584 - 27 May 2019

Cited by 15 | Viewed by 4880

Abstract

Content-addressable memory (CAM) is a type of associative memory, which returns the address of a given search input in one clock cycle. Many designs are available to emulate the CAM functionality inside the re-configurable hardware, field-programmable gate arrays (FPGAs), using static random-access memory (SRAM) and flip-flops. FPGA-based CAMs are becoming popular due to the rapid growth in software defined networks (SDNs), which uses CAM for packet classification. Emulated designs of CAM consume much dynamic power owing to a high amount of switching activity and computation involved in finding the address of the search key. In this paper, we present a power and resource efficient binary CAM architecture, Zi-CAM, which consumes less power and uses fewer resources than the available architectures of SRAM-based CAM on FPGAs. Zi-CAM consists of two main blocks. RAM block (RB) is activated when there is a sequence of repeating zeros in the input search word; otherwise, lookup tables (LUT) block (LB) is activated. Zi-CAM is implemented on Xilinx Virtex-6 FPGA for the size 64 × 36 which improved power consumption and hardware cost by 30 and 32%, respectively, compared to the available FPGA-based CAMs. Full article

(This article belongs to the Special Issue Emerging Applications of Recent FPGA Architectures)

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15 pages, 3744 KiB

Open AccessArticle

Stereo Matching in Address-Event-Representation (AER) Bio-Inspired Binocular Systems in a Field-Programmable Gate Array (FPGA)

by Manuel Domínguez-Morales, Juan P. Domínguez-Morales, Ángel Jiménez-Fernández, Alejandro Linares-Barranco and Gabriel Jiménez-Moreno

Electronics 2019, 8(4), 410; https://doi.org/10.3390/electronics8040410 - 8 Apr 2019

Cited by 15 | Viewed by 4491

Abstract

In stereo-vision processing, the image-matching step is essential for results, although it involves a very high computational cost. Moreover, the more information is processed, the more time is spent by the matching algorithm, and the more inefficient it is. Spike-based processing is a relatively new approach that implements processing methods by manipulating spikes one by one at the time they are transmitted, like a human brain. The mammal nervous system can solve much more complex problems, such as visual recognition by manipulating neuron spikes. The spike-based philosophy for visual information processing based on the neuro-inspired address-event-representation (AER) is currently achieving very high performance. The aim of this work was to study the viability of a matching mechanism in stereo-vision systems, using AER codification and its implementation in a field-programmable gate array (FPGA). Some studies have been done before in an AER system with monitored data using a computer; however, this kind of mechanism has not been implemented directly on hardware. To this end, an epipolar geometry basis applied to AER systems was studied and implemented, with other restrictions, in order to achieve good results in a real-time scenario. The results and conclusions are shown, and the viability of its implementation is proven. Full article

(This article belongs to the Special Issue Emerging Applications of Recent FPGA Architectures)

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