Next Article in Journal
Tilted-Beam Switched Array Antenna for UAV Mounted Radar Applications with 360° Coverage
Previous Article in Journal
Implementation of SOH Estimator in Automotive BMSs Using Recursive Least-Squares
Previous Article in Special Issue
Zi-CAM: A Power and Resource Efficient Binary Content-Addressable Memory on FPGAs
Open AccessFeature PaperArticle

Efficient Implementation on Low-Cost SoC-FPGAs of TLSv1.2 Protocol with ECC_AES Support for Secure IoT Coordinators

Department of System and Multimedia Architecture, Centre de Développement des Technologies Avancées, Baba Hassen, Algiers 16081, Algeria
LRDSI Laboratory, Department of Electronics, Blida 1 University, Blida 09000, Algeria
Departamento Electrónica y Tecnología de Computadores, Universidad de Granada, 18071 Granada, Spain
Ecole Supérieure d’Informatique, El Harrach, Algiers 16270, Algeria
Departamento Informática, Universidad de Almería, 04120 Almería, Spain
Author to whom correspondence should be addressed.
Electronics 2019, 8(11), 1238;
Received: 7 October 2019 / Revised: 24 October 2019 / Accepted: 26 October 2019 / Published: 30 October 2019
(This article belongs to the Special Issue Emerging Applications of Recent FPGA Architectures)
Security management for IoT applications is a critical research field, especially when taking into account the performance variation over the very different IoT devices. In this paper, we present high-performance client/server coordinators on low-cost SoC-FPGA devices for secure IoT data collection. Security is ensured by using the Transport Layer Security (TLS) protocol based on the TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 cipher suite. The hardware architecture of the proposed coordinators is based on SW/HW co-design, implementing within the hardware accelerator core Elliptic Curve Scalar Multiplication (ECSM), which is the core operation of Elliptic Curve Cryptosystems (ECC). Meanwhile, the control of the overall TLS scheme is performed in software by an ARM Cortex-A9 microprocessor. In fact, the implementation of the ECC accelerator core around an ARM microprocessor allows not only the improvement of ECSM execution but also the performance enhancement of the overall cryptosystem. The integration of the ARM processor enables to exploit the possibility of embedded Linux features for high system flexibility. As a result, the proposed ECC accelerator requires limited area, with only 3395 LUTs on the Zynq device used to perform high-speed, 233-bit ECSMs in 413 µs, with a 50 MHz clock. Moreover, the generation of a 384-bit TLS handshake secret key between client and server coordinators requires 67.5 ms on a low cost Zynq 7Z007S device. View Full-Text
Keywords: TLS; ECC; AES; FPGA; Embedded Linux TLS; ECC; AES; FPGA; Embedded Linux
Show Figures

Figure 1

MDPI and ACS Style

Bellemou, A.M.; García, A.; Castillo, E.; Benblidia, N.; Anane, M.; Álvarez-Bermejo, J.A.; Parrilla, L. Efficient Implementation on Low-Cost SoC-FPGAs of TLSv1.2 Protocol with ECC_AES Support for Secure IoT Coordinators. Electronics 2019, 8, 1238.

Show more citation formats Show less citations formats
Note that from the first issue of 2016, MDPI journals use article numbers instead of page numbers. See further details here.

Article Access Map by Country/Region

Back to TopTop I did now initially check that there shouldn't be