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A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: closed (15 November 2021) | Viewed by 21294

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Prof. Dr. Luis Parrilla Roure

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Departamento de Electrónica y Tecnología de Computadores, Universidad de Granada, 18071 Granada, Spain
Interests: FPGAs; cryptography; biosignal processing; computer arithmetic; hardware acceleration; smart instrumentation
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Special Issue Information

Dear Colleagues,

The expansion of the Internet of Things (IoT) is leading to searches for new low-power solutions in very different contexts and applications. Usually, these solutions must have low-computing and low-memory resources available, while requiring a high connectivity and flexibility. On the other hand, one of the main issues related to IoT deployment is security in communications and hardware. Security solutions based on Public Key Cryptography require high-computing resources, thus it is a challenge to develop high-security hardware systems while maintaining a low power consumption.

Authors are invited to submit regular papers following the JLPEA submission guidelines within the remit of this Special Issue call. Topics include but are not limited to:

Design of low-power cryptographic hardware;
Design of low-power hardware secure systems;
Cryptographic algorithms for low-power implementation.

Prof. Dr. Luis Parrilla Roure
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1800 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

Low-power hardware design
Low-power cryptography
Low-power cryptographic hardware.

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Published Papers (6 papers)

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Research

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18 pages, 413 KiB

Open AccessArticle

Time- and Amplitude-Controlled Power Noise Generator against SPA Attacks for FPGA-Based IoT Devices

by Luis Parrilla, Antonio García, Encarnación Castillo, Salvador Rodríguez-Bolívar and Juan Antonio López-Villanueva

J. Low Power Electron. Appl. 2022, 12(3), 48; https://doi.org/10.3390/jlpea12030048 - 10 Sep 2022

Cited by 2 | Viewed by 2728

Abstract

Power noise generation for masking power traces is a powerful countermeasure against Simple Power Analysis (SPA), and it has also been used against Differential Power Analysis (DPA) or Correlation Power Analysis (CPA) in the case of cryptographic circuits. This technique makes use of power consumption generators as basic modules, which are usually based on ring oscillators when implemented on FPGAs. These modules can be used to generate power noise and to also extract digital signatures through the power side channel for Intellectual Property (IP) protection purposes. In this paper, a new power consumption generator, named Xored High Consuming Module (XHCM), is proposed. XHCM improves, when compared to others proposals in the literature, the amount of current consumption per LUT when implemented on FPGAs. Experimental results show that these modules can achieve current increments in the range from 2.4 mA (with only 16 LUTs on Artix-7 devices with a power consumption density of 0.75 mW/LUT when using a single HCM) to 11.1 mA (with 67 LUTs when using 8 XHCMs, with a power consumption density of 0.83 mW/LUT). Moreover, a version controlled by Pulse-Width Modulation (PWM) has been developed, named PWM-XHCM, which is, as XHCM, suitable for power watermarking. In order to build countermeasures against SPA attacks, a multi-level XHCM (ML-XHCM) is also presented, which is capable of generating different power consumption levels with minimal area overhead (27 six-input LUTS for generating 16 different amplitude levels on Artix-7 devices). Finally, a randomized version, named RML-XHCM, has also been developed using two True Random Number Generators (TRNGs) to generate current consumption peaks with random amplitudes at random times. RML-XHCM requires less than 150 LUTs on Artix-7 devices. Taking into account these characteristics, two main contributions have been carried out in this article: first, XHCM and PWM-XHCM provide an efficient power consumption generator for extracting digital signatures through the power side channel, and on the other hand, ML-XHCM and RML-XHCM are powerful tools for the protection of processing units against SPA attacks in IoT devices implemented on FPGAs. Full article

(This article belongs to the Special Issue Low-Power Hardware Security)

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17 pages, 964 KiB

Open AccessArticle

The Benefits and Costs of Netlist Randomization Based Side-Channel Countermeasures: An In-Depth Evaluation

by Ali Asghar, Andreas Becher and Daniel Ziener

J. Low Power Electron. Appl. 2022, 12(3), 42; https://doi.org/10.3390/jlpea12030042 - 23 Jul 2022

Cited by 1 | Viewed by 2177

Abstract

Exchanging FPGA-based implementations of cryptographic algorithms during run-time using netlist randomized versions has been introduced recently as a unique countermeasure against side channel attacks. Using partial reconfiguration, it is possible to shuffle between structurally different but functionally similar versions of a cryptographic implementation. The resulting varying power profile enhances the resistance against power-based side channel attacks. While side channel leakage is reduced, costs in terms of additional resources and/or lowered throughput are often increased due to the overheads of the required online partial reconfiguration. In this work, we provide an in-depth evaluation of the leakage-area-throughput trade-off. Full article

(This article belongs to the Special Issue Low-Power Hardware Security)

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11 pages, 1847 KiB

Open AccessArticle

FPGA Implementation of Mutual Authentication Protocol for Medication Security System

by Wei-Chen Lin, Po-Kai Huang, Chung-Long Pan and Yu-Jung Huang

J. Low Power Electron. Appl. 2021, 11(4), 48; https://doi.org/10.3390/jlpea11040048 - 12 Dec 2021

Cited by 9 | Viewed by 3487

Abstract

Medication safety administration is a complicated process involving the information of patients, drugs, and data storage. The sensitive data transmitted through wireless sensor networks (WSNs) from Internet of things (IoT) over an insecure channel is vulnerable to several threats and needs proper attention to be secured from adversaries. Taking medication safety into consideration, this paper presents a secure authentication protocol for wireless medical sensor networks. The XOR scheme-based algorithm is applied to achieve the purposes of data confidentiality. The proposed architecture is realized as hardware in a field-programmable gate array (FPGA) device which acts as a secure edge computing device. The performance of the proposed protocol is evaluated and simulated via Verilog hardware description language. The functionality of the proposed protocol is verified using the Altera Quartus II software tool and implemented in the Altera Cyclone II DE2-70 FPGA development module. Furthermore, the output signals from the FPGA are measured in the 16702A logic analyzer system to demonstrate real-time functional verification. Full article

(This article belongs to the Special Issue Low-Power Hardware Security)

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23 pages, 1630 KiB

Open AccessArticle

Design and Validation of Low-Power Secure and Dependable Elliptic Curve Cryptosystem

by Bikash Poudel, Arslan Munir, Joonho Kong and Muazzam A. Khan

J. Low Power Electron. Appl. 2021, 11(4), 43; https://doi.org/10.3390/jlpea11040043 - 12 Nov 2021

Viewed by 2848

Abstract

The elliptic curve cryptosystem (ECC) has been proven to be vulnerable to non-invasive side-channel analysis attacks, such as timing, power, visible light, electromagnetic emanation, and acoustic analysis attacks. In ECC, the scalar multiplication component is considered to be highly susceptible to side-channel attacks (SCAs) because it consumes the most power and leaks the most information. In this work, we design a robust asynchronous circuit for scalar multiplication that is resistant to state-of-the-art timing, power, and fault analysis attacks. We leverage the genetic algorithm with multi-objective fitness function to generate a standard Boolean logic-based combinational circuit for scalar multiplication. We transform this circuit into a multi-threshold dual-spacer dual-rail delay-insensitive logic (

M T D^{3} L

) circuit. We then design point-addition and point-doubling circuits using the same procedure. Finally, we integrate these components together into a complete secure and dependable ECC processor. We design and validate the ECC processor using Xilinx ISE

14.7

and implement it in a Xilinx Kintex-7 field-programmable gate array (FPGA). Full article

(This article belongs to the Special Issue Low-Power Hardware Security)

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18 pages, 6328 KiB

Open AccessArticle

Comprehensive Study of Side-Channel Attack on Emerging Non-Volatile Memories

by Mohammad Nasim Imtiaz Khan, Shivam Bhasin, Bo Liu, Alex Yuan, Anupam Chattopadhyay and Swaroop Ghosh

J. Low Power Electron. Appl. 2021, 11(4), 38; https://doi.org/10.3390/jlpea11040038 - 28 Sep 2021

Cited by 12 | Viewed by 4347

Abstract

Emerging Non-Volatile Memories (NVMs) such as Magnetic RAM (MRAM), Spin-Transfer Torque RAM (STTRAM), Phase Change Memory (PCM) and Resistive RAM (RRAM) are very promising due to their low (static) power operation, high scalability and high performance. However, these memories bring new threats to data security. In this paper, we investigate their vulnerability against Side Channel Attack (SCA). We assume that the adversary can monitor the supply current of the memory array consumed during read/write operations and recover the secret key of Advanced Encryption Standard (AES) execution. First, we show our analysis of simulation results. Then, we use commercial NVM chips to validate the analysis. We also investigate the effectiveness of encoding against SCA on emerging NVMs. Finally, we summarize two new flavors of NVMs that can be resilient against SCA. To the best of our knowledge, this is the first attempt to do a comprehensive study of SCA vulnerability of the majority of emerging NVM-based cache. Full article

(This article belongs to the Special Issue Low-Power Hardware Security)

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Review

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39 pages, 12006 KiB

Open AccessReview

Comprehensive Study of Security and Privacy of Emerging Non-Volatile Memories

by Mohammad Nasim Imtiaz Khan and Swaroop Ghosh

J. Low Power Electron. Appl. 2021, 11(4), 36; https://doi.org/10.3390/jlpea11040036 - 24 Sep 2021

Cited by 12 | Viewed by 4537

Abstract

Several promising non-volatile memories (NVMs) such as magnetic RAM (MRAM), spin-transfer torque RAM (STTRAM), ferroelectric RAM (FeRAM), resistive RAM (RRAM), and phase-change memory (PCM) are being investigated to keep the static leakage within a tolerable limit. These new technologies offer high density and consume zero leakage power and can bridge the gap between processor and memory. The desirable properties of emerging NVMs make them suitable candidates for several applications including replacement of conventional memories. However, their unique characteristics introduce new data privacy and security issues. Some of them are already available in the market as discrete chips or a part of full system implementation. They are considered to become ubiquitous in future computing devices. Therefore, it is important to ensure their security/privacy issues. Note that these NVMs can be considered for cache, main memory, or storage application. They are also suitable to implement in-memory computation which increases system throughput and eliminates von Neumann bottleneck. Compute-capable NVMs impose new security and privacy challenges that are fundamentally different than their storage counterpart. This work identifies NVM vulnerabilities and attack vectors originating from the device level all the way to circuits and systems, considering both storage and compute applications. We also summarize the circuit/system-level countermeasures to make the NVMs robust against security and privacy issues. Full article

(This article belongs to the Special Issue Low-Power Hardware Security)

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