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JLPEA
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Low-Power Computation at the Edge
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Low-Power Computation at the Edge

A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: closed (15 December 2022) | Viewed by 12383

Special Issue Editors

Prof. Dr. Luis Parrilla Roure

E-Mail Website
Guest Editor
Departamento de Electrónica y Tecnología de Computadores, Universidad de Granada, 18071 Granada, Spain
Interests: FPGAs; cryptography; biosignal processing; computer arithmetic; hardware acceleration; smart instrumentation
Special Issues, Collections and Topics in MDPI journals
Prof. Dr. Antonio García

E-Mail Website
Guest Editor
Departamento de Electrónica y Tecnología de Computadores, Universidad de Granada, 18071 Granada, Spain
Interests: reconfigurable instruments; biosignal processing; cryptography; computer arithmetic
Special Issues, Collections and Topics in MDPI journals
Prof. Dr. Encarnación Castillo

E-Mail Website
Guest Editor
Departamento de Electrónica y Tecnología de Computadores, Universidad de Granada, 18071 Granada, Spain
Interests: biosignal processing; FPGA; smart instrumentation; computer arithmetic; cryptography
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

The deployment of the Internet of Things (IoT) and the Industrial Internet of Things (IIoT) is generating new computing paradigms, as lots of small processing units are idle most of the time. As a first approach for taking advantage of all this processing potential, some of the computing required for processing data, acquired by these IoT nodes, has been moved to the nodes themselves, thus elevating so-called edge computing. In this context, it is interesting to explore the transfer of more computing tasks to the edge, emerging new distributed computing applications where the involved nodes are located at different places and interconnected by heterogeneous networks. For this type of applications, low-power processing units are required, such as hardware accelerators, hardware-implemented neural networks, or even cryptoprocessors, to guarantee security of the data being processed at the edge.

Authors are invited to submit regular papers following the JLPEA submission guidelines within the remit of this Special Issue call. Topics of interest include but are not limited to:

  • Design of low-power hardware accelerators for the edge;
  • Design of low-power hardware-implemented neural networks;
  • Cryptographic processors for secure edge computing.

Prof. Dr. Luis Parrilla Roure
Prof. Dr. Antonio García
Prof. Dr. Encarnación Castillo
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1800 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

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Published Papers (4 papers)

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25 pages, 11174 KiB  
Article
DycSe: A Low-Power, Dynamic Reconfiguration Column Streaming-Based Convolution Engine for Resource-Aware Edge AI Accelerators
by Weison Lin, Yajun Zhu and Tughrul Arslan
J. Low Power Electron. Appl. 2023, 13(1), 21; https://doi.org/10.3390/jlpea13010021 - 16 Mar 2023
Cited by 4 | Viewed by 2834
Abstract
Edge AI accelerators are utilized to accelerate the computation in edge AI devices such as image recognition sensors on robotics, door lockers, drones, and remote sensing satellites. Instead of using a general-purpose processor (GPP) or graphic processing unit (GPU), an edge AI accelerator [...] Read more.
Edge AI accelerators are utilized to accelerate the computation in edge AI devices such as image recognition sensors on robotics, door lockers, drones, and remote sensing satellites. Instead of using a general-purpose processor (GPP) or graphic processing unit (GPU), an edge AI accelerator brings a customized design to meet the requirements of the edge environment. The requirements include real-time processing, low-power consumption, and resource-awareness, including resources on field programmable gate array (FPGA) or limited application-specific integrated circuit (ASIC) area. The system’s reliability (e.g., permanent fault tolerance) is essential if the devices target radiation fields such as space and nuclear power stations. This paper proposes a dynamic reconfigurable column streaming-based convolution engine (DycSe) with programmable adder modules for low-power and resource-aware edge AI accelerators to meet the requirements. The proposed DycSe design does not target the FPGA platform only. Instead, it is an intellectual property (IP) core design. The FPGA platform used in this paper is for prototyping the design evaluation. This paper uses the Vivado synthesis tool to evaluate the power consumption and resource usage of DycSe. Since the synthesis tool is limited to giving the final complete system result in the designing stage, we compare DycSe to a commercial edge AI accelerator for cross-reference with other state-of-the-art works. The commercial architecture shares the competitive performance within the low-power ultra-small (LPUS) edge AI scopes. The result shows that DycSe contains 3.56% less power consumption and slight resources (1%) overhead with reconfigurable flexibility. Full article
(This article belongs to the Special Issue Low-Power Computation at the Edge)
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23 pages, 7408 KiB  
Article
Self-Parameterized Chaotic Map for Low-Cost Robust Chaos
by Partha Sarathi Paul, Anurag Dhungel, Maisha Sadia, Md Razuan Hossain and Md Sakib Hasan
J. Low Power Electron. Appl. 2023, 13(1), 18; https://doi.org/10.3390/jlpea13010018 - 13 Feb 2023
Cited by 5 | Viewed by 3182
Abstract
This paper presents a general method, called “self-parameterization”, for designing one-dimensional (1-D) chaotic maps that provide wider chaotic regions compared to existing 1-D maps. A wide chaotic region is a desirable property, as it helps to provide robust performance by enlarging the design [...] Read more.
This paper presents a general method, called “self-parameterization”, for designing one-dimensional (1-D) chaotic maps that provide wider chaotic regions compared to existing 1-D maps. A wide chaotic region is a desirable property, as it helps to provide robust performance by enlarging the design space in many hardware-security applications, including reconfigurable logic and encryption. The proposed self-parameterization scheme uses only one existing chaotic map, referred to as the seed map, and a simple transformation block. The effective control parameter of the seed map is treated as an intermediate variable derived from the input and control parameter of the self-parameterized map, under some constraints, to achieve the desired functionality. The widening of the chaotic region after adding self-parameterization is first demonstrated on three ideal map functions: Logistic; Tent; and Sine. A digitized version of the scheme was developed and realized in a field-programmable gate array (FPGA) implementation. An analog version of the proposed scheme was developed with very low transistor-count analog topologies for hardware-constrained integrated circuit (IC) implementation. The chaotic performance of both digital and analog implementations was evaluated with bifurcation plots and four established chaotic entropy metrics: the Lyapunov Exponent; the Correlation Coefficient; the Correlation Dimension; and Approximate Entropy. An application of the proposed scheme was demonstrated in a random number generator design, and the statistical randomness of the generated sequence was verified with the NIST test. Full article
(This article belongs to the Special Issue Low-Power Computation at the Edge)
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9 pages, 1789 KiB  
Article
Ocelli: Efficient Processing-in-Pixel Array Enabling Edge Inference of Ternary Neural Networks
by Sepehr Tabrizchi, Shaahin Angizi and Arman Roohi
J. Low Power Electron. Appl. 2022, 12(4), 57; https://doi.org/10.3390/jlpea12040057 - 30 Oct 2022
Cited by 2 | Viewed by 2508
Abstract
Convolutional Neural Networks (CNNs), due to their recent successes, have gained lots of attention in various vision-based applications. They have proven to produce incredible results, especially on big data, that require high processing demands. However, CNN processing demands have limited their usage in [...] Read more.
Convolutional Neural Networks (CNNs), due to their recent successes, have gained lots of attention in various vision-based applications. They have proven to produce incredible results, especially on big data, that require high processing demands. However, CNN processing demands have limited their usage in embedded edge devices with constrained energy budgets and hardware. This paper proposes an efficient new architecture, namely Ocelli includes a ternary compute pixel (TCP) consisting of a CMOS-based pixel and a compute add-on. The proposed Ocelli architecture offers several features; (I) Because of the compute add-on, TCPs can produce ternary values (i.e., −1, 0, +1) regarding the light intensity as pixels’ inputs; (II) Ocelli realizes analog convolutions enabling low-precision ternary weight neural networks. Since the first layer’s convolution operations are the performance bottleneck of accelerators, Ocelli mitigates the overhead of analog buffers and analog-to-digital converters. Moreover, our design supports a zero-skipping scheme to further power reduction; (III) Ocelli exploits non-volatile magnetic RAMs to store CNN’s weights, which remarkably reduces the static power consumption; and finally, (IV) Ocelli has two modes, including sensing and processing. Once the object is detected, the architecture switches to the typical sensing mode to capture the image. Compared to the conventional pixels, it achieves an average 10% efficiency on its lane detection power consumption compared with existing edge detection algorithms. Moreover, considering different CNN workloads, our design shows more than 23% power efficiency over conventional designs, while it can achieve better accuracy. Full article
(This article belongs to the Special Issue Low-Power Computation at the Edge)
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17 pages, 3342 KiB  
Article
Designing Energy-Efficient Approximate Multipliers
by Stefania Perri, Fanny Spagnolo, Fabio Frustaci and Pasquale Corsonello
J. Low Power Electron. Appl. 2022, 12(4), 49; https://doi.org/10.3390/jlpea12040049 - 27 Sep 2022
Cited by 2 | Viewed by 3031
Abstract
This paper proposes a novel approach suitable to design energy-efficient approximate multipliers using both ASIC and FPGAs. The new strategy harnesses specific encoding logics based on bit significance and computes the approximate product performing accurate sub-multiplications by applying an unconventional approach instead of [...] Read more.
This paper proposes a novel approach suitable to design energy-efficient approximate multipliers using both ASIC and FPGAs. The new strategy harnesses specific encoding logics based on bit significance and computes the approximate product performing accurate sub-multiplications by applying an unconventional approach instead of using approximate computational modules implementing traditional static or dynamic bit-truncation approaches. The proposed platform-independent architecture exhibits an energy saving of up to 80% over the accurate counterparts and significantly better behavior in terms of accuracy loss with respect to competitor approximate architectures. When employed in 2D digital filters and edge detectors, the novel approximate multipliers lead to an energy consumption up to ~82% lower than the accurate counterparts, which is up to ~2 times higher than that obtained by state-of-the-art competitors. Full article
(This article belongs to the Special Issue Low-Power Computation at the Edge)
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