Search Results (57)

The continuous scaling of microelectronic technology nodes has imposed fundamental physical constraints on conventional floating-gate (FG) non-volatile memory, driving the adoption of charge-trapping memory such as Silicon–Oxide–Nitride–Oxide–Silicon (SONOS) technology. SONOS devices offer advantages in scalability, endurance, and compatibility with advanced CMOS processes, yet their high-temperature reliability remains challenging due to charge loss mechanisms influenced by device structure and material properties. In this work, we systematically evaluate the reliability of two-transistor SONOS memory fabricated using a 28 nm high-K metal gate (HKMG) process. A refined temperature-dependent charge loss model (T-model) is introduced, which, by incorporating a characteristic temperature parameter (T₀) that captures the dynamic shift in activation energy, fundamentally departs from the constant-activation energy assumption of the conventional Arrhenius model. This approach more accurately describes charge retention behavior across a wide temperature range. Experimental results demonstrate excellent device performance, including endurance exceeding 10⁴ program/erase cycles at 85 °C and data retention over 10 years at 85 °C. The T-model shows strong agreement with measured data, providing a physically grounded framework for predicting long-term reliability. This study not only validated a novel charge loss model, providing insights for predicting the failure time of SONOS memory, but also demonstrated that HKMG-integrated SONOS memory exhibits high reliability. Full article

We investigated the radio frequency (RF) performance of AlGaN/GaN high electron mobility transistors (HEMTs) fabricated on silicon carbide substrates, featuring two distinct T-shaped gate structures. A comparative analysis between a silicon nitride (SiN_x)-passivated T-gate and a floating T-gate design reveals significant differences in parasitic capacitance and high-frequency behavior. The floating gate structure effectively reduces fringe capacitance, resulting in improved cut-off frequency (f_T) and maximum oscillation frequency (f_max), achieving f_T = 82.7 GHz and f_max = 80.2 GHz, respectively. These enhancements underscore the critical importance of optimizing gate structures to advance GaN-based HEMTs for high-speed and high-power applications. The findings provide valuable insights for the design of future RF and millimeter-wave (mm-wave) devices. Full article

NO₂ is a toxic gas mainly generated by combustion processes, such as vehicle emissions and industrial activities. It is a key contributor to smog, acid rain, ground-level ozone, and particulate matter, all of which pose serious risks to human health and the environment. Conventional resistive gas sensors, typically based on metal oxide semiconductors, detect NO₂ by resistance modulation through surface interactions with the gas. However, they often suffer from low responsiveness and poor selectivity. This study investigates NO₂ detection using nanoporous zinc oxide thin films integrated into a resistor structure and floating-gate field-effect transistor (FGFET). Both Silvaco-Atlas simulations and experimental fabrication were employed to evaluate sensor behavior under NO₂ exposure. The results show that FGFET provides higher sensitivity, faster response times, and improved selectivity compared to resistor-based devices. In particular, FGFET achieves a detection limit as low as 89 ppb, with optimal performance around 400 °C, and maintains stability under varying humidity levels. The enhanced performance arises from quantum well effects at the floating-gate Schottky contact, combined with NO₂ adsorption on the ZnO surface. These interactions extend the depletion region and confine charge carriers, amplifying conductivity modulation in the channel. Overall, the findings demonstrate that FGFET is a promising platform for NO₂ sensors, with strong potential for environmental monitoring and industrial safety applications. Full article

Nanoparticle floating gate (NPFG) transistors have gained attention as synaptic devices due to their discrete charge storage capability, which minimizes leakage currents and enhances the memory window. In this study, we propose and evaluate a mesh-type floating gate transistor (Mesh-FGT) designed to emulate the characteristics of NPFG transistors. Individual floating gates with dimensions of 3 µm × 3 µm are arranged in an array configuration to form the floating gate structure. The Mesh-FGT is composed of an Al/Pt/Cr/HfO₂/Pt/Cr/HfO₂/SiO₂/SOI (silicon-on-insulator) stack. Threshold voltages (Vth) extracted from the transfer and output curves followed Gaussian distributions with means of 0.063 V (σ = 0.100 V) and 1.810 V (σ = 0.190 V) for the erase (ERS) and program (PGM) states, respectively. Synaptic potentiation and depression were successfully demonstrated in a multi-level implementation by varying the drain current (I_ds) and Vth. The Mesh-FGT exhibited high immunity to leakage current, excellent repeatability and retention, and a stable memory window that initially measured 2.4 V. These findings underscore the potential of the Mesh-FGT as a high-performance neuromorphic device, with promising applications in array device architectures and neuromorphic neural network implementations. Full article

As a critical storage technology, the material selection and structural design of flash memory devices are pivotal to their storage density and operational characteristics. Although van der Waals materials can potentially take over the scaling roadmap of silicon-based technologies, the scaling mechanisms and optimization principles at low-dimensional scales remain to be systematically unveiled. In this study, we experimentally demonstrated that the floating-gate length can significantly affect the memory window characteristics of memory devices. Experiments involving various floating-gate and tunneling-layer configurations, combined with TCAD simulations, were conducted to reveal the electrostatic coupling behaviors between floating gate and source/drain electrodes during shaping of the charge storage capabilities. Fundamental performance characteristics of the designed memory devices, including a large memory ratio (82.25%), good retention (>50,000 s, 8 states), and considerable endurance characteristics (>2000 cycles), further validate the role of floating-gate topological structures in manipulating low-dimensional memory devices, offering valuable insights to drive the development of next-generation memory technologies. Full article

Accurate monitoring of sodium and potassium ions in biological fluids is crucial for diseases related to electrolyte imbalance. Low-dimensional materials such as carbon nanotubes can be used to construct biochemical sensors based on high-performance field effect transistor (FET), but they face the problems of poor device consistency and difficulty in stable and reliable operation. In this work, we mass-produced carbon nanotube (CNT) floating-gate field-effect transistor devices with high uniformity and consistency through micro-/nanofabrication technology to improve the accuracy and reliability of detection without the need for statistical analysis based on machine learning. By introducing waterproof hafnium oxide gate dielectrics on the CNT FET channel, we not only effectively protect the channel area but also significantly improve the stability of the sensor. We have prepared array sensing technology based on CNT FET that can detect potassium, sodium, calcium, and hydrogen ions in artificial cerebrospinal fluid. The detection concentration range is 10 μM–100 mM and pH 3–pH 9, with a sensitivity close to the Nernst limit, and exhibits selective and long-term stable responses. This could help achieve early diagnosis and real-time monitoring of central nervous system diseases, highlighting the potential of this ion-sensing platform for highly sensitive and stable detection of various neurobiological markers. Full article

In this work, floating-gate organic field-effect transistor memory using the n-type semiconductor poly-{[N,N′-bis(2-octyldodecyl) naphthalene-1,4,5,8-bis (dicarbo- ximide)-2,6-dili]-alt-5,5′-(2,2′-bithiophene)} (N2200) as a charge-trapping layer is presented. With the assistance of a technology computer-aided design (TCAD) tool (Silvaco-Atlas), the storage characteristics of the device are numerically simulated by using the carrier injection and Fower–Nordheim (FN) tunneling models. The shift in the transfer characteristic curves and the charge-trapping mechanism after programming/erasing (P/E) operations under different P/E voltages and different pulse operation times are discussed. The impacts of different thicknesses of the tunneling layer on storage characteristics are also analyzed. The results show that the memory window with a tunneling layer thickness of 8 nm is 16.1 V under the P/E voltage of ±45 V, 5 s. After 1000 cycle tests, the memory shows good fatigue resistance, and the read current on/off ratio reaches 10³. Full article

In this paper, we proposed the development of stackable 3D ferroelectric random-access memory (FeRAM), with two select transistors and n capacitors (2TnC), to address scaling limitations for bit density growth and the complicated manufacturing of 3D dynamic random-access memory (DRAM). The proposed 3D FeRAM has a 3D NAND-like architecture, with stacked metal–ferroelectric–metal (MFM) capacitors serving as memory cells in a unit string. A similar manufacturing process is used to achieve a cost-effective process and high bit density for next-generation DRAM applications. The two access transistors, string–select–line (SSL) and ground–select–line (GSL), are perfect string selections. We confirmed that the grounded back gate (GBG) of the proposed architecture can significantly improve the worst disturbance case compared to a floating back gate (FBG) like the 1TnC structure. Also, we confirmed the feasibility of performing the random-access operation during the read operation regardless of the data pattern of the selected string. Full article

An N-bit priority resolver having N inputs and N outputs functions as polling hardware in an embedded system, enabling access to a resource when multiple devices initiate access requests at its inputs which may be located on-chip or off-chip. Subsystems such as data buses, comparators, fixed- and floating-point arithmetic units, interconnection network routers, etc., utilize the priority resolver function. In the literature, there are many transistor-level designs for the priority resolver based on dynamic CMOS logic, some of which are modular and others are not. This article presents a novel gate-level modular design of priority resolvers that can accommodate any number of inputs and outputs. Based on our modular design architecture, small-size priority resolvers can be conveniently combined to form medium- or large-size priority resolvers along with extra logic. The proposed modular design approach helps to reduce the coding complexity compared to the conventional direct design approach and facilitates scalability. We discuss the gate-level implementation of 4-, 8-, 16-, 32-, 64-, and 128-bit priority resolvers based on the direct and modular approaches and provide a performance comparison between these based on the design metrics. According to the modular approach, different sizes of priority resolver modules were used to implement larger-size priority resolvers. For example, a 4-bit priority resolver module was used to implement 8-, 16-, 32-, 64-, and 128-bit priority resolvers in a modular fashion. We used a 28 nm CMOS standard digital cell library and Synopsys EDA tools to synthesize the priority resolvers. The estimated design metrics show that the modular approach tends to facilitate increasing reductions in delay and power-delay product (PDP) compared to the direct approach, especially as the size of the priority resolver increases. For example, a 32-bit modular priority resolver utilizing 16-bit priority resolver modules had a 39.4% reduced delay and a 23.1% reduced PDP compared to a directly implemented 32-bit priority resolver, and a 128-bit modular priority resolver utilizing 16-bit priority resolver modules had a 71.8% reduced delay and a 61.4% reduced PDP compared to a directly implemented 128-bit priority resolver. Full article

Although the von Neumann architecture-based computing system has been used for a long time, its limitations in data processing, energy consumption, etc. have led to research on various devices and circuit systems suitable for logic-in-memory (LiM) computing applications. In this paper, we analyze the temperature-dependent device and circuit characteristics of the floating gate field effect transistor (FGFET) source drain barrier (SDB) and FGFET central shallow barrier (CSB) identified in previous papers, and their applicability to LiM applications is specifically confirmed. These FGFETs have the advantage of being much more compatible with existing silicon-based complementary metal oxide semiconductor (CMOS) processes compared to devices using new materials such as ferroelectrics for LiM computing. Utilizing the 32 nm technology node, the leading-edge node where the planar metal oxide semiconductor field effect transistor structure is applied, FGFET devices were analyzed in TCAD, and an environment for analyzing circuits in HSPICE was established. To seamlessly connect FGFET-based devices and circuit analyses, compact models of FGFET-SDB and -CSBs were developed and applied to the design of ternary content-addressable memory (TCAM) and full adder (FA) circuits for LiM. In addition, depression and potential for application of FGFET devices to neural networks were analyzed. The temperature-dependent characteristics of the TCAM and FA circuits with FGFETs were analyzed as an indicator of energy and delay time, and the appropriate number of CSBs should be applied. Full article

We analyze several factors that affect the linear output range of CMOS image sensors, including charge transfer time, reset transistor supply voltage, the capacitance of integration capacitor, the n-well doping of the pinned photodiode (PPD) and the output buffer. The test chips are fabricated with 0.18 μm CMOS image sensor (CIS) process and comprise six channels. Channels B1 and B2 are 10 μm pixels and channels B3–B6 are 20 μm pixels, with corresponding pixel arrays of 1 × 2560 and 1 × 1280 respectively. The floating diffusion (FD) capacitance varies from 10 fF to 23.3 fF, and two different designs were employed for the n-well doping in PPD. The experimental results indicate that optimizing the FD capacitance and PPD design can enhance the linear output range by 37% and 32%, respectively. For larger pixel sizes, extending the transfer gate (TG) sampling time leads to an increase of over 60% in the linear output range. Furthermore, optimizing the design of the output buffer can alleviate restrictions on the linear output range. The lower reset voltage for noise reduction does not exhibit a significant impact on the linear output range. Furthermore, these methods can enhance the linear output range without significantly amplifying the readout noise. These findings indicate that the linear output range of pixels is not only influenced by pixel design but also by operational conditions. Finally, we conducted a detailed analysis of the impact of PPD n-well doping concentration and TG sampling time on the linear output range. This provides designers with a clear understanding of how nonlinearity is introduced into pixels, offering valuable insight in the design of highly linear pixels. Full article

Hydrogen sulphide (H₂S) is a toxic gas soluble in water, H₂S_aq, as a weak acid. Since H₂S_aq usually originates from the decomposition of faecal matter, its presence also indicates sewage dumping and possible parallel waterborne pathogens associated with sewage. We here present a low footprint (‘frugal’) H₂S_aq sensor as an accessible resource for water quality monitoring. As a sensing mechanism, we find the chemical affinity of thiols to gold (Au) translates to H₂S_aq. When an Au electrode is used as a control gate (CG) or floating gate (FG) electrode in the electric double layer (EDL) pool of an extended gate field effect transistor (EGFET) sensor, EGFET transfer characteristics shift along the CG voltage axis in response to H₂S_aq. We rationalise this by the interface potential from the adsorption of polar H₂S molecules to the electrode. The sign of the shift changes between Au CG and Au FG, and cancels when both electrodes are Au. The sensor is selective for H₂S_aq over the components of urine, nor does urine suppress the sensor’s ability to detect H₂S_aq. Electrodes can be recovered for repeated use by washing in 1M HCl. Quantitatively, CG voltage shift is fitted by a Langmuir-Freundlich (LF) model, supporting dipole adsorption over an ionic (Nernstian) response mechanism. We find a limit-of-detection of 14.9 nM, 100 times below potability. Full article

A novel super-junction (SJ) double-trench metal oxide semiconductor field effect transistor (DT-MOS) is proposed and studied using Synopsys Sentaurus TCAD in this article. The simulation results show that the proposed MOSFET has good static performance and a longer short-circuit withstand time (t_sc). The super-junction structure enables the device to possess an excellent compromise of breakdown voltage (BV) and specific on-resistance (R_on,sp). Under short-circuit conditions, the depletion of p-pillar, p-shield, and floating p regions can effectively reduce saturation current and improve short-circuit capability. The proposed device has minimum gate-drain charge (Q_gd) and gate-drain capacitance (C_gd) compared with other devices. Moreover, the formation of floating p regions will not lead to an increase in process complexity. Therefore, the proposed MOSFET can maintain good dynamic and static performance and short-circuit ability together without increasing the difficulty of the process. Full article

We further simplify the most ‘user-friendly’ potentiometric sensor for waterborne analytes, the ‘extended-gate field effect transistor’ (EGFET). This is accomplished using a ‘bridge’ design, that links two separate water pools, a ‘control gate’ (CG) pool and a ‘floating gate’ (FG) pool, by a bridge filled with agar-agar hydrogel. We show electric communication between electrodes in the pools across the gel bridge to the gate of an LND150 FET. When loading the gel bridge with a sorbent that is known to act as a sensitiser for Cu²⁺ water pollution, namely, the ion exchanging zeolite ‘clinoptilolite’, the bridged EGFET acts as a potentiometric sensor to waterborne Cu²⁺. We then introduce novel sensitisers into the gel bridge, the commercially available resins Puromet^TM MTS9140 and MTS9200, which are sorbents for the extraction of mercury (Hg²⁺) pollution from water. We find a response of the bridged EGFET to Hg²⁺ water pollution, setting a template for the rapid screening of ion exchange resins that are readily available for a wide range of harmful (or precious) metal ions. We fit the potentiometric sensor response vs. pollutant concentration characteristics to the Langmuir–Freundlich (LF) model which is discussed in context with other ion-sensor characteristics. Full article

Artificial intelligence has made people’s demands for computer computing efficiency increasingly high. The traditional hardware circuit simulation method for neural morphology computation has problems of unstable performance and excessive power consumption. This research will use non-volatile flash memory cells that are easy to read and write to build a convolutional neural network structure to improve the performance of neural morphological computing. In the experiment, floating-gate transistors were used to simulate neural network synapses to design core cross-array circuits. A voltage subtractor, voltage follower and ReLU activation function are designed based on a differential amplifier. An Iris dataset was introduced in this experiment to conduct simulation experiments on the research circuit. The IMC circuit designed for this experiment has high performance, with an accuracy rate of 96.2% and a recall rate of 60.2%. The overall current power consumption of the hardware circuit is small, and the current power consumption of the subtractor circuit and ReLU circuit does not exceed 100 µA, while the power consumption of the negative feedback circuit is about 440 mA. The accuracy of analog circuits under the IMC architecture is above 93%, the energy consumption is only about 360 nJ, and the recognition rate is about 12 μs. Compared with the classic von Neumann architecture, it reduces the circuit recognition rate and power consumption while meeting accuracy requirements. Full article