Electrical Characteristics of Mesh-Type Floating Gate Transistors for High-Performance Synaptic Device Applications

Abstract

Nanoparticle floating gate (NPFG) transistors have gained attention as synaptic devices due to their discrete charge storage capability, which minimizes leakage currents and enhances the memory window. In this study, we propose and evaluate a mesh-type floating gate transistor (Mesh-FGT) designed to emulate the characteristics of NPFG transistors. Individual floating gates with dimensions of 3 µm × 3 µm are arranged in an array configuration to form the floating gate structure. The Mesh-FGT is composed of an Al/Pt/Cr/HfO₂/Pt/Cr/HfO₂/SiO₂/SOI (silicon-on-insulator) stack. Threshold voltages (Vth) extracted from the transfer and output curves followed Gaussian distributions with means of 0.063 V (σ = 0.100 V) and 1.810 V (σ = 0.190 V) for the erase (ERS) and program (PGM) states, respectively. Synaptic potentiation and depression were successfully demonstrated in a multi-level implementation by varying the drain current (I_ds) and Vth. The Mesh-FGT exhibited high immunity to leakage current, excellent repeatability and retention, and a stable memory window that initially measured 2.4 V. These findings underscore the potential of the Mesh-FGT as a high-performance neuromorphic device, with promising applications in array device architectures and neuromorphic neural network implementations.

1. Introduction

The rapid growth of information in recent years has highlighted the limitations of existing systems in efficiently processing large datasets, prompting the exploration of various technological solutions [1,2,3]. Traditional von Neumann computing architectures, which transfer data between memory and the central processing unit (CPU), offer versatility and practicality. However, the von Neumann architecture is limited by a memory bus bandwidth bottleneck, which slows data transfer between memory and the CPU, particularly during sequential processing for memory updates [4,5].

To address these limitations, neuromorphic devices have emerged as a promising alternative by configuring neural networks directly in hardware. Neuromorphic devices emulate biological neurons and synapses through mechanisms like spike-based signaling and synaptic weight adjustment, enabling parallel processing operations with low power consumption and high speed [6,7,8].

Typical neuromorphic devices include memristors and field-effect transistors (FETs) [9,10,11,12,13]. Memristors, developed in various forms such as resistive random-access memory (RRAM), phase-change random-access memory (PCRAM), and magnetic random-access memory (MRAM), are considered promising synaptic devices due to their simple structure and suitability for crossbar array (CBA) architectures [14]. However, CBA structures suffer from sneak currents, where current flows in undesired directions, necessitating the integration of three-terminal structures to mitigate these issues. Furthermore, achieving long-term reliability remains challenging due to the degradation of resistance states over time.

In contrast, FETs offer precise control of current flow through gate voltage modulation, effectively eliminating sneak path issues. Additionally, their standardized manufacturing processes facilitate large-scale production and integration. Flash transistors, characterized by non-volatile behavior, can emulate synapses by implementing learning and memory functions through output signal modulation via floating gates [15,16,17,18].

Among floating gate devices, nanoparticle floating gate (NPFG) structures have been developed with a focus on discrete charge trapping. NPFG transistors exhibit superior durability, low power consumption, and multi-level capability compared to continuous (conventional) floating gate transistors. Materials such as gold, quantum dots, aluminum and silicon carbide are employed as nanoparticles, with their charge storage capacity tunability based on material type, size, and density, enabling extensive comparative analyses [19,20,21,22,23,24]. In our previous work, we developed an NPFG device using InP quantum dots and demonstrated excellent performance [25]. However, the non-uniform size and dispersion of quantum dots adversely affect carrier mobility and device reproducibility, and their low thermal stability further compromises device stability at high temperatures. [26,27].

In this study, to address these limitations, the uniform size and dispersion of the floating gate were controlled through photolithography, and the limitations of NPFG were addressed by utilizing platinum, which exhibits high thermal stability.

In addition, by ensuring spatial uniformity and structural precision of the charge storage locations, this work aims to implement a synaptic device with high reproducibility.

This structure presents a unique approach not discussed in the previous literature, namely the regularized spatial control of charge storage regions, and it is meaningful in that it considers both scalability to nanoscale structures and expandability to neuromorphic array architectures. The minimum pattern size achievable using a contact aligner (i-line, 365 nm) was set to 3 μm × 3 μm for each floating gate, which was implemented in a mesh-type arrangement. The detailed structures, processes, and their electrical characteristics are discussed in subsequent sections.

The structure of this paper is organized as follows: In Section 2, we provide a detailed explanation of the experimental methods, including the device structure of the Mesh-FGT, the fabrication process, and the measurement conditions. Section 3 presents the experimental results, such as the program/erase (PGM/ERS) operations identified through electrical characterization, synaptic weight modulation depending on threshold voltage and drain current, and retention characteristics. In Section 4, we discuss the device operation mechanism and its technical significance based on the experimental results and analyze the advantages of the mesh-type structure in terms of reproducibility compared to conventional NPFG devices. Finally, Section 5 summarizes the overall conclusions of this study and suggests future research directions for the structural scalability of the device and its application to neuromorphic systems.

2. Materials and Methods

The fabrication process of the device is shown in Figure 1a. A silicon-on-insulator (SOI) wafer is utilized to minimize electron interactions between devices and reduce leakage current. After cleaning the SOI wafer, unnecessary silicon regions were removed through an etching process, and each device was fabricated in an isolated form on top of the BOX layer. By utilizing the insulating BOX layer of the SOI structure, each device is electrically isolated from the underlying substrate, enabling accurate electrical characterization without interference between devices. The SOI wafer consists of a device (silicon) layer with a resistivity of 8–22 Ω·cm and a thickness of 290 nm, a buried oxide (BOX) layer with a thickness of 1 μm, and a substrate layer with a thickness of 675 μm.

The fabrication process starts with cleaning procedure using acetone, methanol, SPM (sulfuric peroxide mixture), and BOE (buffered oxide etchant, 6:1) solutions. Subsequently, lithography and etching processes are conducted to define the active area. The tunnel oxide, which facilitates electron tunneling, is fabricated by forming a 30 Å thick SiO₂ layer using thermal dry oxidation in a furnace, followed by the deposition of 50 cycles HfO₂ using atomic layer deposition (ALD) method.

The floating gate, serving as the electron storage and erase site, is implemented in a mesh-type structure using chromium (Cr) and platinum (Pt). Image reversal lithography (IR lithography) is employed to pattern the mesh-type floating gates by optimizing UV exposure and development times [28]. A total of 2.5 nm of Cr and 25 nm of Pt are deposited via sputtering, and the mesh pattern is defined using a lift-off process to complete the floating gate. As shown in Figure 1b, the mesh-type floating gate is fabricated with dimensions of 3 μm × 3 μm, acting as separated floating charge storage node under the control gate. We fabricate the mesh-type floating gate due to its durability and multi-level functionality.

The control oxide, which acts as a barrier to prevent electron erasure from the floating gate, is designed to be thicker than the tunnel oxide. This layer was fabricated by depositing 200 cycles of HfO₂ using ALD process. The control gate is then formed by depositing 2.5 nm of Cr and 100 nm of Pt, followed by IR lithography, sputtering, and lift-off processes. Figure 1c shows the SEM image of the manufactured synaptic device with a gate width of 50 μm and a gate length of 3 μm, respectively.

Before n-type phosphorus doping, an etching process is conducted to remove deposited HfO₂ and oxidized SiO₂ in the areas designated for dopant injection. Phosphorus is subsequently introduced into the device using the solid phase diffusion (SPD) process [29,30,31]. Figure 1d shows a schematic of the SPD process and a comparison of sheet resistance according to the temperature and time of RTA (rapid thermal annealing) during the curing process. The RTA temperature and time are chosen as the optimal process conditions to minimize control gate damage and to satisfy a doping concentration of 10¹⁹ cm⁻³ or higher. At an RTA temperature of 800 °C and a duration of 20 min, sheet resistance is measured as 65 Ω/□ and the doping concentration is determined to be 5 × 10¹⁹ cm⁻³ using the four-point probe system and the Hall effect measurement system.

To enhance electrical contact between the probe and the source, drain, and gate during device measurements, the Al pad formation process is performed using IR lithography, sputtering, and lift-off techniques. Finally, an annealing process is performed in a box furnace at 450 °C for 1 h to reduce overall device resistance and restore the crystal structure, completing the device fabrication. All processes were conducted in the cleanroom facility at the Nano Fab of Hallym University.

The electrical performance of the fabricated device was evaluated using the B1500A Semiconductor Device Parameter Analyzer (Keysight Technologies, Santa Rosa, CA, USA), with probes connected to the gate, source, drain, and substrate. The measurement software used was Keysight EasyEXPERT (version 6.4.2312.1715), and the collected data were analyzed and visualized using Microsoft Excel (version 2506) and OriginLab Origin (version 8.5).

Table 1. Voltage applied during program and erase operations. All figures perform operations according to the following table.

	Gate Voltage Vgs	Substrate Voltage Vsub	Source Voltage Vss (Fixed)	Drain Voltage Vds (Fixed)
PGM operation	6 V, 1~10 s	0 V	0 V	0 V
ERS operation	−6 V, 10 s	1~20 V	0 V	0 V

presents the voltage conditions applied during the program (PGM) and erase (ERS) operations. In this study, to effectively represent synaptic weight, the PGM and ERS operations were each repeated 20 times. During the 20-cycle experiment, the ERS operation was conducted by applying a gate voltage (V_gs) of −6 V for 10 s. Additionally, the substrate voltage (V_sub) was incrementally increased by 1 V per cycle, ranging from 1 V to 20 V, for a total of 20 repetitions. The source voltage (V_ss) and drain voltage (V_ds) were maintained at 0 V throughout this process. Conversely, the PGM operation was conducted by applying V_gs of 6 V. This voltage was applied twice at 1 s intervals, increasing from 1 s to 10 s, resulting in a total of 20 repetitions. Throughout this process, V_sub, V_ss, and V_ds were maintained at 0 V.

3. Results

The fundamental operation of the device is analyzed through transfer curves and output curves. In Figure 2a,b, the threshold voltage (Vth) is calculated from the transfer curves and the corresponding transconductance (g_m) with V_ds of 0.1 V applied [32,33]. The Vth in the ERS state was about 0.03 V, while in the PGM state, it was about 1.8 V. The subthreshold swing (SS) was calculated as 113 mV/decade for the ERS state and 110 mV/decade for the PGM state. The device incorporates a composite dielectric layer (HfO₂/SiO₂) and a mesh-type floating gate structure, which result in a measured SS higher than the theoretical limit of 60 mV/decade due to factors such as interface traps and electric field non-uniformity. This increase in SS is interpreted as being caused by structural characteristics of the flash memory device and defects introduced during the fabrication process. Figure 2c shows the output curve for the ERS state, revealing a cut-off region at V_gs of 0 V and a saturation region between 1 and 5 V. Figure 2d illustrates the output curve for the PGM state, showing cut-off regions at V_gs = 0 V and V_gs = 1 V, with saturation confirmed from 2 to 5 V. The gate leakage current ranged from 10⁻¹³ A/μm to 10⁻¹¹ A/μm for both the ERS state and the PGM state, demonstrating excellent insulation properties and suppression of leakage current, as shown in Figure 2e,f.

To verify the stable operation of the Mesh-FGT under appropriate voltage conditions, the channel mobility and Fowler–Nordheim (F–N) tunneling characteristics were evaluated. First, based on the transfer curve shown in Figure 2a, the channel mobility of the Mesh-FGT was calculated. Since the device operates in the linear region at V_ds = 0.1 V, the channel mobility satisfies the following Equation (1):

$$\mu ={\displaystyle \frac{1}{C_{ox}}}·{\displaystyle \frac{L}{W}}·{\displaystyle \frac{1}{V_{ds}}}·\left({\displaystyle \frac{d{I}_{ds}}{d{V}_{gs}}}\right)$$

(1)

$\mu$: channel mobility [units: m²/V∙s or cm²/V∙s];

$C_{ox}$: oxide capacitance per unit area [units: F/m²];

$L$: channel length [units: m];

$W$: channel width [units: m];

$V_{ds}$: drain voltage [units: V];

${\displaystyle \frac{d{I}_{ds}}{d{V}_{gs}}}$: slope of I_ds–V_gs curve [units: S = A/V].

Here, $L$ is 3 μm (3 × 10⁻⁶ m), and $W$ is 50 μm (50 × 10⁻⁶ m). The value of ${\displaystyle \frac{d{I}_{ds}}{d{V}_{gs}}}$ corresponds to the peak point of the mutual conductance ($g_m)$, which is calculated as 9.8236 × 10⁻⁷ S/μm × 50 μm = 4.9118 × 10⁻⁵ S. To determine the oxide capacitance ($C_{ox}$), which is a variable in the channel mobility equation, Figure 3a,b were utilized. Figure 3a shows the stack structure used to extract $C_{ox}$, which shares the same configuration and conditions as the fabricated Mesh-FGT device. Based on this structure, the capacitance–voltage curve was measured using an Agilent 4284A LCR Meter (Keysight Technologies, Santa Rosa, CA, USA), as shown in Figure 3b, and $C_{ox}$ was calculated to be 1.508 × 10⁻¹⁰ F. Given that the electrode area is 200 μm × 200 μm, the areal capacitance $C_{ox}$ is 3.77 × 10⁻³ F/m². Consequently, the channel mobility ($\mu$) is calculated to be 0.007817 m²/V·s, which corresponds to 78.17 cm²/V·s. This value is within the typical range reported for similar devices, suggesting that the Mesh-FGT operates with stable electrical performance.

Figure 3c–e illustrate the Fowler–Nordheim (F–N) tunneling characteristics of the Mesh-FGT and provide insight into the operating voltages for the program (PGM) and erase (ERS) operations. In a flash transistor, the charge stored in the floating gate modulates the channel conductivity by shifting the Vth. This charge is injected or removed through F–N tunneling during the PGM and ERS operations. The stack structure shown in Figure 3c served as the basis for the F–N tunneling evaluation, with Figure 3d,e presenting the corresponding electrical measurements. From the log I–V curve in Figure 3d, it can be observed that F–N tunneling occurs between 4.9 V and 8 V. Beyond this range, dielectric breakdown is evident. This implies that the PGM and ERS operations are feasible within this voltage window, while voltages outside this range are likely to result in device failure or non-operation. Figure 3e, along with the following F–N tunneling Equation (2), was used to closely examine whether the voltage range from 4.9 V to 8 V corresponds to the expected F–N tunneling behavior.

$$\mathit{ln}\left({\displaystyle \frac{I}{V^2}}\right)\propto -{\displaystyle \frac{1}{V}}\left({\displaystyle \frac{8\pi d\sqrt{2m^{*}{\Phi }^3}}{3he}}\right)$$

(2)

$d$: tunnel oxide thickness [units: m];

$m^{*}$: effective mass of electron [units: kg];

$\Phi$: barrier height [units: eV or J];

$h$: Planck’s constant [units: J·s].

From the linear fitting, a negative slope of –80.27 was obtained within the specified voltage range, confirming that the data follows the proportional relationship characteristic of F–N tunneling. Therefore, it can be concluded that the dominant charge transport mechanism in the device is Fowler–Nordheim tunneling. Furthermore, the operating voltages listed in Table 1 (PGM: +6 V, ERS: –6 V) are within a stable range that does not induce dielectric breakdown, indicating reliable device operation.

The synaptic weight of the device is examined by analyzing the changes in Vth and drain current (I_ds) during ERS and PGM operations. During ERS, the increase in current indicates synaptic potentiation, while the decrease in current during PGM reflects synaptic depression [34]. These phenomena are attributed to Fowler–Nordheim (F–N) tunneling, suggesting stable device operation [35,36]. Figure 4a,b demonstrate multi-level synaptic potentiation and depression over 40 cycles, with clear Vth changes. Figure 4c shows that the synaptic connection strength can be adjusted from −0.02 to 2.14 V, highlighting the potential of this device as an artificial synapse. In particular, a noticeable Vth shift is observed during the first PGM and ERS operations, which is attributed to the long voltage pulse duration (1~10 s) that induces significant initial charge injection and removal in the floating gate. To improve control over gradual synaptic weight changes, future experiments will adopt microsecond-scale pulse measurements using the B1500A system. The distribution of Vth was analyzed using Figure 4d, confirming that it follows a Gaussian distribution [37,38,39]. For the ERS state, we can see that the changes in Vth were smaller than for the PGM state, indicating a more centralized distribution. This suggests that the Vth in the ERS state exhibits better reproducibility compared to the PGM state. The Vth in the ERS state exhibited a Gaussian distribution with a mean (μ) of 0.063 V and a standard deviation (σ) of 0.100 V. In the PGM state, the Vth showed a mean of 1.810 V with a standard deviation of 0.190 V. The broader Vth variation in the PGM state is attributed to charge trapping during repeated operations. Additionally, since PGM was performed after full erase measurements, prior stress may have further degraded Vth reproducibility.

Based on the transfer curves shown in Figure 4a,b, synaptic weights were extracted by analyzing the changes in I_ds with respect to different read voltage (V_read) values. The corresponding results are depicted as black curves in Figure 5. The V_read is adjusted to ensure accurate data retrieval by setting a specific V_gs as the reference voltage. In this study, specific values of V_read values (0, 0.5, 1, and 1.5 V) were selected, and the synaptic weights were plotted based on the resulting changes in I_ds, as illustrated in Figure 4.

The long-term objective of this research is to develop synaptic array devices. Achieving this requires not only sufficient I_ds but also significant synaptic weight variation. Therefore, in this study, synaptic weights were analyzed under various conditions by incorporating V_ds as an additional variable alongside V_read, with the results presented in Figure 5. Furthermore, to assess the reliability of the device, its repeatability was evaluated by performing three program/erase (P/E) cycles.

To evaluate synaptic weight based on changes in I_ds, appropriate V_ds and V_read are selected [40]. V_ds values were set to 0.1, 1, 3, and 5 V, taking into account the device characteristics, while V_read values were set to 0, 0.5, 1, and 1.5 V to ensure stable signal acquisition under various conditions.

A total of 484 repeated measurements (121 cycles × 4) were conducted using the initial I_ds as a baseline for each combination of V_ds and V_read. These measurements confirmed that the device accurately represents synaptic potentiation and depression. During repeated measurements, the device demonstrated stable current changes and maintained synaptic connection strength, even after hundreds of cycles. This indicates high durability and reliability, making the device suitable for neuromorphic array designs.

The subsequent goal of this study is to develop neuromorphic array devices capable of dynamically controlling signal transduction between neurons. To achieve this, the properties of a single synaptic device were examined. Under conditions where V_ds = 1 V and V_read = 0.5 V, the device exhibited stable signal transmission and reading characteristics without degradation of synaptic connection strength. The results successfully demonstrated a synaptic current change of more than 10³ times.

In neuromorphic array devices, the ability to perform parallel operations and respond to diverse input signals with multi-level synaptic connection strengths is critical. Therefore, stable and sufficiently high synaptic variation and current values are essential requirements. High synaptic variation precisely controls various signal strengths and effectively emulates the behavior between neurons and synapses. In addition, maintaining sufficiently high current prevents loss of synaptic connection strength, thereby improving signal transmission and ensuring device stability.

Figure 6 illustrates results from additional measurements under identical conditions (V_ds = 1 V, V_read = 0.5 V), showing synaptic weights expressed as changes in Vth and I_ds. The analysis of Vth reveals a change of 1.721 V, ranging from 0.186 V to 1.907 V. For changes in I_ds, the synaptic weights can be precisely adjusted by more than 10³ times, ranging from 10⁻⁹ A/μm to 10⁻⁶ A/μm, without compromising connection strength. This demonstrates the device’s strong potential for application in future array designs.

The retention characteristics of the device were analyzed under these operating conditions [41]. The device’s maximum synaptic potentiation and depression values were evaluated by transfer curves, and changes in the memory window were monitored over a period of 2880 min for each operation. Figure 7a shows the changes in Vth over 2880 min. During synaptic potentiation, Vth increased from –0.2 to 0.13 V, while during synaptic depression it decreased from 2.2 to 1.93 V, resulting in a memory window ranging from approximately 2.4 V to 1.8 V. Figure 7b shows the corresponding I_ds changes over the same period, indicating that a stable current is maintained around 10⁻¹⁰ to 10⁻⁶ A/μm. The retention characteristics presented in this study were measured over a period of two days (2880 min) for both fully programmed and erased states. However, this does not imply that the device operates only for two days. The measurement duration was determined by time constraints associated with the use of the B1500A measurement system in the university cleanroom. As shown in Figure 6, after an initial fluctuation within approximately the first 180 min, both Vth and I_ds remained stable. This trend aligns with the typical retention behavior of non-volatile memory devices. In future work, long-term retention characteristics over several weeks to months will be investigated.

Based on the retention results, gradual changes in Vth and I_ds over time suggest that increasing the thickness of the control oxide film and implementing additional passivation layers would be necessary to prevent electron loss from the floating gate [42,43]. These modifications could further improve device stability and reproducibility.

4. Discussion

Previous studies on NPFG transistors have demonstrated advantages such as multi-level synaptic weight representation and an extended memory window. The NPFG device previously fabricated by our group also exhibited comparable performance [25]. However, it faced limitations in terms of reproducibility. The primary factors contributing to reduced reproducibility are the non-uniform distribution of nanoparticles (NPs) and the challenges associated with size control. To address these issues, this study proposes Mesh-FGT to achieve a more uniform floating gate pattern.

In the proposed structure, individual floating gates with dimensions of 3 μm × 3 μm were arranged in a mesh pattern using a contact aligner, facilitating uniform pattern formation. Furthermore, the size of the floating gates can be readily adjusted through a fabrication process involving IR lithography, sputtering, and lift-off techniques. The memory window was observed to be 2.4 V initially and sustained a value above 1.8 V over a duration of 2880 min.

Despite these advancements, the present design has certain limitations. The individual floating gates implemented in this study have a dimension of approximately 3 μm × 3 μm, posing challenges in forming an effective mesh pattern in transistors at the nanometer scale. Moreover, the current architecture is based on a single transistor, limiting its scalability for neuromorphic applications that require large-scale parallel computation.

To overcome these limitations, future research will proceed in two main directions:

First, future work will focus on reducing the size of individual floating gates to the nanometer scale. Specifically, a 10 nm × 10 nm floating gate mesh structure will be fabricated using electron beam lithography (E-beam lithography). As the floating gate size decreases, the feasibility of Mesh-FGT in nanoscale transistor environments will improve. Additionally, an increased number of floating gates is expected to enhance charge storage capacity, enabling finer synaptic weight representation. These advancements are anticipated to expand the memory window and improve multi-level performance, while also reducing the overall gate area of the device.

Second, building upon the characteristics of the single Mesh-FGT studied here, future research will explore its scalability to an array-based architecture. By constructing 2 × 2, 3 × 3, and 4 × 4 Mesh-FGT arrays, the feasibility of parallel computation in neuromorphic systems will be examined. This expansion aims to assess the potential of Mesh-FGT as a fundamental component in large-scale neuromorphic computing beyond its role as an isolated device. To support this, further studies will involve array-based structural scaling as well as statistical analysis using multiple devices, ensuring reproducibility and consistency across larger systems.

By addressing these research directions, Mesh-FGT has the potential to overcome the reproducibility challenges associated with NPFG transistors, enable integration into nanoscale transistor environments, and serve as a critical element for neuromorphic computation.

5. Conclusions

In this study, we developed the Mesh-FGT and analyzed the electrical characteristics of the device. To address the limitations of conventional quantum dot floating gates, individual floating gates with dimensions of 3 μm × 3 μm was fabricated in a mesh-type configuration using platinum, selected for its high thermal stability. SOI wafers were employed during the fabrication process to minimize leakage current and enhance device stability.

The experimental results showed that the Mesh-FGT effectively controlled synaptic strength through PGM and ERS operations and demonstrated stable electron transport through F–N tunneling. In the retention characteristics, the memory window initially measured 2.4 V and gradually decreased to 1.8 V, which was stably maintained for 2880 min. These findings demonstrate that the Mesh-FGT provides precise control of synaptic connection strength, stable current transmission, and robust retention characteristics, supporting its applicability in neuromorphic array devices. As demonstrated, the Mesh-FGT exhibits stable electrical performance and synaptic behavior, confirming that the primary objective of this study—enhancing reproducibility and overcoming the limitations of conventional NPFG devices through the introduction of a mesh-type floating gate structure—has been successfully achieved.

The main contribution of this work is the proposal and experimental validation of a mesh-type floating gate transistor (Mesh-FGT) structure, fabricated using lithography and sputtering techniques, to overcome the non-uniform charge storage and reproducibility issues observed in conventional quantum dot-based NPFG transistors. Unlike previous NPFG studies, the proposed structure enables stable control of charge storage regions through a well-defined array configuration, providing a foundation for systematic analysis of electrical characteristics based on the size and number of individual floating gates. By employing a platinum floating gate and SOI substrate, the device exhibited enhanced thermal stability and reduced leakage current. However, the current work is limited to single-device characterization. Long-term reliability tests were not included, and further efforts are required to scale down the floating gate size and implement array-level integration for practical neuromorphic applications.

Future research will focus on fabricating smaller individual floating gates with dimensions of 10 nm × 10 nm to further minimize leakage current and expand the memory window. Additionally, array devices will be developed to facilitate the implementation of parallel processing-based neuromorphic neural networks. Through this study, Mesh-FGT is expected to play an important role in the implementation of next-generation artificial synaptic devices.