Search Results (41)

This paper presents a flipped-voltage-follower low-dropout regulator (FVF-LDO) for power supply rejection enhancement and low-power operation in CMOS transimpedance amplifiers for optical receiver applications. The proposed FVF-LDO ensures high stability and reliable regulation over a wide range of load conditions by employing a flipped-voltage follower for fast local feedback and improved power supply rejection, while a super-source follower enhances the transient response through increased current-driving capability. A bandgap reference with a 3-bit trimming DAC is adopted to compensate process variations and support stable LDO operations, achieving a temperature coefficient of 19.6 ppm/°C over a wide range of −25 °C to 125 °C. The FVF-LDO exhibits a 101 mV undershoot under a 100 µA-to-10 mA load step with a 100 ns edge time. When applied to an optoelectronic inverter-based active-feedback transimpedance amplifier (TIA), the regulated supply improves the power supply rejection ratio (PSRR) from −6 dB to −38.3 dB. The proposed optoelectronic TIA realized in a 180 nm CMOS process achieves 67 dBΩ transimpedance gain, 869 MHz bandwidth, 66 dB dynamic range, 6.68 pA/√Hz input-referred noise current spectral density, and 4.68 mW power consumption from a single 1.8 V supply. The proposed TIA chip occupies a core area of 940 × 162 µm². Full article

In this study, an ultra-low-voltage operational transconductance amplifier (OTA) operating from a 0.3 V supply, designed in a 45 nm CMOS process, is presented. To overcome the severe headroom constraints, the design employs a bulk-driven differential input stage combined with a current-reuse strategy, effectively enhancing transconductance while operating all transistors in the subthreshold region. This approach enables a rail-to-rail input common-mode range. A multipath Miller zero cancellation compensation technique ensures stability. The resulting OTA achieves an open-loop gain of 44.2 dB and a remarkable common-mode rejection ratio (CMRR) of 87.5 dB, all while consuming 23.3 nW of power. With a gain–bandwidth product of 9.9 kHz, a power supply rejection ratio (PSRR) of 41.1 dB, and an input noise of 1.0 μV/√Hz, this design is highly suitable for energy-constrained, low-frequency applications such as biomedical sensor interfaces and IoT nodes. Full article

This paper introduces the design of a reference voltage buffer (RVB) for pipelined analog-to-digital converters (ADCs) in a 180 nm CMOS process with a 1.8 V supply voltage. The loop stability of the proposed RVB is verified by the theoretical calculations. The driving capability of the proposed RVB is demonstrated by its large driving current, and the transient response simulation results reveal its impressive speed and precision in the reference voltage settling process. Moreover, the power supply rejection ratio (PSRR) performance indicates that the proposed RVB is insensitive to the variation in power supply voltage, meeting the application requirements for high-speed and high-precision pipelined ADCs. Full article

High-performance low dropout regulator (LDO) chips are core components that provide clean power for high-precision sensors, radio frequency (RF) circuits, low noise amplifiers and other noise-sensitive circuits. In the reported literature, the designed LDO chip has advantages in certain parameters, but it cannot meet all the requirements of a high power supply rejection ratio (PSRR), low output noise and low standby current at the same time, which makes the high-end applications of LDOs greatly limited. In this paper, an LDO chip with high PSRR, low output noise and low standby current has been designed and fabricated. By increasing the loop gain, introducing an improved feedforward path, and adopting isolated power supply, the PSRR of the LDO at different frequency bands is greatly improved. By optimizing the design of the error amplifier (EA) and adding a low-pass filter to filter out the reference noise, the output voltage noise of the LDO is reduced. Within the depletion process and an optimized reference structure, the standby power consumption of the LDO is reduced without damaging the output voltage accuracy. The chip is taped out with SMIC’s 0.18 μm/5 V/BCD process. The measured PSRR of the chip is as high as 95dB at a frequency of 1 kHz, and the high-frequency (1 MHz) PSRR is above 45 dB. The amplitude of integrated output noise is below 5.4 μVrms within the frequency range of 10 Hz to 100 KHz. When the load current is zero, the measured standby current is less than 400 nA. The test results indicate that the chip has excellent performance in terms of PSRR, output noise and standby power consumption. Full article

This paper introduces an enhanced bandgap reference (BGR) design, addressing the shortcomings of traditional circuits, such as significant temperature drift, limited power-supply rejection, and inadequate load-driving capacity. The proposed design incorporates a symmetric folded common-emitter–common-base BJT amplifier with MOS-assisted biasing, employed in the proposed BGR, enforcing branch voltage symmetry to effectively suppress intrinsic offset caused by structural mismatch. By reducing the amplifier input offset, the circuit achieves improved reference voltage stability, a lower temperature coefficient (TC), and an enhanced power-supply rejection ratio (PSRR). Additionally, a negative-feedback adaptive current-adjustment driver is implemented to dynamically adjust the output current in response to real-time load changes. This method bolsters the load-driving capability and maintains a stable reference output across varying load conditions. The circuit was simulated using a 0.18 μm BCD process, revealing that with a 3.3 V supply voltage, the BGR produces a stable output voltage of 2.5 V, with a TC of $2.372\times {10}^{-6}$ °C⁻¹. The simulated PSRR is −114.2 dB at DC and −62.07 dB at 1 kHz. Moreover, under a 3.3 V supply, sweeping the load capacitance from 0.1 μF to 100 μF demonstrates that the reference voltage remains consistently regulated at 2.5 V, confirming its excellent load tolerance and output stability. Full article

A 3.0 V bandgap reference (BGR) for battery management integrated circuit (BMIC) is presented, achieving a low temperature coefficient (TC) and a high power supply rejection ratio (PSRR). Precision is enhanced through two techniques: (1) a base current correction technique eliminates errors from the bipolar junction transistor (BJT) base current, and (2) a high-order temperature compensation circuit counteracts the inherent nonlinearity of the BJT’s base-emitter voltage (V_BE). Furthermore, an improved flipped voltage follower (FVF) pre-regulation structure is integrated for efficient power supply noise suppression. The circuit is designed based on a 180 nm BiCMOS process, occupying a layout area of 0.0459 mm². Post-layout simulation results demonstrate that the BGR achieves a temperature coefficient of 1.59 ppm/°C over the −40 °C to 125 °C temperature range. Within a supply voltage range of 4.7 V to 5.3 V, the line regulation is 0.00058 mV/V. At a 5.0 V supply voltage, the quiescent current is 23 μA, and the PSRR is −128.89 dB@1 Hz and −102.9 dB@1 kHz. Full article

Temperature is a crucial indicator in monitoring industrial operations. Two-wire temperature transmitters, known for their precise measurements, are extensively used in sectors like crude oil extraction, refining, and fine chemicals. These transmitters can handle a maximum input voltage of 36 V and output a current signal up to 20 mA, enhancing resistance to electromagnetic interference and line noise while improving system compatibility and safety. In contrast, traditional low-dropout linear regulators (LDOs) typically have an input voltage below 6 V and suffer from limitations such as low power supply rejection ratio (PSRR), inadequate current driving capability, and significant temperature drift. This paper proposes a wide-input-range LDO with enhanced output accuracy and digital trimming, designed using the 180 nm BCD process. It incorporates dynamic mismatch compensation, digital trimming, and a strong-drive buffer, achieving a broad input voltage range and high PSRR with minimal temperature drift. The input voltage spans 6 V to 60 V, the output voltage is 1.8 V, and the PSRR reaches 124.5 dB. Across a temperature range of −40 °C to 130 °C, the maximum output voltage error is only 0.3%. This makes it highly suitable for high-precision circuit power supplies in industrial process control. Full article

To meet the requirements of integrated accelerometers for a high-precision reference voltage under wide supply voltage range, high current drive capability, and low power consumption, this paper presents a bandgap reference operational amplifier (op-amp) circuit implemented in CMOS/BiCMOS technology. The proposed design employs a folded-cascode input stage, a push–pull Class-AB output stage, an adaptive output switching mechanism, and a composite frequency compensation scheme. In addition, overcurrent protection and low-frequency noise suppression techniques are incorporated to balance low static power consumption with high load-driving capability. Simulation results show that, under the typical process corner (TT), with VDD = 3 V and T = 25 °C, the op-amp achieves an output swing of 0.2 V~2.8 V, a low-frequency gain of 102~118 dB, a PSRR of 90 dB at 60 Hz, overcurrent protection of ±25 mA, and a phase margin exceeding 48.8° with a 10 μF capacitive load. Across the entire supply voltage range, the static current remains below 150 μA, while maintaining a line regulation better than 150 μV/V and a load regulation better than 150 μV/mA. These results verify the feasibility of achieving both high drive capability and high stability under stringent power constraints, making the proposed design well-suited as a bandgap reference buffer stage for integrated accelerometers, with strong engineering practicality and potential for broad application. Full article

In loop-powered 4–20 mA transmitter systems, sensors like temperature, pressure, flow, and gas sensors are chosen based on specific application requirements. These systems are widely adopted in high-precision measurement scenarios, including industrial automation, process control, and environmental monitoring. The transmitter requires a high-performance analog front end (AFE) for precise amplification and signal conditioning. This paper presents a low-noise instrumentation amplifier (IA) for high-precision transmitter front ends, featuring a Successive Approximation Register (SAR)-assisted offset calibration architecture. The proposed structure integrates a chopper current-feedback instrumentation amplifier (CFIA) with an automatic offset calibration loop (AOCL), significantly suppressing internal offset errors and enabling high-accuracy signal acquisition under stringent power and environmental temperature constraints. The designed amplifier provides four selectable gain settings, covering a range from ×32 to ×256. Fabricated in a 0.18 μm CMOS process, the CFIA operates at a 1.8 V supply voltage, consumes a static current of 182 μA, and achieves an input-referred noise as low as 20.28 nV/√Hz at 1 kHz, with a common-mode rejection ratio (CMRR) up to 122 dB and a power-supply rejection ratio (PSRR) up to 117 dB. Experimental results demonstrate that the proposed amplifier exhibits excellent performance in terms of input-referred noise, offset voltage, PSRR, and CMRR, making it well-suited for front-end detection in field instruments that require direct interfacing with measured media. Full article

The rapid advancement of electronic technology demands circuit designs that minimize power consumption while maximizing performance. The power supply rejection ratio (PSRR) is a critical metric for quantifying an amplifier’s ability to suppress supply noise, yet accurately predicting PSRR in high-frequency domains and complex multi-stage architectures is increasingly challenging. In this work, we introduce a new framework for PSRR prediction that overcomes these limitations. Leveraging a simplified circuit abstraction based on Thevenin’s theorem, we reduced multi-stage operational amplifiers to “black-box” models—collapsing intricate small-signal networks into a tractable form without sacrificing accuracy. Building on this foundation, we proposed the Power-Supply Rejection Gain-Bandwidth (PGB) metric, which concisely captures the trade-off between an amplifier’s DC PSRR and the frequency range over which that rejection is effective. Using PGB, designers gain an intuitive figure-of-merit for early-stage optimization of PSRR. We validated the efficacy of the combined black-box modeling and PGB approach through detailed case studies, including a 180 nm CMOS two-stage op-amp design. These findings confirmed that the proposed black box plus PGB framework can reliably guide the design of analog circuits with stringent PSRR requirements. Full article

Reverberation is the primary interference of active detection. Therefore, the effective suppression of reverberation is a prerequisite for reliable signal processing. Existing dereverberation methods have shown effectiveness in specific scenarios. However, they often struggle to exploit the distinction between target echo and reverberation, especially in complex, dynamically changing underwater environments. This paper proposes a novel dereverberation network, ERCL-AttentionNet (Echo–Reverberation Complementary Learning Attention Network). We use the Continuous Wavelet Transform (CWT) to extract time–frequency features from the received signal, effectively balancing the time and frequency resolution. The real and imaginary parts of the time–frequency matrix are combined to generate attention representations, which are processed by the network. The network architecture consists of two complementary UNet models sharing the same encoder. These models independently learn target echo and reverberation features to reconstruct the target echo. An attention mechanism further enhances performance by focusing on target information and suppressing irrelevant disturbances in complex environments. Experimental results demonstrate that our method achieves a higher Peak-to-Average Signal-to-Reverberation Ratio (PSRR), Structural Similarity Index (SSIM), and Peak-to-Average Ratio (PAR) of cross-correlation while effectively preserving key time–frequency features, compared to traditional methods such as autoregressive (AR) and singular value decomposition (SVD). Full article

Energy-efficient integrated circuits require scaled-down supply voltages, posing challenges for analog design, particularly for operational transconductance amplifiers (OTAs) essential in high-accuracy CMOS feedback systems. Below 1 V, gate-driven OTAs are limited in common-mode input range and minimum supply voltage. This work investigates CMOS Bulk-Driven (BD) sub-threshold techniques as an efficient alternative for ultra-low voltage (ULV) and ultra-low power (ULP) designs. Although BD overcomes MOS threshold voltage limitations, historical challenges like lower transconductance, latch-up, and layout complexity hindered its use. Recent advancements in CMOS processes and the need for ULP solutions have revived industrial interest in BD. Through theoretical analysis and computer simulations, we explore BD topologies for ULP OTA input stages, classifying them as tailed/tail-less and class A/AB, evaluating their effectiveness for robust analog design, while offering valuable insights for circuit designers. Full article

A programmable gain amplifier (PGA) is commonly used to optimize the input dynamic range of high-performance systems such as headphones and biomedical sensors. But PGA is rather sensitive to electromagnetic interference (EMI), which limits the precision of these systems. Many capacitor-less low-dropout regulator (LDO) schemes with high power supply rejection have been proposed to act as the independent power supply for PGA, which consumes additional power and area. This paper proposed a PGA with a high power supply rejection ratio (PSRR) and low power consumption, which serves as the analog front-end amplifier in the 20-bit sigma-delta ADC. The PGA is a two-stage amplifier with hybrid compensation. The first stage is the recycling folded cascode amplifier with the gain-boost technique, while the second stage is the class-AB output stage. The PGA was implemented in the 0.18 μm CMOS technology and achieved a 9.44 MHz unity-gain bandwidth (UGBW) and a 57.8° phase margin when driving the capacitor of 5.9 pF. An optimum figure-of-merit (FoM) value of 905.67 has been achieved with the proposed PGA. As the front-end amplifier of a high-precision ADC, it delivers a DC gain of 162.1 dB, the equivalent input noise voltage of 301.6 nV and an offset voltage of 1.61 μV. Within the frequency range below 60 MHz, the measured PSRR of ADC is below −70 dB with an effective number of bits (ENOB), namely 20 bits. Full article

A split-voltage amplifier architecture is proposed which improves the power efficiency compared to a conventional implementation. The approach is verified with a prototype fabricated in 0.35 µm CMOS technology using lateral bipolar input transistors. It achieves a measured DC gain of 105 V/V, a differential AC gain of 40.3 dB with a bandwidth of 55 kHz, a CMRR of approximately 75 dB, and a PSRR of 55 dB. The input-referred noise is 7 nV/√Hz and 923 nVrms integrated from 100 Hz to 10 kHz, resulting in a Noise Efficiency Factor (NEF) of 2.84 and a Power Efficiency Factor (PEF) of 18.3. The split-voltage configuration improves power efficiency by nearly 25% compared to a full voltage supply and maintains a small area design. Action potentials of the medial and lateral giant fiber of an earthworm are recorded as an example application. Full article

In this work, we introduce the design of a 16-channel in-pixel neural analog front end that employs a current-based summing approach to establish a common-mode feedback loop. The primary aim of this novel structure is to enhance both the system common-mode rejection ratio (SCMRR) and the common-mode interference (CMI) range. Compared to more conventional designs, the proposed front end utilizes DC-coupled inverter-based main amplifiers, which significantly reduce the occupied on-chip area. Additionally, the current-based implementation of the CMFB loop obviates the need for voltage buffers, replacing them with simple common-gate transistors, which, in turn, decreases both area occupancy and power consumption. The proposed architecture is further examined from an analytical standpoint, providing a comprehensive evaluation through design equations of its performance in terms of gain, common-mode rejection, and noise power. A 50 $\mathsf{\mu }$m × 65 $\mathsf{\mu }$m compact layout of the pixel amplifiers that make up the recording channels of the front end was designed using a 180 nm CMOS process. Simulations conducted in Cadence Virtuoso reveal an SCMRR of 80.5 dB and a PSRR of 72.58 dB, with a differential gain of 44 dB and a bandwidth that fully encompasses the frequency range of the bio-signals that can be theoretically captured by the neural probe. The noise integrated in the range between 1 Hz and 7.5 kHz results in an input-referred noise (IRN) of 4.04 $\mathsf{\mu }{V}_{rms}$. Power consumption is also tested, with a measured value of 3.77 $\mathsf{\mu }$W per channel, corresponding to an overall consumption of about 60 $\mathsf{\mu }$W. To test its robustness with respect to PVT and mismatch variations, the front end is evaluated through extensive parametric simulations and Monte Carlo simulations, revealing favorable results. Full article