A 0.3 V Ultra-Low-Power Bulk-Driven Current-Reuse OTA for Batteryless Applications

Abstract

In this study, an ultra-low-voltage operational transconductance amplifier (OTA) operating from a 0.3 V supply, designed in a 45 nm CMOS process, is presented. To overcome the severe headroom constraints, the design employs a bulk-driven differential input stage combined with a current-reuse strategy, effectively enhancing transconductance while operating all transistors in the subthreshold region. This approach enables a rail-to-rail input common-mode range. A multipath Miller zero cancellation compensation technique ensures stability. The resulting OTA achieves an open-loop gain of 44.2 dB and a remarkable common-mode rejection ratio (CMRR) of 87.5 dB, all while consuming 23.3 nW of power. With a gain–bandwidth product of 9.9 kHz, a power supply rejection ratio (PSRR) of 41.1 dB, and an input noise of 1.0 μV/√Hz, this design is highly suitable for energy-constrained, low-frequency applications such as biomedical sensor interfaces and IoT nodes.

1. Introduction

As semiconductor process technology continues to advance, the size of transistors such as Metal Oxide Semiconductor Field-effect Transistors (MOSFETs) is becoming smaller. This reduction in size translates into a shorter channel length, thereby lowering the maximum voltage that the MOSFET channel can tolerate. In other words, in more advanced nodes, a lower supply voltage must be used to prevent the MOSFET from being damaged by excessive voltages. This whole phenomenon is known as transistor scaling [1]. Nevertheless, the threshold voltage ($V_{th}$) does not scale at the same rate as the supply voltage $V_{DD}$, resulting in a reduced overdrive voltage ($V_{DD}-V_{th}$) and consequently limited voltage headroom for circuit operation [2]. In integrated systems, amplifiers, including operational amplifiers and operational transconductance amplifiers, typically dominate the overall power consumption. Conventional amplifier designs bias their transistors in the saturation region to achieve high gain [3]. Although saturation provides higher gain, it also demands higher voltage and current. As the supply voltage continues to decrease, certain conventional amplifier designs may no longer have adequate voltage headroom to operate properly. Consequently, in future low-power circuits. It may become increasingly difficult to maintain the traditional saturation operation.

On the other hand, with the rapid development of Internet of Things (IoT) applications and portable devices, the design of ultra-low-voltage (ULV) circuits has received increasing attention. In recent years, a number of ULV amplifier designs have been proposed [4,5,6,7,8,9,10], with a growing number operating at sub-0.5 V supply voltages. Sub-0.5 V OTAs are typically based on bulk-driven (BD) transistors. Unlike conventional gate-driven transistors, BD transistors use the bulk terminal as the input, which enables control over and reduction in the threshold voltage [11]. Moreover, the bulk terminal provides a means for common-mode control, which relaxes input-range limitations and allows the input common-mode voltage to be extended without relying on a conventional tail current source, thereby supporting rail-to-rail operation [12]. Several advanced sub-0.5 V OTA designs have been presented in the recent literature. In [13], a three-stage sub-0.5 V OTA employing pseudodifferential input was demonstrated. Fabricated using a 65 nm process, the design achieves a gain–bandwidth product (GBW) in the megahertz range, which is highly competitive for ULV OTAs. In [14], A bulk-driven four-stage OTA operating at 0.3 V has been reported to achieve >116 dB DC gain and rail-to-rail dynamic range with nW power consumption for ultra-low-voltage analog systems. More recent innovations have focused on hybrid compensation and positive feedback to overcome the inherent gain–bandwidth trade-offs of ULV circuits. The design in [15] introduces a 0.3 V bulk-driven OTA that integrates partial positive feedback with a hybrid frequency compensation scheme, combining current-buffer and Miller techniques. Implemented in a 65 nm CMOS process, this amplifier achieves a DC gain of 61.7 dB and a GBW of 12.7 kHz, all while consuming a mere 23.7 nW of power. For applications prioritizing nanowatt-level power budgets, the 0.4 V bulk-driven single-stage OTA presented in [16] offers a compelling solution. Fabricated in a 180 nm CMOS process, it employs replica biasing and positive feedback for gain enhancement, achieving a gain of approximately 75 dB with an extraordinarily low power consumption of just 1.8 nW.

Biomedical applications represent another domain that can significantly benefit from ULV OTA. Owing to their low-frequency characteristics and stringent power consumption requirements, ULV circuits are well-suited for biomedical devices. For instance, in Gm–C filters commonly used in electrocardiogram (ECG) and electroencephalogram (EEG) signal conditioning, the OTA serves as the core building block. In [17], a digitally programmable OTA was proposed that achieves a tuning range from 114 Hz to 12 MHz at a supply voltage of 1.2 V by employing three parallel paths corresponding to different frequency ranges. The OTA employed in [17] was proposed in [18]. By incorporating three linearization techniques, source degeneration, double differential pairs, and adaptive biasing. The design achieves a third-order harmonic distortion lower than −65 dB in Gm-C filter applications. Moreover, a low-power Gm–C filter was proposed in [19]. By employing source degeneration and a flipped-voltage follower, the design achieves a linear input range of ±0.8 V under a ±0.9 V supply voltage. In addition, [20] presents a programmable low-$g_m$ OTA for Gm-C filter applications, in which a low-pass filter implemented using a programmable OTA achieves a cutoff frequency range from 16 Hz to 971 Hz with an ultra-low power consumption of 209.8 nW. Similar digitally programmable OTA designs have also been reported in [21], targeting various low-power wireless communication applications. In [22], a 0.4 V current-controlled ring oscillator was proposed, in which a ULV OTA is employed for bias generation. By operating MOSFETs in the subthreshold region, the design achieves a low power consumption of 10.23 μW, making it well-suited to implantable medical devices, battery-less systems, and other applications with stringent power constraints. More importantly, the ring oscillator presented in [23] adopts a fully digital architecture and also utilizes transistors biased in the subthreshold region, demonstrating that subthreshold operation can be effectively applied in low-power digital circuits as well. To summarize, the suitability of the proposed OTA for various low-power applications is illustrated in Figure 1.

This paper presents a 0.3 V ULV OTA designed to address the stringent demands of energy-harvesting and battery-less systems. At such low supply voltages, conventional design techniques face significant challenges due to threshold voltage limitations and reduced intrinsic gain. To overcome these obstacles, the proposed OTA employs a bulk-driven, gain-boosted input stage [24] operating in the subthreshold region, which removes the threshold voltage from the signal path and maximizes the input common-mode range. This is combined with a current-reuse technique that enhances the effective transconductance, and consequently, the gain–bandwidth product (GBW) without increasing quiescent current consumption. By reusing the bias current, the circuit achieves superior power efficiency, a critical metric in ULV/ULP design where every nanoamp must be utilized effectively.

While bulk-driven (BD) input stages and current-reuse techniques have been individually explored in prior works, their integration introduces a specific challenge related to frequency stability. The auxiliary branch used for current reuse, while boosting transconductance, inherently shifts the non-dominant pole to a lower frequency. This exacerbates phase-margin degradation, particularly under the large capacitive loads common in low-power sensor interfaces. To address this without the area and power penalties of simply increasing compensation capacitance, the design adopts a Multipath Miller Zero-Cancellation Compensation (MMZCC) scheme [25]. This technique creates a left-half-plane zero that effectively cancels the phase lag introduced by the shifted pole, preserving robust stability.

Previous works have addressed only isolated aspects of this design trade-off. For instance, the work in [26] focused on compensation within a BD architecture but did not consider the transconductance enhancement from a current-reuse auxiliary branch. Conversely, studies such as [27,28] demonstrated current reuse to improve transconductance efficiency but failed to explicitly compensate for the resulting downward shift in the non-dominant pole using techniques like MMZCC. In the proposed OTA, the current-reuse branch is intentionally introduced to maximize effective transconductance under 0.3 V subthreshold operation, while MMZCC is simultaneously employed to counteract the associated stability risks. The novelty of this work, therefore, lies in the co-optimized integration of these techniques within a single low-voltage architecture. This holistic approach enables stable operation, superior power efficiency, and near rail-to-rail output swing, making the design highly suitable for the ultra-tight power budgets of modern energy-harvesting applications.

The remaining sections of this work are organized as follows. Section 2 reviews subthreshold MOSFET operation and compares various ULV OTA topologies. Section 3 details the proposed OTA architecture together with the associated design rationale. Section 4 presents the simulation results, followed by concluding remarks in Section 5.

2. ULV OTA Review

This section is organized into two main sub-sections. Section 2.1 presents the operating principles of MOSFETs in the subthreshold region, including the underlying physical mechanisms and the corresponding drain current equations. Section 2.2 compares nineteen subthreshold OTA designs employing different topologies and summarizes their advantages, disadvantages, and performance-enhancement techniques in Table 1.

2.1. Subthreshold Principle

As shown in Figure 2a, a MOSFET typically operates in three regions: the cutoff region ($\left|V_{GS}\right|<\left|V_{th}\right|$), the linear/triode region ($\left|V_{GS}\right|\ge \left|V_{th}\right|, \left|V_{DS}\right|\le \left|V_{GS}\right|-\left|V_{th}\right|$), and the saturation region ($\left|V_{GS}\right|\ge \left|V_{th}\right|, \left|V_{DS}\right|\ge \left|V_{GS}\right|-\left|V_{th}\right|$), where $V_{GS}$ is the gate to the source voltage, $V_{th}$ is the threshold voltage, and $V_{DS}$ is the drain to source voltage [29]. When $V_{GS}$ is lower than $V_{th}$, the MOSFET is in the cutoff region, and theoretically, the drain to source current $I_{DS}$ should be zero. In practice, under weak-inversion conditions, a small current still exists even when the transistor is nominally turned off. This region with small $I_{DS}$ is referred to as the subthreshold region. As illustrated by the energy-band diagram of a p-type MOSFET in Figure 2b, the surface potential shifts such that the conduction band approaches the Fermi level more closely than the valence band. As a result, the surface of the p-type semiconductor effectively becomes a lightly doped n-type semiconductor. Consequently, a very thin inversion layer is formed at the surface [30]. Carrier diffusion through this weak inversion layer enables source-to-drain current flow even when the device operates in the subthreshold region.

The drain current $I_{DS}$ under subthreshold operation is described by the expression given in (1) [31]:

$$I_{DS}=0.1{\displaystyle \frac{W}{L}}{e}^{{\displaystyle \frac{q(V_{GS}-V_{th})}{\eta kT}}}$$

(1)

where $\eta$ is the charge factor in the subthreshold region, and $0.1{\displaystyle \frac{W}{L}}$ represents threshold current $I_{DS,t}$ with a unit of A. In this region, $I_{DS}$ exhibits an exponential dependence on $V_{GS}$.

Table 1. Comparison of ULV OTA designs.

Ref.	Tech. Node	Mode	Topology	Advantage	Limitations	Improvement
2021 [32]	180 nm	GD	Pseudo-Differential Input	High open-loop gain. Wide input CMR covers 94% of supply voltage. High CMRR.	Low SR restricts high-speed operation. High design complexity.	Using pseudo-differential Pair with cross-connected node to enhance the effective transconductance.
2014 [33]	130 nm	BD	Positive Feedback Source Degeneration	Rail-to-rail output swings. Ultra-low voltage and power consumption. High phase margin.	Relatively low gain compared to other OTAs. Distortion at maximum swing.	Using positive feedback source degeneration to enhance the bulk-driven transconductance.
2020 [34]	180 nm	BD	Double Recycling Current Mirror	High open-loop gain. Ultra-low supply voltage. Compact chip area.	High UGF limits in high-frequency app. Sensitive to temp. as PM degrades to 40° at −10 °C. Design complexity.	Using double recycling structure, PPF, and FVF topology to enhance the transconductance for bulk-driven MOSFET.
2016 [35]	65 nm	BD	Folded Cascode with Current Recycling	Wide UGBW with superior GBW, suitable for high-speed applications.	Higher power consumption than other subthreshold designs. Low SR restricts high-speed operation.	Recycling folded-cascode architecture enhances effective transconductance in subthreshold operation.
2020 [26]	180 nm	BD	Multipath Miller Zero Compensation	High CMRR. Ultra-low voltage and power consumption. Compact chip area.	Highly sensitive to process variations. Low GBW (2.96 kHz) limits high-speed operation.	Using bulk-driven non-tailed dif. stage to increase the ICMR. Using MMZCC to eliminate the right half plane zero to improve the phase margin.
2016 [36]	130 nm	BD	Positive Feedback Source Degeneration and Current Recycling	Ultra-low voltage and power consumption.	Lower DC gain than other subthreshold OTA designs. Design complexity.	Using positive-feedback source degeneration and current recycling to improve effective transconductance.
2021 [37]	130 nm	BD	Dual-path Body-driven Input	Ultra-low voltage and power consumption. Compact chip area.	Lower DC gain than other subthreshold OTA designs. Lower phase margin.	Using dual-path transconductance stage to improve the CMRR and the diff. gain. Using a bulk-driven current mirror to simplify the design, eliminating the need for additional compensation.
2021 [38]	180 nm	BD	Flipped Voltage Follower Differential Pair	Higher DC gain. Improved CMRR.	High design complexity. Improved but still insufficient SR for high-speed operation. Large phase margin limits transient response speed.	Using FVF and PPF to enhance the effective transconductance of the bulk-driven stage. Increased DC gain using a self-cascode current mirror. Improved SR through class-AB operation.
2016 [39]	180 nm	GD	Cross-coupled Output Stage	Higher DC gain. Ultra-low power consumption. Symmetrical SR.	Insufficient GBW for high-speed operation. Significant current increase above 0.5 V. Higher design complexity and bias sensitivity in GD mode.	Using cross-coupled configuration to increase the output transconductance. Improved input impedance using a gate-driven input.
2021 [40]	130 nm	BD	Local Common Mode Feedback	Ultra-low voltage and power consumption.	Lower DC gain than other subthreshold OTA designs. Relatively high IRN. Higher SR asymmetry.	Using body-to-gate interface to enhance the SR. Improved CMRR using local CMFB with pseudo-resistors.
2022 [41]	180 nm	MI-BD	Multiple-input MOS Transistor Differential Pair	High gain for ultra-low-voltage amplifier. Good noise performance.	High input-referred offset of 6.14 mV. High design complexity and area. Partial positive feedback enhances gain but reduces stability.	Using an MI-BD stage to reduce power consumption. Enhanced gain using a self-cascode output stage with partial positive feedback.
2023 [42]	180 nm	BD	Bulk-driven and Self-cascode Transistor	Ultra-low power consumption Low THD of −53.56 dB means good linearity. High CMRR and PSRR.	Relatively lower gain than other designs. Limited GBW restricts operation to low-frequency apps.	Using partial positive feedback to enhance gain.
2020 [43]	180 nm	BD	Reversed Nested Miller Compensation	High open-loop gain. Ultra-low voltage and power consumption.	Limited GBW restricts operation to low-frequency apps. Higher SR asymmetry.	Using three amplification stages to achieve higher gain and stable operation by RNMC.
2020 [44]	65 nm	BD	Asymmetric Self-cascode Transistor and Indirect Feedback Compensation	High open-loop gain. Ultra-low voltage and power consumption.	High phase margin leads to slow response; low slew rate limits fast signal tracking.	Using a three-stage asymmetric self-cascode design to achieve higher gain. Improved phase margin using indirect feedback compensation.
2015 [13]	65 nm	BD	Pseudo-differential Pair and Self-biasing Technique	Ultra-low supply voltage. High GBW, enabling higher-speed operation than comparable designs.	Lower gain than comparable designs. High power consumption.	Using self-biasing to improve robustness to process variations. Reduced compensation capacitance using DFC.
2024 [27]	180 nm	BD	Current-reuse Pseudo-differential Pairs	Ultra-low power consumption. Stable transconductance with only 1.35% variation.	Increased complexity due to negative impedance and current-correction branches. Performance degra-dation for $C_L$>15 pF.	Using a negative-impedance branch to boost transconductance and improve NMOS–PMOS matching.
2022 [45]	130 nm	BD	Linearization Using a Linear Resistor	Ultra-low power consumption. High linearity with THD less than 0.5%. Small chip area.	Significantly lower gain. Linearity is sensitive to resistor sizing and process variations.	Using a linearization resistor to improve input-stage linearity.
2023 [46]	180 nm	BD	Replica Loop Biasing	Ultra-low voltage and power consumption.	Limited GBW limits the applications to low-speed signals. Lower SR results in slower tran. response. Stability issue due to low phase margin.	Using replica-loop biasing to improve CMRR and PVT robustness. Reduced current mirror gain error using an auxiliary amplifier.
2022 [47]	180 nm	MI-BD	Source Degeneration with Multiple-input Transistor	Ultra-low power consumption. High CMRR and improved linearity. Stable performance across PVT.	Low gain compared to other designs. Limited GBW restricts operation to low-frequency applications.	Using MI-BD with capacitive summing to reduce the number of OTAs in filters. Extended linear range using source degeneration and MI capacitive division.

GD—gate driven; BD—bulk driven; MI-BD—multi-input bulk driven; CMR—common mode range; PSRR—power supply rejection ratio; UGBW—unity gain bandwidth; SR—slew rate; PPF—partial positive feedback; FVF—flipped voltage follower; IRN—input-referred noise; CMFB—common mode feedback; RNMC—reversed nested Miller compensation; DFC—damping factor control; PVT—process, voltage, temperature.

Table 1. Comparison of ULV OTA designs.

Ref.	Tech. Node	Mode	Topology	Advantage	Limitations	Improvement
2021 [32]	180 nm	GD	Pseudo-Differential Input	High open-loop gain. Wide input CMR covers 94% of supply voltage. High CMRR.	Low SR restricts high-speed operation. High design complexity.	Using pseudo-differential Pair with cross-connected node to enhance the effective transconductance.
2014 [33]	130 nm	BD	Positive Feedback Source Degeneration	Rail-to-rail output swings. Ultra-low voltage and power consumption. High phase margin.	Relatively low gain compared to other OTAs. Distortion at maximum swing.	Using positive feedback source degeneration to enhance the bulk-driven transconductance.
2020 [34]	180 nm	BD	Double Recycling Current Mirror	High open-loop gain. Ultra-low supply voltage. Compact chip area.	High UGF limits in high-frequency app. Sensitive to temp. as PM degrades to 40° at −10 °C. Design complexity.	Using double recycling structure, PPF, and FVF topology to enhance the transconductance for bulk-driven MOSFET.
2016 [35]	65 nm	BD	Folded Cascode with Current Recycling	Wide UGBW with superior GBW, suitable for high-speed applications.	Higher power consumption than other subthreshold designs. Low SR restricts high-speed operation.	Recycling folded-cascode architecture enhances effective transconductance in subthreshold operation.
2020 [26]	180 nm	BD	Multipath Miller Zero Compensation	High CMRR. Ultra-low voltage and power consumption. Compact chip area.	Highly sensitive to process variations. Low GBW (2.96 kHz) limits high-speed operation.	Using bulk-driven non-tailed dif. stage to increase the ICMR. Using MMZCC to eliminate the right half plane zero to improve the phase margin.
2016 [36]	130 nm	BD	Positive Feedback Source Degeneration and Current Recycling	Ultra-low voltage and power consumption.	Lower DC gain than other subthreshold OTA designs. Design complexity.	Using positive-feedback source degeneration and current recycling to improve effective transconductance.
2021 [37]	130 nm	BD	Dual-path Body-driven Input	Ultra-low voltage and power consumption. Compact chip area.	Lower DC gain than other subthreshold OTA designs. Lower phase margin.	Using dual-path transconductance stage to improve the CMRR and the diff. gain. Using a bulk-driven current mirror to simplify the design, eliminating the need for additional compensation.
2021 [38]	180 nm	BD	Flipped Voltage Follower Differential Pair	Higher DC gain. Improved CMRR.	High design complexity. Improved but still insufficient SR for high-speed operation. Large phase margin limits transient response speed.	Using FVF and PPF to enhance the effective transconductance of the bulk-driven stage. Increased DC gain using a self-cascode current mirror. Improved SR through class-AB operation.
2016 [39]	180 nm	GD	Cross-coupled Output Stage	Higher DC gain. Ultra-low power consumption. Symmetrical SR.	Insufficient GBW for high-speed operation. Significant current increase above 0.5 V. Higher design complexity and bias sensitivity in GD mode.	Using cross-coupled configuration to increase the output transconductance. Improved input impedance using a gate-driven input.
2021 [40]	130 nm	BD	Local Common Mode Feedback	Ultra-low voltage and power consumption.	Lower DC gain than other subthreshold OTA designs. Relatively high IRN. Higher SR asymmetry.	Using body-to-gate interface to enhance the SR. Improved CMRR using local CMFB with pseudo-resistors.
2022 [41]	180 nm	MI-BD	Multiple-input MOS Transistor Differential Pair	High gain for ultra-low-voltage amplifier. Good noise performance.	High input-referred offset of 6.14 mV. High design complexity and area. Partial positive feedback enhances gain but reduces stability.	Using an MI-BD stage to reduce power consumption. Enhanced gain using a self-cascode output stage with partial positive feedback.
2023 [42]	180 nm	BD	Bulk-driven and Self-cascode Transistor	Ultra-low power consumption Low THD of −53.56 dB means good linearity. High CMRR and PSRR.	Relatively lower gain than other designs. Limited GBW restricts operation to low-frequency apps.	Using partial positive feedback to enhance gain.
2020 [43]	180 nm	BD	Reversed Nested Miller Compensation	High open-loop gain. Ultra-low voltage and power consumption.	Limited GBW restricts operation to low-frequency apps. Higher SR asymmetry.	Using three amplification stages to achieve higher gain and stable operation by RNMC.
2020 [44]	65 nm	BD	Asymmetric Self-cascode Transistor and Indirect Feedback Compensation	High open-loop gain. Ultra-low voltage and power consumption.	High phase margin leads to slow response; low slew rate limits fast signal tracking.	Using a three-stage asymmetric self-cascode design to achieve higher gain. Improved phase margin using indirect feedback compensation.
2015 [13]	65 nm	BD	Pseudo-differential Pair and Self-biasing Technique	Ultra-low supply voltage. High GBW, enabling higher-speed operation than comparable designs.	Lower gain than comparable designs. High power consumption.	Using self-biasing to improve robustness to process variations. Reduced compensation capacitance using DFC.
2024 [27]	180 nm	BD	Current-reuse Pseudo-differential Pairs	Ultra-low power consumption. Stable transconductance with only 1.35% variation.	Increased complexity due to negative impedance and current-correction branches. Performance degra-dation for $C_L$>15 pF.	Using a negative-impedance branch to boost transconductance and improve NMOS–PMOS matching.
2022 [45]	130 nm	BD	Linearization Using a Linear Resistor	Ultra-low power consumption. High linearity with THD less than 0.5%. Small chip area.	Significantly lower gain. Linearity is sensitive to resistor sizing and process variations.	Using a linearization resistor to improve input-stage linearity.
2023 [46]	180 nm	BD	Replica Loop Biasing	Ultra-low voltage and power consumption.	Limited GBW limits the applications to low-speed signals. Lower SR results in slower tran. response. Stability issue due to low phase margin.	Using replica-loop biasing to improve CMRR and PVT robustness. Reduced current mirror gain error using an auxiliary amplifier.
2022 [47]	180 nm	MI-BD	Source Degeneration with Multiple-input Transistor	Ultra-low power consumption. High CMRR and improved linearity. Stable performance across PVT.	Low gain compared to other designs. Limited GBW restricts operation to low-frequency applications.	Using MI-BD with capacitive summing to reduce the number of OTAs in filters. Extended linear range using source degeneration and MI capacitive division.

GD—gate driven; BD—bulk driven; MI-BD—multi-input bulk driven; CMR—common mode range; PSRR—power supply rejection ratio; UGBW—unity gain bandwidth; SR—slew rate; PPF—partial positive feedback; FVF—flipped voltage follower; IRN—input-referred noise; CMFB—common mode feedback; RNMC—reversed nested Miller compensation; DFC—damping factor control; PVT—process, voltage, temperature.

Another significant parameter for subthreshold is the slope of $log{I}_{DS}$ versus $V_{GS}$, known as the subthreshold swing S. Note that according to Formula (1), $I_{DS}$ is not zero even when $V_{GS}=0$.

In other words, there is current flowing inside the MOSFET when no gate voltage is applied. The current when $V_{GS}=0$ is referred to as the leakage current. This leakage current causes the MOSFET to consume power even when no gate voltage is applied, which is not ideal for reducing overall circuit power consumption. The subthreshold swing directly determines the magnitude of the leakage current and can be calculated using the following equation:

$${\displaystyle \frac{d}{d{V}_{GS}}}\log \left(I_{DS}\right)={\displaystyle \frac{1}{2.3\left(\frac{kT}{q}\right)\eta }}={\displaystyle \frac{1}{\left(0.06 \mathrm{V}\right)\eta }}={\displaystyle \frac{1}{S}} ; S=2.3{\displaystyle \frac{kT}{q}}\eta =(60 \mathrm{m}\mathrm{V})\eta$$

(2)

indicating that $I_{DS}$ will change ten times for every $(60 \mathrm{m}\mathrm{V})\eta$ change in the $V_{GS}$. The leakage current is then calculated as

$$I_{off}=0.1{\displaystyle \frac{W}{L}}{e}^{{\displaystyle \frac{-{2.3V}_{th}}{S}}}$$

(3)

A smaller subthreshold swing S will result in a lower leakage current, and the subthreshold swing can be calculated with $\eta$:

$$\eta =1+{\displaystyle \frac{C_{dep}}{C_{ox}}}=1+\sqrt{{\displaystyle \frac{q{N}_a{\epsilon }_s}{2\left({\varphi }_{bi}+V_{GS}\right)}}}\left({\displaystyle \frac{t_{ox}}{{\epsilon }_{ox}}}\right)$$

(4)

where ${\varphi }_{bi}$ denotes the built-in potential determined by the substrate doping, $N_a$ represents substrate doping concentration, ${\epsilon }_s$ is the permittivity of the semiconductor, and $t_{ox}$ specifies the oxide thickness. Reducing $\eta$ helps lower the subthreshold swing, thereby decreasing the leakage current.

Traditional MOSFETs utilize a gate-driven topology, where the gate terminal serves as the input. As mentioned in the section on subthreshold operation, when the device operates in the weak-inversion region, the applied gate voltage lies below the threshold voltage, and a 60 mV change in gate voltage results in a decade variation in the drain current.

To address this issue, multiple differential pairs can be used in parallel, or a floating gate approach can be employed. Both methods require designing highly complex circuits to control the biasing of the transistors [48]. Another approach is to adjust the threshold voltage through body biasing, which can be used to reduce the MOSFET threshold voltage and thereby lower power consumption and enable operation at lower supply voltages [49]. However, this approach is not suitable for subthreshold operation. This makes using a gate-driven topology in the subthreshold region particularly challenging. To address this issue, a bulk-driven topology is adopted for MOSFETs operating in weak inversion. In a bulk-driven configuration, the input signal is applied to the bulk terminal while the gate is held at a constant bias voltage. This approach resolves the problem of gate voltage significantly impacting the current. The drain to source current $I_{DS}$ using bulk-driven topology is given as [33]

$$I_{DS}\propto \mathrm{e}\mathrm{x}\mathrm{p}(q{\displaystyle \frac{V_{GS}}{nkT}})\mathrm{e}\mathrm{x}\mathrm{p}(q(n-1){\displaystyle \frac{V_{BS}}{nkT}})$$

(5)

It is noted that the influence of $V_{BS}$ on $I_{DS}$ is (n − 1) times weaker than that of $V_{GS}$ on $I_{DS}$. Additionally, the bulk transconductance $g_{mb}$ is typically only 20–30% of the gate transconductance $g_m$ [48]. As a result, the achievable maximum transconductance with bulk-driven topology is relatively low. Traditionally, OTAs using a bulk-driven topology experience some performance trade-offs, which is less than ideal. To address this limitation, additional topologies must be employed alongside the bulk-driven approach to enhance transconductance.

2.2. Comparative Analysis of ULV OTA Topologies

In this section, nineteen ultra-low-voltage (ULV) OTA designs employing different circuit topologies are compared. The advantages and disadvantages of each topology are briefly analyzed, and the performance improvements that each topology can bring to OTA performance are summarized.

Based on the comparison results, most ULV OTA designs employ bulk-driven (BD) input stages, since the input swing of bulk-driven transistors is not limited by the threshold voltage. Therefore, bulk-driven transistors are also adopted as the input devices in this design. In addition, the comparison in Table 1 shows that designs utilizing multiple-input techniques generally exhibit improved robustness against temperature and process-corner variations. However, this robustness is achieved at the expense of significantly increased circuit complexity and area. Since the primary goal of this design is to realize a compact OTA, multiple-input techniques are deliberately not adopted. Furthermore, it can be observed that designs based on recycling current mirrors or current-reuse architectures typically achieve lower power consumption, which aligns well with the low-power design objective of this work. Therefore, a current-reuse technique is employed to effectively reduce the overall power consumption.

3. Proposed Design

This section presents the detailed design of the proposed OTA design presented in this paper, including an explanation of the adopted topology and the associated mathematical analysis. The section sequentially discusses the OTA input stage and the compensation techniques employed.

3.1. Input Stage of OTA

Figure 3 illustrates the amplifier core of the proposed two-stage amplifier. The first stage adopts a bulk-driven input structure optimized for ultra-low-voltage operation in [22] and incorporates a current-reuse scheme to enhance transconductance efficiency. The output stage employs a common-source configuration realized by PM6 and NM5. To suppress the right-half-plane zero associated with Miller compensation, a feedforward path implemented by PM5 and NM4 is introduced in conjunction with the compensation capacitor $C_C$. The circuit operates under an ultralow supply voltage while achieving improved CMRR, PSRR, and a nearly rail-to-rail input common-mode range (ICMR). Furthermore, the amplifier operates in class-AB mode, providing enhanced slew rate (SR) performance.

In the input stage, the bulk-driven differential pair is formed by PM1 and PM4, whose gate terminals are biased by the diode-connected transistors PM2 and PM3, respectively. The bulk terminals of PM1 and PM4 are cross-coupled to the gate-drain nodes of PM3 and PM2, establishing a cross-coupled bulk-driven excitation that enhances effective transconductance.

In the proposed design, transistors NM1a and NM1b are introduced beneath the input core to implement a current-reuse structure. These NMOS devices are driven by the same internal gate–drain nodes of PM2 and PM3, such that the small-signal voltage variations at these nodes generate additional signal-dependent drain currents through NM1a and NM1b. As a result, the same bias current is reused by both the bulk-driven PMOS input pair and the NMOS auxiliary transconductor branch, improving transconductance efficiency without altering the bulk-driven input mechanism. Consequently, the effective input-stage transconductance and overall voltage gain are significantly enhanced.

Thanks to the fully symmetrical structure of the design, the following small-signal analysis was carried out to further examine the advantages of this topology. Based on the BD differential input pair presented in [24], the resulting input-stage transconductance can be expressed for the current reuse input as

$$g_{meff}=g_{mb,PM1}(1+{\displaystyle \frac{g_{m,PM1}+g_{m,CR}}{g_{mb,PM1}}}·{\displaystyle \frac{g_{mb,PM2}}{g_{m,PM2}+g_{ds,PM2}+g_{ds,NM2}+g_{load,CR}}})$$

(6)

$$g_{meff}=g_{mb,PM1}(1+{\displaystyle \frac{g_{m,PM1}+g_{m,CR}}{g_{mb,PM1}}}·{\displaystyle \frac{g_{mb,PM2}}{g_{m,PM2}}})$$

(7)

$$g_{meff}={\left(1+\eta \right)g}_{mb,PM1}$$

(8)

$$\eta ={\displaystyle \frac{g_{m,PM1}+g_{m,CR}}{g_{mb,PM1}}}·{\displaystyle \frac{g_{mb,PM2}}{g_{m,PM2}}}$$

(9)

where $g_{m,CR}$ is the transconductance of the current-reuse node. In Equation (7), it is assumed that $g_{load,CR} \ll g_{m,PM1}$. From the above expression, it can be observed that the effective transconductance is approximately $\left(1+\eta \right)$ times that of a conventional bulk-driven transistor. The overall voltage gain of the proposed design can be expressed as

$$A_v={\displaystyle \frac{g_{meff}}{g_{out}}}={\displaystyle \frac{\left(1+\eta \right)\frac{n}{n+1}{g}_{meff,con}}{\frac{n}{n+1}{g}_{out,con}}}=\left(1+\eta \right)A_{v,con}$$

(10)

where n denotes the ratio of the transistor aspect ratio. From this expression, it is evident that the use of a gain-boosted input stage and current-reuse technique enables the amplifier to achieve higher gain than a conventional differential input stage.

3.2. Multipath Miller Zero Cancellation Compensation (MMZCC)

The introduction of the current-reuse auxiliary branch successfully increases the effective transconductance ($g_{m,eff}$) of the input stage (as derived in Equation (6)), thereby enhancing both DC gain and GBW. However, as noted in similar high-efficiency designs, this performance boost comes at a cost: the additional path introduces a non-dominant pole that shifts toward lower frequencies. This shift aggravates the phase-margin degradation associated with conventional Miller compensation, especially when driving large capacitive loads. To ensure stable operation under ULV conditions without resorting to prohibitively large compensation capacitors, the proposed circuit utilizes the MMZCC technique [23]. By generating a left-half-plane zero, this method enables precise pole-zero cancellation. This preserves the phase margin and slew-rate performance while maintaining the power efficiency gains achieved by the current-reuse stage. The transfer function of the complete amplifier, illustrating this compensation, can be derived as follows:

$${\displaystyle \frac{V_{out}}{V_{in}}}={\displaystyle \frac{g_{meff}{g}_{m,NM5}}{g_{out,CR}\left(g_{ds,PM6+}{g}_{ds,NM5}\right)}}·{\displaystyle \frac{1+s\frac{(g_{mf}-g_{meff})C_C}{g_{meff}{g}_{m,NM5}}}{(1+s{C}_L/g_{m,NM5})(1+s\frac{g_{m,NM5}{C}_C}{g_{out,CR}\left(g_{ds,PM6+}{g}_{ds,NM5}\right)})}}$$

(11)

where $C_C$ is the Miller compensation capacitance, $g_{mf}$ is the transconductance of the feedforward circuit formed by PM5 and NM4, $C_L$ is the load capacitance. From the transfer function, it can be observed that the system exhibits two left-half-plane (LHP) poles and one zero, which are given by

$$p_1=-{\displaystyle \frac{g_{out,CR}\left(g_{ds,PM6+}{g}_{ds,NM5}\right)}{g_{m,NM5}{C}_C}}$$

(12)

$$p_2=-{\displaystyle \frac{g_{m,NM5}}{C_L}}$$

(13)

$$z_1=-{\displaystyle \frac{g_{meff}{g}_{m,NM5}}{(g_{mf}-g_{meff})C_C}}$$

(14)

Noting that zero shifts to the LHP when $g_{mf}>g_{meff}$. The $p_2$ could also be canceled with $z_1$ [26] if this condition can be satisfied:

$$g_{mf}=(1+{\displaystyle \frac{C_L}{C_C}})g_{meff}$$

(15)

The effective transconductance of the feedforward circuit could be calculated as

$$g_{mf}={\displaystyle \frac{g_{meff}}{2}}\times {\displaystyle \frac{g_{m,NM9}}{g_{m,NM7}}}\times {\displaystyle \frac{g_{m,PM6}}{g_{m,PM5}}}$$

(16)

assuming that all transistors operate in the subthreshold region, where the transconductance is proportional to the biasing current. From Equations (15) and (16), we could obtain the pole-zero cancellation as

$${\displaystyle \frac{I_{D,PM6}}{I_{D,NM7}}}={\displaystyle \frac{1}{2}}(1+{\displaystyle \frac{C_L}{C_C}})$$

(17)

When this condition is met, the $z_1$ will cancel with $p_2$ and the transfer function (11) has only one pole. To fulfill this condition, a large $I_{D,PM6}$ is needed, which is difficult in the ultra-low power design where current is small and limited by the ultra-low supply voltage. We could also use larger $C_C$ to realize this condition. However, a larger $C_C$ will result in lower gain bandwidth product (GBW) and slew rate (SR). Consequently, the discussed compensation strategy is suitable for applications with relatively small load capacitance.

To enhance the output driving capability, a push–pull feedforward structure is incorporated in the proposed design. In this configuration, NM4 mirrors the current of NM3 and the PM6 mirrors the current of PM5, which is the same as $I_{D,NM3}$. PM6 will be given a large size; thus, the output current will be increased when the NM4 current is mirrored to the output. The GBW is

$$GBW\cong {\displaystyle \frac{g_{meff}}{C_C}}$$

(18)

For an ideal symmetrical input stage, the CMRR could be calculated based on the equation presented in [26] as

$$CMRR\cong {\displaystyle \frac{g_{meff}}{(g_{ds,PM2}+g_{ds,NM2}+g_{ds,CR})}}·{\displaystyle \frac{g_{m,NM3}}{(g_{ds,PM1}+g_{ds,CR}+g_{ds,NM3})}}·{\displaystyle \frac{g_{m,PM5}}{(g_{ds,PM5}+g_{ds,NM4})}}$$

(19)

Because the small-signal gain from the VDD to the output is close to unity, the resulting power-supply rejection ratio is dominated by the open-loop gain of the OTA. The corresponding positive and negative slew rate of the proposed design can be expressed as

$$SR-\cong {\displaystyle \frac{I_{D,NM5}}{C_C+C_L}}$$

(20)

$$SR+\cong \mathrm{m}\mathrm{i}\mathrm{n}({\displaystyle \frac{\left(I_{bias}+I_{Reuse}\right)·W_{PM6}}{2W_{NM3}\left(C_C+C_L\right)}}, {\displaystyle \frac{g_{meff}·v_{id}}{C_C}})$$

(21)

Here, $I_{bias}$ denotes the bias current of the input stage, $I_{D,NM5}$ represents the maximum current NM5 could sink, $W_{PM6}$ and $W_{NM3}$ are the widths of PM6 and NM3, respectively, and $I_{Reuse}$ corresponds to the reused current in NM1a and NM1b. SR- is determined by how fast the output stage can discharge the load, which depends on the maximum current that transistor NM5 can sink. In contrast, the positive slew rate (SR+) depends on the charging capability of the output stage, which is set by the maximum sourcing current. From the expression, we could observe that the SR- is constrained by $I_{D,NM5}$ and $C_L$. Owing to the absence of a tail current limitation, the output current of the first stage can exceed the biasing current of the input stage, resulting in an enhanced SR [24].

4. Simulation Results

All circuit simulations are conducted using Cadence Virtuoso with a 45 nm CMOS PDK. This section presents and analyzes the OTA performance based on simulation results, beginning with pre-layout simulations and followed by post-layout verification. Unless otherwise stated, simulations are performed at a nominal temperature of 27 °C.

The transistor sizes were determined through simulation-based optimization, with the highest achievable gain as the primary design target. The final selected transistor dimensions are listed in

Table 2. Transistor aspect ratios.

Devices	$\mathbf{W}/\mathbf{L} [\mathsf{\mu }\mathbf{m}/\mathsf{\mu }\mathbf{m}$]
PM1-4	2 × 15/1
PM5	2 × 5/2
PM6	10 × 5/2
NM1a/b	2 × 10/0.5
NM2	8 × 10/1
NM3	2 × 4/2
NM4	2 × 15/2
NM5	4 × 37.5/2
NM6	2 × 2.5/1
${\mathit{C}}_{\mathit{c}}$	2.5 pF

. Based on the calculations using the MMZCC method, the required Miller compensation capacitance $C_C$ was determined to be 2 pF. Initially, using this value of $C_c$ resulted in a phase margin of 46.7°, indicating insufficient stability. Since the phase margin typically degrades after layout, a larger $C_c$ is required. After adjusting, a value of 2.5 pF is ultimately selected for $C_c$, yielding a phase margin of 55.11°. This choice ensures adequate stability while preventing excessive degradation of the slew rate.

Simulation results indicate that the proposed OTA achieves an open-loop gain of 44.38 dB with a phase margin of 55.11°, effectively balancing circuit stability and speed. As discussed previously, increasing the channel length helps to improve the gain due to the reduction in output conductance. However, excessively large channel lengths are generally not practical from a fabrication standpoint and are therefore avoided. Although larger channel lengths may degrade the circuit’s speed, this trade-off is acceptable in ultra-low-power OTA designs, which are typically intended for low-speed applications such as bio signal processing. In such scenarios, prioritizing power efficiency and gain over speed is considered a reasonable design choice.

Figure 4 presents the step response of the proposed OTA when driving a 30 pF load capacitance. The output of the OTA swings from 10 mV to 290 mV, achieving an output swing utilization of 94%, which demonstrates a near rail-to-rail output capability. The input common-mode voltage is swept from 0 mV to 300 mV.

At 0 mV, a gain of 44.83 dB is measured. As the input common-mode voltage increases, the gain gradually decreases, reaching 43.47 dB at 300 mV, corresponding to a reduction of approximately 3%. Therefore, the OTA maintains stable gain across the entire 0.3 V common-mode range, effectively achieving a full input common-mode range (ICMR). The 1% settling time is measured to be 164.901 μs.

Although the settling time is relatively slow compared to high-speed amplifiers, the proposed OTA is designed for ultra-low-power applications where speed is not the primary requirement. Typical use cases, such as IoT devices and biomedical applications, generally operate at low frequencies and do not demand high-speed performance. Therefore, the slower response time is considered an acceptable trade-off in favor of power efficiency and wide output swing.

The proposed OTA exhibits a slew rate of 4.64 V/ms for positive transitions and 7.83 V/ms for negative transitions. These results demonstrate a largely symmetric slew-rate behavior, confirming the amplifier’s ability to respond uniformly to variations in the signal input.

Figure 5a presents the pre-layout simulation results, while Figure 5b shows the post-layout simulation results. The phase margin decreases from 55.11° to 53.93° after layout. Such a reduction in phase margin is a common phenomenon in post-layout simulations, as the introduction of parasitic capacitances associated with the transistors shifts the locations of system poles and zeros, thereby degrading the alignment of the compensation network and reducing its effectiveness. This effect is particularly pronounced when using MMZCC, where pole–zero cancellation is highly sensitive to alignment accuracy, leading to a noticeable degradation in phase margin after layout.

Figure 6a compares the pre-layout and post-layout CMRR. The CMRR is 76.01 dB in the pre-layout simulation and increases to 87.48 dB in the post-layout simulation, corresponding to an improvement of 11.47 dB. The post-layout result is obtained from parasitic-extracted simulations without device mismatch, and the CMRR is reported at 1 Hz. Further explanations will be given in the following section. Figure 6b shows the comparison of PSRR measured at 1 Hz, which decreases from 42.64 dB in the pre-layout simulation to 41.13 dB in the post-layout simulation, representing a reduction of 1.5 dB. A slight degradation in PSRR after layout is a commonly observed phenomenon. Figure 6c compares the pre-layout and post-layout input noise. At 1000 Hz, the input noise is 0.93 μV/√Hz in the pre-layout simulation and increases to 1.02 μV/√Hz in the post-layout simulation. In addition, the total harmonic distortion (THD) of the circuit is 0.8% at a 200 mV peak-to-peak input signal and reaches 1% at approximately 250 mV peak-to-peak, corresponding to about 86% of the output swing.

The CMRR shows a noticeable improvement after layout, which is not commonly observed. As indicated by (19), the CMRR depends on both the transconductance $g_m$ and the output conductance $g_{ds}$. An increase in CMRR requires either an increase in $g_{m,\mathrm{e}\mathrm{f}\mathrm{f}}$ or a decrease in $g_{ds}$. In subthreshold operation, the transconductance is primarily determined by the drain current $I_D$, which is usually set by the bias conditions; thus, $g_m$ is not expected to increase significantly after layout. In contrast, a reduction in $g_{ds}$, or equivalently, an increase in the output resistance $r_o$ as $r_o={\displaystyle \frac{1}{g_{ds}}}$, is more likely to occur after layout. Effects such as diffusion extension and well proximity effects can increase $r_o$, leading to a decrease in $g_{ds}$ [50] and, consequently, an increase in CMRR.

In the proposed design, the observed increase in CMRR suggests that the output resistance $r_o$ increases after layout, implying a reduction in $g_{ds}$. Since $g_{ds}$ appears in the denominator of Equation (19), a decrease in $g_{ds}$ leads to an improvement in CMRR, which explains the simulation results observed after layout.

Figure 7 compares the output impedance of the proposed OTA obtained from pre-layout and post-layout simulations. It can be observed that the output impedance increases significantly after layout, which is consistent with the previous analysis. The increase in output impedance directly contributes to the observed improvements in CMRR.

As this is a bulk-driven ultra-low-voltage, low-power design, careful device matching, shortest possible routing, and proper placement of substrate tap cells are essential to minimize parasitic RC effects and substrate resistance. Since the circuit operates with nanoampere-level currents and millivolt-level voltage variations, even small parasitic mismatches can significantly impact performance. Figure 8 presents the layout of the proposed OTA. The measured chip area is approximately 0.0044 mm².

The DC gain decreases from 44.38 dB to 44.24 dB after layout, corresponding to a decrease of 0.14 dB. A decrease in gain after layout is commonly observed, as post-layout parasitic effects typically degrade circuit performance.

Table 3. Results of pre-layout simulation and post-layout simulation.

Parameter	Pre-Layout	Post-Layout
${\mathit{A}}_{\mathit{v}\mathit{o}}$, [dB]	44.38	44.24
Phase margin, [°]	55.11	53.93
GBW, [kHz]	13.01	9.87
SR+, [V/ms]	5.62	4.64
SR−, [V/ms]	9.59	7.83
CMRR, [dB]	76.01	87.48
PSRR, [dB]	42.64	41.13

compares the OTA performance parameters obtained from pre-layout and post-layout simulations. It can be observed that most performance metrics degrade after layout, primarily due to the parasitic effects introduced during layout, which adversely affect circuit performance. According to (18), the gain–bandwidth product (GBW) is related to the transconductance $g_m$. Since layout parasitics typically reduce $g_m$, the GBW correspondingly decreases from 13.01 kHz to 9.87 kHz by approximately 3.14 kHz after layout.

The SR+ is 4.64 V/ms, while the SR- is 7.83 V/ms, showing an asymmetry. This asymmetry mainly arises because the size of NM5 is larger than that of PM6, resulting in a higher sinking current than sourcing current. The larger NM5 size is intentionally chosen to increase the voltage gain, leading to a deliberate trade-off between gain and slew-rate symmetry.

According to Equation (1), the drain current in subthreshold operation exhibits strong temperature dependence due to its exponential behavior. This dependence is considerably weaker for transistors operating in the conventional saturation region. Since all transistors in the proposed OTA are biased in subthreshold, the circuit is therefore sensitive to temperature and process corner variations.

Table 4. Simulated main performance parameter over process corner variation.

Parameter (27 °C)	FF	FS	TT	SF	SS
${\mathit{A}}_{\mathit{v}\mathit{o}},$ [dB]	39.17	42.23	44.24	45.01	45.26
Phase margin, [°]	60	55.54	53.93	53.07	52.24
GBW, [kHz]	18.71	9.72	9.87	9.69	3.71
SR+, [V/ms]	8.41	4.31	4.64	4.62	1.84
SR−, [V/ms]	14.81	7.93	7.83	7.34	3.01
CMRR, [dB]	74.75	84.7	87.48	88.62	86.35
PSRR, [dB]	38.33	37.67	41.13	43.4	42.42

presents the performance variations in the proposed OTA across different process corners. Note that process corners have different impacts on various performance metrics: the gain variation is 13.46%, the phase margin variation is 12.93%, the GBW variation is 83.06%, the slew-rate (SR) variation is 79.67%, the CMRR variation is 15.65%, and the PSRR variation is 13.2%. Among these metrics, phase margin is the least affected by process corners, while GBW exhibits the largest variation. Process corners alter the threshold voltage $V_{th}$, and since the transconductance $g_m$ is directly related to the drain current $I_D$, the exponential dependence of $I_D$ on $V_{th}$ in the subthreshold region leads to significant variations in $g_m$. This explains why GBW is particularly sensitive to process corner variations in the simulation results.

Table 5. Simulated main performance parameter over temperature variation.

Parameter (TT Corner)	0 °C	27 °C	70 °C
${\mathit{A}}_{\mathit{v}\mathit{o}},$ [dB]	46.1	44.24	36.54
Phase margin, [°]	51.45	53.93	62.54
GBW, [kHz]	4.93	9.87	17.15
SR+, [V/ms]	2.51	4.64	7.36
SR−, [V/ms]	4.27	7.83	12.25
CMRR, [dB]	78.29	87.48	80
PSRR, [dB]	42.42	41.13	36.29

presents the performance variations in the proposed OTA under different temperatures. It can be observed that temperature also has a significant impact on circuit performance. The gain variation is 20.73%, the phase margin variation is 17.73%, the GBW variation is 71.25%, the slew-rate (SR) variation is 65.14%, the CMRR variation is 10.5%, and the PSRR variation is 14.45%. Similar to the process-corner analysis, GBW is the most severely affected performance metric. As indicated by (1), the drain current $I_D$ exhibits an exponential dependence on temperature in the subthreshold region; therefore, temperature variations strongly affect $I_D$, leading to significant changes in $g_m$ and, consequently, GBW. In addition, it can be observed that the SR increases with temperature, indicating that the circuit operates faster at higher temperatures. Moreover, the impacts of temperature and process-corner variations on circuit performance exhibit similar trends, suggesting that $I_D$ is the dominant factor affecting performance in subthreshold operation. Since $I_D$ follows an exponential relationship in the subthreshold region.

While the proposed OTA achieves impressive power efficiency through subthreshold operation, this design choice inherently introduces sensitivity to PVT variations. In weak inversion, drain current exhibits an exponential dependence on threshold voltage and thermal voltage, making transconductance and, consequently, GBW particularly susceptible to environmental and manufacturing fluctuations. Simulation results confirm this behavior: across PVT corners, GBW and slew rate show noticeable variation, with a worst-case GBW of 3.71 kHz at the slow–slow (SS) corner.

Despite this reduction, the worst-case performance remains entirely adequate for its target application domain in biomedical signal acquisition. Diagnostic electrocardiogram (ECG) signals, for instance, typically occupy a bandwidth of 0.05–250 Hz, while the bandwidth of a clinical electroencephalogram (EEG) is generally below 150 Hz. Even at the SS corner, the achieved 3.71 kHz GBW provides sufficient margin for amplifying these low-frequency biosignals without distortion. Slew rate requirements further confirm this suitability. For diagnostic ECG, considering the highest frequency component of 150 Hz and a peak input amplitude of 0.3 mV (assuming subsequent amplification), the required slew rate can be estimated as $S{R}_{req}=2\pi \times 150\times 0.3\approx 0.28$ V/ms. The proposed design delivers a worst-case slew rate of 1.84 V/ms, exceeding this requirement by a factor of six.

However, while GBW and slew rate remain sufficient for basic amplification, PVT-induced variations can impact other critical performance metrics. Shifts in settling time and bandwidth, for example, could compromise the accuracy of high-gain configurations or the timing of time-multiplexed sensor interfaces. Furthermore, because transconductance in subthreshold decreases with rising temperature, input-referred noise and gain can vary across the operating temperature range. For more demanding applications requiring precise filter cutoff frequencies or higher sampling rates, these sensitivities may necessitate additional compensation. Adaptive bias stabilization or proportional-to-absolute-temperature (PTAT) current sources could be incorporated to stabilize transconductance and reduce GBW sensitivity across temperature.

The underlying cause of this sensitivity can be traced to the biasing structure of the auxiliary branch. In the proposed architecture, the currents through transistors NM3, NM4, and NM5 are not derived from an independent, stable bias reference. Instead, they are established indirectly through an internal current-mirroring path originating from the input stage. Consequently, the bias currents of these devices are fundamentally dependent on the operating points of upstream transistors, rendering them more susceptible to both PVT variations and device mismatch. Since the transconductances of NM3–NM5 directly influence the output stage drive strength and the feedforward path within the MMZCC network, any fluctuation in their bias currents propagates directly to the amplifier’s dynamic response. Variations in these bias conditions shift the effective transconductance and alter the pole-zero locations established by the compensation network, leading to the observed fluctuations in GBW and slew rate. These effects will be further quantified in the Monte Carlo simulation results.

Mitigating these PVT-induced variations is achievable through established circuit techniques. Employing a regulated bias current can stabilize the operating point of the OTA. By precisely controlling the bias current in the subthreshold region, variations in drain current and transconductance can be significantly suppressed, yielding a more robust design across process and temperature corners. Additionally, ensuring a clean, well-regulated supply voltage minimizes supply-induced fluctuations, further enhancing overall performance robustness and making the design more resilient for deployment in real-world, energy-harvesting environments.

Figure 9 presents the Monte Carlo simulation results for 200 samples, performed with the “ALL” variation option that encompasses both global process variations and local mismatch. For PSRR, variations with a standard deviation below 3 dB are regarded as not significant, a criterion comfortably satisfied, indicating that the amplifier’s rejection of supply noise remains robust despite device mismatch. Similarly, input-referred noise exhibits exceptional stability, with a standard deviation of only 2.37 nV/√Hz. This minimal variation confirms that the noise performance, fundamentally determined by the input pair’s transconductance and thermal noise contribution, is well-controlled even under mismatch, representing a critical attribute for biomedical applications where signal integrity is paramount.

However, as anticipated for circuits operating in deep subthreshold, where the drain current exhibits an exponential dependence on threshold voltage ($V_{th}$), this translates directly into noticeable changes in bias current and transconductance. This fundamental sensitivity propagates through other performance metrics. CMRR exhibits a standard deviation of 6.33 dB, with minimum and maximum values of 64.81 dB and 109.22 dB, respectively. This spread reflects mismatch-induced variations affecting both the differential-mode and common-mode gain paths. Nevertheless, the minimum CMRR of 64.81 dB remains a respectable value for low-frequency biomedical applications. For the same underlying reasons, DC gain shows notable variation, with the minimum value dropping to 23.86 dB under worst-case mismatch. While this represents a reduction from the nominal gain, it remains sufficient for many closed-loop biomedical amplifier configurations where gain is precisely set by feedback resistor ratios rather than open-loop gain.

GBW and phase margin are similarly influenced by mismatch. The worst-case GBW decreases to 7.11 kHz, a reduction from the nominal value, yet still more than adequate for processing biosignals such as ECG and EEG. Phase margin maintains a worst-case value of 53.69°, confirming that the circuit remains stable with adequate phase margin under all simulated mismatch conditions, ensuring robust closed-loop operation.

Input offset voltage, a critical parameter for precision amplification, demonstrates the expected sensitivity to device mismatch. The offset varies from −2 mV to 1.8 mV, with a standard deviation of 636.3 μV. To understand the practical implications, consider a worst-case scenario combining a 2 mV input offset with a DC gain of 44.34 dB. The corresponding DC output offset can be estimated as

$$V_{out}\approx {10}^{{\displaystyle \frac{44.24}{20}}}·2 \mathrm{m}\mathrm{V}\approx 326 \mathrm{m}\mathrm{V}$$

This value exceeds the 300 mV supply voltage, which would indeed saturate the output if the amplifier were operated in an open-loop configuration. However, in practical biomedical sensor front-end circuits, this is not the intended mode of operation. Real-world implementations routinely mitigate DC offsets using established techniques such as AC coupling via on-chip capacitors or DC servo loops, which are standard in bio-signal acquisition systems to block electrode offset potentials and ensure the signal remains within the amplifier’s linear range. These system-level strategies effectively manage offset variations, ensuring the circuit remains fully functional in its target application environment despite the inherent mismatch sensitivity of the core amplifier.

In summary, the Monte Carlo results confirm that while mismatch-induced variations are non-negligible, as expected for any deeply scaled, ultra-low-voltage design operating in weak inversion, the circuit’s core performance metrics consistently meet the requirements of low-frequency biomedical sensing. The combination of stable PSRR and input noise, adequate minimum CMRR, sufficient GBW for biosignal bandwidths, guaranteed stability, and system-level offset mitigation strategies ensures that the proposed OTA remains a viable and robust building block for energy-constrained biomedical interfaces.

The performance of the proposed OTA is compared with other ULV OTA designs reported in the literature over the past five years, as summarized in

Table 6. Performance comparison of sub-0.5 V OTA.

Parameter	This Work	[51] 2023	[41] 2022	[52] 2022	[53] 2021	[40] 2021	[38] 2021	[37] 2021	[44] 2020
Technology, [nm]	45	130	180	180	130	130	180	130	65
${\mathit{V}}_{\mathit{D}\mathit{D}}$, [V]	0.3	0.3	0.5	0.4	0.3	0.3	0.5	0.3	0.25
${\mathit{C}}_{\mathit{L}}$, [pF]	30	35	20	2 × 15	50	50	200	40	15
DC gain, [dB]	44.24	86.83	95	60	64.6	38.07	86.55	40.8	70
GBW, [kHz]	9.87	10.32	12.82	7	3.58	24.14	25.1	18.65	9.5
Phase margin, [°]	53.93	58.27	55.7	60.2	53.76	60.15	93.64	51.93	88
SR+, [V/ms]	4.64	2.32	15.81	78	1.7	20.02	5.62	10.83	2
SR-, [V/ms]	7.83	5.14	16.69	80	0.15	8.44	7.47	32.37	2
${\mathit{S}\mathit{R}}_{\mathit{a}\mathit{v}\mathit{g}}$, [V/ms]	6.24	3.73	16.25	79	0.93	14.23	6.54	21.60	2
CMRR, [dB]	87.48	57.8	60	85.4	61	54.88	108.32	67.49	62.5
PSRR, [dB]	41.13	46.59	66	76.3	28	51.05	95.86	45	38
Power, [nW]	23.28	33.73	313	24	11.4	59.88	178	73	26
THD, [%]	0.8	0.2	0.28	-	0.84	1.63	-	1.4	-
Input noise, [${\displaystyle \frac{\mathsf{\mu }\mathbf{V}}{\sqrt{\mathbf{H}\mathbf{z}}}}$] @1 kHz	1.02	2.86	0.88 *	0.31	2.69 **	3.156	0.775	2.12	-
Operation Mode	BD	BD	MI-BD	BD	BD	BD	BD	BD	BD
ICMR/${\mathit{V}}_{\mathit{D}\mathit{D}}$, [%]	100	73	100	100	100	80	100	100	100
Area, [${\mathbf{m}\mathbf{m}}^2$]	0.0044	0.0023	-	0.0079	0.0064	0.0027	0.0099	0.0036	0.002
${\mathit{F}\mathit{O}\mathit{M}}_1$	12.72	10.7	0.82	4.38	15.7	20.16	28.2	10.21	5.48
${\mathit{F}\mathit{O}\mathit{M}}_2$	8.04	3.87	1.04	49.38	4.07	11.88	7.35	11.84	1.15
${\mathit{F}\mathit{O}\mathit{M}}_3$	3.68	0.6	0.22	11.48	1.99	0.29	0.79	0.44	-
${\mathit{F}\mathit{O}\mathit{M}}_4$	140.37	34.55	7.26	336.02	108.7	17.64	14.5	21.54	-
${\mathit{F}\mathit{O}\mathit{M}}_5$	42.4	35.67	1.64	10.95	52.33	67.2	56.4	34.03	21.92
${\mathit{F}\mathit{O}\mathit{M}}_6$	26.8	12.9	2.08	123.45	13.57	39.6	14.7	39.47	4.6

* The frequency is not specified in the original reference. ** Input noise is evaluated at 100 Hz.

. From the comparison in Table 6, it can be observed that the proposed OTA demonstrates outstanding CMRR compared to other designs. The gain–bandwidth products (GBWs) of the various designs are generally in a similar range, as the operating speed of ultra-low-power circuits is fundamentally limited by the low supply voltage and power constraints, making these designs unsuitable for high-speed applications. It is also noticeable from Table 6 that the gain values across different designs vary significantly. This variation is largely influenced by the choice of amplifier topology. For example, the designs reported in [31,34,43] utilize three-stage amplifier structures, which enable higher gain but also require more complex compensation schemes to maintain stability.

To enable a rigorous and fair comparison of both small-signal and large-signal performance across different OTA designs, this work employs a comprehensive set of six figures of merit (FOMs). These metrics are carefully chosen to capture not only conventional speed-power trade-offs, but also noise robustness and supply-voltage scalability, which represent critical considerations in ULV design.

The first two FOMs address fundamental performance dimensions. ${FOM}_1$ measures how efficiently an OTA converts power into bandwidth under a given capacitive load, reflecting small-signal behavior. ${FOM}_2$ extends this by incorporating the average slew rate, thereby capturing large-signal transient efficiency, a key metric for applications requiring rapid signal changes. Together, they provide a baseline assessment of speed-power trade-offs:

$${FOM}_1={\displaystyle \frac{GBW·C_L}{P}} \left[{\displaystyle \frac{\mathrm{k}\mathrm{H}\mathrm{z}·\mathrm{p}\mathrm{F}}{\mathrm{n}\mathrm{W}}}\right]$$

(22)

$${FOM}_2={\displaystyle \frac{{SR}_{avg}·C_L}{P}} \left[{\displaystyle \frac{\mathrm{V}·\mathrm{p}\mathrm{F}}{\mathrm{n}\mathrm{W}·\mathrm{m}\mathrm{s}}}\right]$$

(23)

For biomedical and sensor interface applications, noise performance and common-mode rejection are equally vital. ${FOM}_3$ and ${FOM}_4$ are therefore introduced to evaluate noise robustness and low-voltage efficiency. ${FOM}_3$ normalizes the CMRR by both power consumption and input noise, yielding a metric that captures the amplifier’s ability to reject interference while maintaining low intrinsic noise and power efficiency. ${FOM}_4$ provides a compact measure of how efficiently the OTA achieves low-noise performance under voltage-scaled operation, offering insight into its suitability for deeply scaled supply voltages:

$${FOM}_3={\displaystyle \frac{CMRR}{P·IN}}\left[{\displaystyle \frac{\mathrm{d}\mathrm{B}·\sqrt{\mathrm{H}\mathrm{z}}}{\mathrm{n}\mathrm{W}·\mathsf{\mu }\mathrm{V}}}\right]$$

(24)

$${FOM}_4={\displaystyle \frac{1}{P·IN·V_{DD}}} \left[{\displaystyle \frac{\sqrt{\mathrm{H}\mathrm{z}}}{\mathrm{n}\mathrm{W}·\mathrm{m}\mathrm{V}·\mathrm{V}}}\right]$$

(25)

Finally, recognizing that designs may operate under different supply voltages, ${FOM}_5$ and ${FOM}_6$ extend ${FOM}_1$ and ${FOM}_2$ by incorporating supply-voltage normalization. This adjustment removes the voltage-dependent bias, enabling a fairer comparison across designs implemented with varying voltage headroom:

$${FOM}_5={\displaystyle \frac{GBW·C_L}{P·V_{DD}}} \left[{\displaystyle \frac{\mathrm{k}\mathrm{H}\mathrm{z}·\mathrm{p}\mathrm{F}}{\mathrm{n}\mathrm{W}·\mathrm{V}}}\right]$$

(26)

$${FOM}_6={\displaystyle \frac{{SR}_{avg}·C_L}{P·V_{DD}}} \left[{\displaystyle \frac{\mathrm{p}\mathrm{F}}{\mathrm{n}\mathrm{W}·\mathrm{m}\mathrm{s}}}\right]$$

(27)

In these expressions, GBW is the gain–bandwidth product, C_L is the load capacitance, P is the power consumption, SR_avg is the average slew rate, CMRR is the common-mode rejection ratio, IN is the input-referred noise, and V_DD is the supply voltage. Collectively, ${FOM}_1$ through $FOM$ provide a multidimensional assessment of OTA performance, where higher values indicate superior overall efficiency and capability.

Compared with other ULV OTA designs (see Figure 10), the proposed OTA demonstrates strong performance in terms of ${FOM}_3$ and ${FOM}_4$, ranking second only to [52]. The superior FoM values reported in [52] are primarily attributed to its significantly lower input noise, which directly benefits both FoMs. The noise is evaluated at 1000 Hz, where the spectrum is predominantly thermal noise dominated. In this operating region, the 180 nm technology benefits from more ideal long-channel carrier transport and reduced short-channel effects, which limit the increase in the excess noise factor associated with device downscaling and thereby enable lower thermal noise for the same bias current [54]. Although design [52] outperforms the proposed OTA in terms of gain, slew rate, and PSRR, the proposed design operates at a lower supply voltage, which can be a critical requirement in certain ULV applications. In addition, the proposed OTA is capable of driving a larger load capacitance, supporting 30 pF compared to 15 pF in [51], corresponding to a twofold increase in capacitive load.

In evaluating the proposed OTA against commonly used figures of merit (FOMs) for ULV designs, the circuit demonstrates competitive, though not peak, performance in FOM₁ and FOM₂. This outcome reflects the deliberate design emphasis on minimizing power consumption over maximizing speed. Slew rate was intentionally deprioritized in favor of energy efficiency, resulting in a conscious trade-off between bandwidth, transient response, and power dissipation.

For FOM₁, while designs [38,40,53] achieve superior performance, this comes at a substantial power cost. Both [38,40] consume significantly more power than the proposed OTA, whereas [52] exhibits a lower GBW despite comparable power levels. Thus, the proposed design achieves a balanced trade-off between power consumption and small-signal bandwidth, offering an attractive compromise for power-constrained applications. For FOM₂, designs [37,38,40,41] demonstrate higher slew rates, but again at the expense of dramatically increased power consumption ranging from 157% to 664% higher than the proposed design. As Equations (20) and (21) indicate, slew rate in this architecture is directly proportional to bias current; therefore, the design can be scaled for higher speed by increasing current, with a corresponding power penalty. This flexibility allows the trade-off between slew rate and power to be tailored to specific application requirements.

FOM₅ and FOM₆, which incorporate supply-voltage normalization, exhibit trends consistent with FOM₁ and FOM₂. Since all compared designs operate below 0.5 V, the supply-voltage differences are relatively modest; consequently, normalization introduces only minor variations, and the comparative rankings remain largely unchanged.

Regarding DC gain, designs [38,41,44,51,52,53] achieve higher values than the proposed OTA. A straightforward path to increasing gain would be the introduction of a third amplification stage. However, this would necessitate a corresponding redesign of the compensation network to maintain adequate phase margin and ensure stability. This represents a promising direction for future work.

A distinct advantage of the proposed design lies in its suitability for mixed-signal system integration. The 45 nm CMOS technology employed presents certain challenges for ULV analog design, including reduced intrinsic gain and increased noise compared to more mature nodes. However, this technology offers substantial benefits for digital circuitry, where shorter channel lengths enable faster switching speeds and higher integration density. Consequently, relative to designs implemented in older process nodes, the proposed OTA is better positioned for integration in mixed-signal systems-on-chip that combine sensitive analog front-ends with extensive digital processing, an increasingly common requirement in modern IoT and biomedical devices.

5. Conclusions

In conclusion, this work successfully presents an ultra-low-voltage (ULV) operational transconductance amplifier (OTA) designed for a 0.3 V supply in a 45 nm CMOS process. By synergistically integrating a bulk-driven input stage with a current-reuse architecture and a multipath Miller zero-cancellation compensation, the design achieves an exceptional combination of high common-mode rejection ratio (CMRR of 87.48 dB) and ultra-low power consumption (23.28 nW), alongside a rail-to-rail input range. This performance profile makes the OTA particularly suitable for very-low-frequency, power-starved sensor interfaces, such as those in biomedical monitoring (e.g., EEG/ECG) and always-on IoT nodes, where high CMRR is paramount for rejecting environmental interference.

A comparative analysis confirms the design’s favorable CMRR and power efficiency relative to recent ULV OTAs. However, the investigation also identifies a primary limitation: critical performance metrics, including gain–bandwidth product and slew rate, exhibit significant sensitivity to process, voltage, and temperature (PVT) variations, a characteristic challenge of subthreshold operation. The performance shift observed between pre- and post-layout simulations further underscores the impact of parasitics.

Therefore, the critical next steps for this research are the fabrication and experimental characterization of the proposed OTA to validate its post-layout performance. Future work must directly address the PVT robustness challenge through the on-chip integration of a stable, ultra-low-voltage bias reference circuit. Finally, demonstrating the OTA within a complete system-level block, such as a Gm-C filter or sensor front-end, will solidify its practical utility and transition the design from simulation to a viable component for next-generation ultra-low-power systems.