A Class-AB Reference Voltage Buffer for SC Circuits in Pipelined ADCs

Abstract

This paper introduces the design of a reference voltage buffer (RVB) for pipelined analog-to-digital converters (ADCs) in a 180 nm CMOS process with a 1.8 V supply voltage. The loop stability of the proposed RVB is verified by the theoretical calculations. The driving capability of the proposed RVB is demonstrated by its large driving current, and the transient response simulation results reveal its impressive speed and precision in the reference voltage settling process. Moreover, the power supply rejection ratio (PSRR) performance indicates that the proposed RVB is insensitive to the variation in power supply voltage, meeting the application requirements for high-speed and high-precision pipelined ADCs.

1. Introduction

In the field of high-speed analog-to-digital converters, the pipelined architecture is widely employed in communication [1,2], medical imaging [3,4], industrial measurement [5,6], and other fields. By decomposing the high-resolution conversion task into multi-stage low-resolution subtasks, and allocating them to multi-stage multiplying digital-to-analog converters (MDACs), the pipelined ADCs are widely applied in both low-to-moderate resolution (6–10 bits) [7,8,9,10,11] and high-resolution (≥14 bits) [12,13,14,15] while maintaining the high sampling rate.

A typical MDAC consists of a sampling switched-capacitor circuit and a residue amplifier. In the conversion process, sub-ADCs and RVB provide comparison results and reference voltage for the DAC capacitor array, respectively. The performance of the pipelined ADC will be significantly determined by the stability and efficiency of the RVB [16]. Moreover, high-speed pipelined ADCs require a fast-settling reference voltage with an error less than the least significant bit (LSB). A traditional differential RVB generally employs a cascode circuit as the output stage, and an excessively long time is sacrificed for the high-precision requirement in ADCs [17]. The unsatisfactory settling time indicates the insufficient driving capability of the traditional RVB, which constrains the size of the capacitor array in the pipelined ADC. This issue would severely limit the precision of the pipelined ADC. The flipped voltage follower and the parallel slew-rate enhancer are proposed by Refs. [18,19]; both of these techniques are able to improve the driving capability of differential RVBs. However, the output stage of differential RVBs requires strong driving capabilities for both P-side and N-side outputs, which presents considerable design challenges. It is only necessary to improve the driving capability of the single-ended output in single-ended RVBs when the ground voltage is adopted as the N-side reference voltage.

A new RVB consisting of two source followers is proposed by Ref. [20]. The key advantage of this RVB is that a sufficient driving current is actively supplied by the source followers. Inspired by this method of enhancing RVBs’ driving capabilities, several studies about Class-AB RVBs are presented. Ref. [21] proposes to separate the bias current generation circuit from the RVB by adding a replica circuit to form the negative feedback for less area consumption, and the Class-AB RVB composed of two push–pull source followers is used in each sub-ADC. Ref. [22] suggests the push–pull source followers as the output stage circuit for composing the Class-AB RVB, and the ground voltage is employed as the N-side reference voltage for reducing design complexity. Moreover, Ref. [23] adds the chopper stabilization for mitigating thermal noise and flicker noise in the loop of the Class-AB RVB. In comparison with other conventional differential RVBs with two high-gain operational amplifiers (P-side and N-side) [24,25,26], the single-ended Class-AB RVBs employ only one amplifier to buffer the reference voltage. The power consumption of RVBs can be significantly reduced in this way. However, there is only one NMOS between the output reference and the supply voltage in Refs. [21,22], which means that the reference voltage is sensitive to the power supply voltage. In other words, the performance of PSRR determines the accuracy of the reference voltage in RVB design. It is desired to design a novel Class-AB RVB with both excellent driving capability and stability.

Herein, the process of reference voltage settling in SC circuits of pipelined ADCs is first discussed. Secondly, the loop stability of the proposed RVB is provided by theoretical analysis. Thirdly, the driving current, transient response, and PSRR of the proposed novel RVB are simulated in different process corners. Lastly, the performance of the proposed RVB is compared with that of other previous RVBs in Table 2.

2. The Process of V_REF Settling

Figure 1 shows the simplified MDAC of pipelined ADCs, which consists of an SC circuit and an amplifier.${\mathit{V}}_{\mathrm{IN}}$ is the input voltage and ${\mathit{V}}_{\mathrm{REF}}$ is the reference voltage. ${\mathit{C}}_{\mathrm{S}}$ tracks ${\mathit{V}}_{\mathrm{IN}}$ and the output of the RVB when ${\Phi }_1$ and ${\Phi }_2$ switch on, respectively. The timing diagram of switches displays that the time of ${\mathit{V}}_{\mathrm{REF}}$ settling takes up almost half of the duty cycle, which indicates the driving capability of the RVB largely influences the speed limit of the high-performance pipelined ADCs. Both the sampling process of ${\mathit{V}}_{\mathrm{IN}}$ and the settling process of ${\mathit{V}}_{\mathrm{REF}}$ are related to the value of ${\mathit{V}}_{\mathrm{S}}$. As a result, it is worth analyzing the variations in ${\mathit{V}}_{\mathrm{S}}$ in periods.

As shown in Figure 2, the input voltage is set to ${\mathit{V}}_{\mathrm{IN}}$ = ${\mathit{V}}_{\mathrm{CM}}$ + 0.5${\mathit{V}}_{\mathrm{REF}}$sin(2πt/T). Therefore, the maximum and minimum sampling voltage is ${\mathit{V}}_{\mathrm{smp},\max }$ (${\mathit{V}}_{\mathrm{CM}}$ + 0.5${\mathit{V}}_{\mathrm{REF}}$) and ${\mathit{V}}_{\mathrm{smp},\min }$ (${\mathit{V}}_{\mathrm{CM}}-0.5{\mathit{V}}_{\mathrm{REF}}$), respectively. ${\mathit{V}}_{\mathrm{S}}$ is reduced from ${\mathit{V}}_{\mathrm{smp},\max }$ to ${\mathit{V}}_{\mathrm{REF}}$ during the first ${\mathit{V}}_{\mathrm{REF}}$ settling period, which is a discharge process. On the contrary, ${\mathit{V}}_{\mathrm{S}}$ is charged from ${\mathit{V}}_{\mathrm{smp},\min }$ to ${\mathit{V}}_{\mathrm{REF}}$ during the second ${\mathit{V}}_{\mathrm{REF}}$ settling period. A wide pull–push voltage range requires the RVB in Figure 1 to exhibit a strong Class-AB characteristic in high-precision pipelined ADCs.

Taking the second ${\mathit{V}}_{\mathrm{REF}}$ settling period as an example in Figure 3, it is clear that the process of the ${\mathit{V}}_{\mathrm{REF}}$ settling can be divided into two parts based on the voltage changing rate. The first part is large signal settling, and 90% of the charging process is completed within ${\mathit{t}}_{\mathrm{lst}}$ in this part. The other 10% of the ${\mathit{V}}_{\mathrm{REF}}$ settling process is finished within ${\mathit{t}}_{\mathrm{sst}}$ in another part, which is called small signal settling. The relationship between the settling time of ${\mathit{V}}_{\mathrm{REF}}$ and the sampling rate of the pipelined ADC is

$$\begin{array}{cc}\hfill t_{\mathrm{lst}}+t_{\mathrm{sst}}& \le {\displaystyle \frac{1}{2f_{\mathrm{s}}}}.\hfill \end{array}$$

(1)

Consequently, fast ${\mathit{V}}_{\mathrm{REF}}$ settling is critical to pipelined ADCs in high-speed applications.

${\mathit{V}}_{\mathrm{S}}$ varies linearly at a defined quiescent operating point during the small signal settling. Therefore, for the convenience of calculation, the small signal settling is considered first. The $\mathit{s}$-domain circuit in small signal settling is depicted in Figure 4, where the RVB is modeled using Thevenin’s theorem. The initial voltage of ${\mathit{V}}_{\mathrm{S}}$ is set to ${\mathit{V}}_{\mathrm{REF}}$−$0.1\Delta V$ (assuming the large signal settling is ideal). The $\mathit{t}$-domain function of ${\mathit{V}}_{\mathrm{S}}$ can be written as

$$\begin{array}{cc}\hfill V_{\mathrm{S}}\left(t\right)& =V_{\mathrm{REF}}\left(1-e^{-{\displaystyle \frac{t}{r_{\mathrm{O}}{C}_{\mathrm{S}}}}}\right)+\left(V_{\mathrm{REF}}-0.1\Delta V\right)e^{-{\displaystyle \frac{t}{r_{\mathrm{O}}{C}_{\mathrm{S}}}}}\hfill \\ \hfill & =V_{\mathrm{REF}}-0.1\Delta V{e}^{-{\displaystyle \frac{t}{r_{\mathrm{O}}{C}_{\mathrm{S}}}}}.\hfill \end{array}$$

(2)

However, ${\mathit{V}}_{\mathrm{S}}$ needs to satisfy $|{\mathit{V}}_{\mathrm{S}}$(${\mathit{t}}_{\mathrm{sst}}$) −${\mathit{V}}_{\mathrm{REF}}|$ ≤ $\mathit{LSB}$ after the small signal settling. As a result, the time of small signal settling can be calculated as

$$\begin{array}{c}\hfill t_{\mathrm{sst}|\min }=r_{\mathrm{O}}{C}_{\mathrm{S}}ln{\displaystyle \frac{0.1|\Delta V|}{LSB}}.\end{array}$$

(3)

According to (3), the smaller the ${\mathit{r}}_{\mathrm{O}}$ of the RVB, the shorter the ${\mathit{t}}_{\mathrm{sst}|\min }$. Therefore, the RVB with low output resistance is efficient in reducing the settling time of the reference voltage, which is beneficial to realize high-speed pipelined ADCs.

Figure 3. Details of the second ${\mathit{V}}_{\mathrm{REF}}$ settling period.

Figure 3. Details of the second ${\mathit{V}}_{\mathrm{REF}}$ settling period.

Figure 4. $\mathit{s}$-domain circuit in small signal settling.

Figure 4. $\mathit{s}$-domain circuit in small signal settling.

The conventional RVB is mainly designed based on the single-transistor source follower, and its output resistance is about 1/${\mathit{gm}}_1$. The source follower with an added amplifier is proposed in Figure 5a, and it is clear that a negative feedback network is formed between M1 and the amplifier to stabilize the output voltage. The output resistance of Figure 5a can be calculated as about 1/(${\mathit{gm}}_1$${\mathit{A}}_{\mathrm{V}}$), which is reduced to 1/${\mathit{A}}_{\mathrm{V}}$ of the original source follower. More importantly, a negative feedback is formed by the amplifier with M1, which enables the output voltage to follow the input voltage accurately. Furthermore, Figure 5a is employed as the RVB, as shown in Figure 5b. ${\mathit{I}}_{\mathrm{charge}}$ and ${\mathit{I}}_{\mathrm{discharge}}$ correspond to the driving currents of the second and the first ${\mathit{V}}_{\mathrm{REF}}$ large signal settlings in Figure 2, respectively. The time of the two large signal settlings can be derived as

$$\begin{array}{cc}\hfill 0.9\Delta V{C}_{\mathrm{S}}& ={\int }_0^{t_{\mathrm{lst}}}{I}_{\mathrm{charge}}d{t}_{(\Delta V>0)}\hfill \\ \hfill 0.9\Delta V{C}_{\mathrm{S}}& ={\int }_0^{t_{\mathrm{lst}}}{I}_{\mathrm{discharge}}d{t}_{(\Delta V<0)},\hfill \end{array}$$

(4)

where the ${\mathit{I}}_{\mathrm{charge}}$ and ${\mathit{I}}_{\mathrm{discharge}}$ are the driving currents. According to (4), regardless of $\Delta \mathit{V}$ < 0 or $\Delta \mathit{V}$ > 0, the RVB is required to generate a large driving current for achieving short ${\mathit{t}}_{\mathrm{lst}}$. As can be seen in Figure 5b, when $\Delta \mathit{V}$ < 0, ${\mathit{V}}_{\mathrm{S}}$ is able to be discharged quickly in large signal settling due to the divergent ${\mathit{I}}_{\mathrm{discharge}}$. However, since the largest ${\mathit{I}}_{\mathrm{charge}}$ is limited to ${\mathit{I}}_1$, the ${\mathit{t}}_{\mathrm{lst}}$ of charging ${\mathit{V}}_{\mathrm{S}}$ is predictably long. Therefore, the RVB in Figure 5a does not possess a Class-AB characteristic, although its output resistance is reduced by the amplifier. As a result, the source follower with an amplifier is not suitable for use as an RVB directly.

Figure 6a displays the structure of the Class-AB RVB. It can be seen that M1 and M2 directly provide divergent ${\mathit{I}}_{\mathrm{discharge}}$ and ${\mathit{I}}_{\mathrm{charge}}$, respectively. Nonetheless, the output resistance of Figure 5a is about 1/(${\mathit{gm}}_1$ + ${\mathit{gm}}_2$), which limits the speed of the small signal settling. By adding an amplifier to comprise a negative feedback network with M1 and M2 as plotted in Figure 6b, the output resistance is reduced to about 1/(${\mathit{gm}}_1$${\mathit{A}}_{\mathrm{V}}$).

As shown in Figure 7a, the structure of Figure 6b is employed to settle ${\mathit{V}}_{\mathrm{REF}}$. In the Class-AB type output stage, the numbers of M1 and M2 are set to $\mathit{n}$ ($\mathit{n}$ > 1). However, it is obvious that the loop characteristics are influenced by ${\mathit{C}}_{\mathrm{S}}$. In this case, the loop stability is worthy of consideration. The loop is broken at the inverting input of the amplifier, and the small signal circuit is displayed in Figure 7b. The amplifier is Norton-equivalent to a parallel combination of a current source and an output resistor. The transfer function can be calculated as

$$\begin{array}{c}\hfill {\displaystyle \frac{v_{\mathrm{OUT}}}{v_{\mathrm{IN}}}}={\displaystyle \frac{-G{M}_{\mathrm{A}}{R}_{\mathrm{O}}g{m}_{12}{r}_{\mathrm{O}12}}{s{C}_{\mathrm{S}}{r}_{\mathrm{O}12}+g{m}_{12}{r}_{\mathrm{O}12}+1}},\end{array}$$

(5)

where ${\mathit{gm}}_{12}$ = $\mathit{n}$(${\mathit{gm}}_1$ + ${\mathit{gm}}_2$) and ${\mathit{r}}_{\mathrm{O}12}$ = (${\mathit{r}}_{\mathrm{O}1}$ // ${\mathit{r}}_{\mathrm{O}2}$)/n. Equation (5) reveals that a large ${\mathit{C}}_{\mathrm{S}}$ contributes a low-frequency pole during loop settling, which could extend the small signal settling time. Different from Figure 4, the ${\mathit{V}}_{\mathrm{REF}}$ small signal settling on ${\mathit{C}}_{\mathrm{S}}$ in Figure 7a is not a simple first-order RC settling model due to the changeable gate voltages of nM1 and nM2. Moreover, the loop needs to be re-established during each ${\mathit{V}}_{\mathrm{REF}}$ settling process, which limits the speed of ADCs. As a result, it is significant to separate ${\mathit{C}}_{\mathrm{S}}$ from the loop in the Class-AB RVB architecture.

To avoid the loading effect in Figure 7a, the replica source-follower is used to isolate the loop from the large ${\mathit{C}}_{\mathrm{S}}$ as depicted in Figure 8 [27,28,29,30,31,32]. Thanks to the replica-driving technique, the loop in the dotted box is independent and stable during each ${\mathit{V}}_{\mathrm{REF}}$ settling process, and the open-loop ${\mathit{V}}_{\mathrm{REF}}$ settling only depends on the Class-AB type output stage. Meanwhile, the settling voltage on ${\mathit{C}}_{\mathrm{S}}$ is precisely mirrored from the negative feedback loop without loading effect. Although the output resistance is not considerably small (1/(n${\mathit{gm}}_1$ + n${\mathit{gm}}_2$)), stable gate voltages of M1 and M2 are more decisive factors in fast small signal settling.

As outlined above, the framework in Figure 8 offers two key advantages. First, for different capacitive loads, the driving current can be directly and dynamically supplied by ($\mathit{n}-1$)M1 and ($\mathit{n}-1$)M2. This Class-AB feature achieves a superior slew rate of the output stage. Strong driving capability is well-suited for the pipelined ADC applications that demand high-speed performance. On the other hand, the gate voltages of ($\mathit{n}-1$)M1 and ($\mathit{n}-1$)M2 are linked to the input voltage by a negative feedback network, which defines the final value of the output reference voltage without the load effect. However, ${\mathit{V}}_{\mathrm{DC}}$ in Figure 8 is an ideal model. As a result, ${\mathit{V}}_{\mathrm{DC}}$ can provide a voltage drop for the DC bias while transmitting AC small signals in the negative feedback network. In practical circuits, implementing the negative feedback loops for both M1 and M2 requires more elaborate calculations and settings for the RVB’s quiescent operating point.

Based on the design signal of negative feedback and Class-AB output stage, ref. [21] presents a Class-AB RVB for a 12-bit 250 MS/s pipelined SAR ADC, as shown in Figure 9a. There are kinds of capacitors in each sub-ADC, and MDAC needs to be charged or discharged by the RVB. In order to obtain stable gate voltages of ($\mathit{n}-1$)M1 and ($\mathit{n}-1$)M2 and reduce the noise interference, the low-pass filters (LPFs) are added in each Class-AB output stage. In contrast to the clear circuit topology and noise cancellation of the output stage, the analysis of the bias circuit of M1 and M2 is even more critical. In Figure 9a, M3 and M4 are equal to M1 and M2, respectively. The negative feedback loop1 (red) is formed by M1 and the operational amplifier: ${\mathit{V}}_{\mathrm{G},\mathrm{M}1}$ increases → ${\mathit{V}}_{\mathrm{S},\mathrm{M}1}$ increases → ${\mathit{V}}_{\mathrm{INN},\mathrm{AMP}}$ increases → ${\mathit{V}}_{\mathrm{OUT},\mathrm{AMP}}$ (${\mathit{V}}_{\mathrm{G},\mathrm{M}1}$) decreases. M3, M4, M5, M6 and ${\mathit{I}}_{\mathrm{B}}$ are designed to generate the bias voltage of M2. Meanwhile, the negative feedback loop2 (blue) is also formed: ${\mathit{V}}_{\mathrm{G},\mathrm{M}3}$ increases → ${\mathit{V}}_{\mathrm{S},\mathrm{M}4}$ increases → ${\mathit{V}}_{\mathrm{G},\mathrm{M}4}$ increases → ${\mathit{V}}_{\mathrm{S},\mathrm{M}2}$ increases → ${\mathit{V}}_{\mathrm{INN},\mathrm{AMP}}$ increases → ${\mathit{V}}_{\mathrm{OUT},\mathrm{AMP}}$ (${\mathit{V}}_{\mathrm{G},\mathrm{M}3}$) decreases. It is clear that loop1 and loop2 interact with each other. In order to analyze the negative feedback network in the bias circuit more accurately, a loop-breaking process is performed at the output of the operational amplifier. The small signal diagram of the feedback network is shown in Figure 9b. The output and negative input terminals of the operational amplifier are defined as ${\mathit{v}}_{\mathrm{i}}$ and ${\mathit{v}}_{\mathrm{o}}$ for obtaining the feedback factor $\beta$:

$$\begin{array}{c}\hfill {\displaystyle \frac{v_{\mathrm{o}}}{v_{\mathrm{i}}}}=\beta ={\displaystyle \frac{{gm}_{1+(\frac{g{m}_{3}g{m}_2{r}_{\mathrm{o}5}}{\frac{1}{\frac{1}{g{m}_4}//r_{\mathrm{o}4}+r_{\mathrm{o}5}}+\frac{1}{r_{\mathrm{o}4}}+g{m}_3})(\frac{1}{g{m}_4}//r_{\mathrm{o}4}+r_{\mathrm{o}5})}}{g{m}_1+\frac{1}{r_{\mathrm{o}1}}+g{m}_2+\frac{1}{r_{\mathrm{o}2}}}}.\end{array}$$

(6)

The approximation that ${\mathit{r}}_{\mathrm{o}}$ >> 1/gm yields the result that β ≈ 1. With the ideal amplifier assumption (${\mathit{A}}_{\mathrm{V}}$ = +∞), the transfer function of Figure 9a can be derived as:

$$\begin{array}{c}\hfill {\displaystyle \frac{V_{\mathrm{OUT}}}{V_{\mathrm{REF}}}}={\displaystyle \frac{A_{\mathrm{V}}}{1+A_{\mathrm{V}}\beta }}\approx {\displaystyle \frac{1}{\beta }}\approx 1.\end{array}$$

(7)

Based on the calculation results and the circuit configuration, as an RVB, Figure 9a achieves output-to-input tracking while maintaining great Class-AB characteristics. However, to generate a reference voltage of 1.2 V, the circuit of Figure 9a operates with a 2.5 V supply voltage, which results in considerable quiescent power consumption (the overall power consumption of the pipelined SAR ADC is 31.5 mW). Moreover, using both thick-oxide NMOS transistors and thin-oxide PMOS transistors also increases the design complexity of the RVB.

For overcoming the power consumption issue of Figure 9a, a low-power Class-AB RVB is presented and applied in a 12-bit 1 GS/s pipelined TI-SAR ADC [22], as shown in Figure 10. The bias circuit provides the gate voltages of M1(($\mathit{n}-1$)M1) and M2(($\mathit{n}-1$)M2) with a supply voltage of 1.8 V. Moreover, since the input swing of the ADC is 1 V, the output stage of the RVB is required to provide a stable 1 V reference voltage with a 1.2 V supply voltage. By separating the supply voltages of the bias circuit and the output stage, the power consumption of Figure 10 is reduced to only 3.7 mW.

It is worth noting that ${\mathit{I}}_{\mathrm{B}}$ in Figure 10 is equivalent to M5 in Figure 9a. As a result, the negative feedback networks of the bias circuits in the two RVBs are identical. In fact, this type of RVB circuit structure still has certain drawbacks. Firstly, a branch consisting of ${\mathit{I}}_{\mathrm{B}}$ (M5), M3, and M4 is added to generate a DC bias voltage for M2. However, M3 and M4 are equal to M1 and M2, but ${\mathit{I}}_{\mathrm{B}}$ is independent of ${\mathit{V}}_{\mathrm{REF}}$. A large voltage difference between the source terminals of M4 and M2 will decrease the matching performance of the two branches in the bias circuit. Taking Figure 10 as an example, the two branches are greatly matched only if the voltage drop of ${\mathit{I}}_{\mathrm{B}}$ is 0.6 V. Secondly, ($\mathit{n}-1$)M1 and ($\mathit{n}-1$)M2 are supposed to have comparable impacts on ${\mathit{V}}_{\mathrm{OUT}}$, but in the two proposed RVBs, the small signal feedback paths of the gate voltage of ($\mathit{n}-1$)M2 are more complex than those of ($\mathit{n}-1$)M1. Finally, ($\mathit{n}-1$)M2 are directly connected to the supply voltage, and the fluctuations of the supply voltage would reduce the stability of the ${\mathit{V}}_{\mathrm{OUT}}$. A deteriorated PSRR of the RVB leads to a lower signal-to-noise ratio (SNR) and fewer effective number of bits (ENOB) of the corresponding high-precision ADCs.

3. The Proposed RVB

3.1. Circuit Architecture

In Figure 11, the current-driven proposed RVB generates different ${\mathit{V}}_{\mathrm{REF}}$ by adjusting the input current $\mathit{I}$ dynamically (${\mathit{V}}_{\mathrm{REF}}$ = $\mathit{I}$$\mathit{R}$). $\mathit{I}$ not only determines the output voltage of this RVB but also generates the bias voltages for M4. The current mirror transistors in output stage are ($\mathit{n}-1$)× those in the loop. Considering the large capacitors of high-precision MDACs, it is worth noting that the driving current of the output stage circuit is amplified by a factor of $\mathit{n}-1$. ${\mathit{C}}_1$ is used to minimize high-frequency noise at the output stage, which is beneficial to the generation of an accurate reference voltage. In the output stage, the amplifier not only forms a negative feedback loop with M5, but also constitutes the other negative feedback loop with M4 by ${\mathit{C}}_2$. Compared with the Class-AB type RVBs proposed by [21,22], the RVB in Figure 11 exhibits superior matching performance due to the equivalent source voltages of M2 and M4. ($\mathit{n}-1$)M3 is used to mitigate the impact of supply voltage fluctuations on the output voltage.

3.2. Loop Stability

The loop stability of the proposed RVB needs to be analyzed and verified due to the two additional feedback loops provided by ${\mathit{C}}_2$. Figure 12 can be obtained by breaking the loop at the input of the amplifier, and the amplifier is Norton-equivalent to a parallel combination of a current source and an output resistor. The equivalent impedance within the dashed box can be written as

$$Z=\left[R+{\displaystyle \frac{r_{\mathrm{o}1}+r_{\mathrm{o}2}(1+g{m}_1{r}_{\mathrm{o}1})}{1+g{m}_2{r}_{\mathrm{o}2}(1+g{m}_1{r}_{\mathrm{o}1})}}\right]//{\displaystyle \frac{1}{s{C}_1}}.$$

(8)

${\mathit{V}}_{\mathrm{A}}$ can be described by

$$\begin{array}{cc}\hfill v_{\mathrm{a}}& =I_{\mathrm{A}}\left[({\displaystyle \frac{1}{s{C}_2}}+Z)//R_{\mathrm{O}}\right]\hfill \\ \hfill & =(v_{\mathrm{IP}}-v_{\mathrm{IN}})G{M}_{\mathrm{A}}\left[({\displaystyle \frac{1}{s{C}_2}}+Z)//R_{\mathrm{O}}\right],\hfill \end{array}$$

(9)

where ${\mathit{v}}_{\mathrm{IP}}$ and ${\mathit{v}}_{\mathrm{IN}}$ are the equivalent differential inputs after breaking the loop. ${\mathit{GM}}_{\mathrm{A}}$ is the equivalent transconductance of the simplified operational amplifier. Furthermore, the differential feedback voltages can be obtained as follows:

$$\begin{array}{cc}\hfill v_{\mathrm{fp}}& =v_{\mathrm{A}}{\displaystyle \frac{Z}{\frac{1}{s{C}_2}+Z}}{\displaystyle \frac{R}{R+\frac{r_{\mathrm{o}1}+r_{\mathrm{o}2}(1+g{m}_1{r}_{\mathrm{o}1})}{1+g{m}_2{r}_{\mathrm{o}2}(1+g{m}_1{r}_{\mathrm{o}1})}}},\hfill \\ \hfill v_{\mathrm{fn}}& =v_{\mathrm{A}}({\displaystyle \frac{Z}{\frac{1}{s{C}_2}+Z}}{\displaystyle \frac{r_{\mathrm{o}4}}{\frac{1}{g{m}_3}//r_{\mathrm{o}3}+r_{\mathrm{o}4}}}g{m}_4+g{m}_5)\left[{\displaystyle \frac{\frac{1}{g{m}_3}//r_{\mathrm{o}3}+r_{\mathrm{o}4}}{1+g{m}_4{r}_{\mathrm{o}4}}}//({\displaystyle \frac{1}{g{m}_5}}//r_{\mathrm{o}5})\right].\hfill \end{array}$$

(10)

Considering (1/$\mathit{gm}$) << ${\mathit{r}}_{\mathrm{o}}$, 1/${\mathit{gm}}_1$ (${\mathit{r}}_{\mathrm{O}1}$) = 1/${\mathit{gm}}_3$ (${\mathit{r}}_{\mathrm{O}3}$) and 1/${\mathit{gm}}_2$ (${\mathit{r}}_{\mathrm{O}2}$) = 1/${\mathit{gm}}_4$ (${\mathit{r}}_{\mathrm{O}4}$), the loop gain can be calculated as

$$\begin{array}{cc}\hfill {\displaystyle \frac{v_{\mathrm{fp}}-v_{\mathrm{fn}}}{v_{\mathrm{ip}}-v_{\mathrm{in}}}}& =-G{M}_{\mathrm{A}}{R}_{\mathrm{O}}{\displaystyle \frac{g{m}_5}{g{m}_4+g{m}_5}}F\left(s\right)\hfill \\ \hfill F\left(s\right)& ={\displaystyle \frac{-s^2\frac{g{m}_4+g{m}_5}{g{m}_5}(\frac{1}{g{m}_4}+R)R{C}_1{C}_2+s\left[(\frac{1}{g{m}_4}+R)C_1+\frac{g{m}_4+g{m}_5}{g{m}_{4}g{m}_5}{C}_2\right]+1}{s^2{R}_{\mathrm{O}}(\frac{1}{g{m}_4}+R)C_1{C}_2+s\left[(R_{\mathrm{O}}+\frac{1}{g{m}_4}+R)C_2+(\frac{1}{g{m}_4}+R)C_1\right]+1}}.\hfill \end{array}$$

(11)

In (11), $\mathit{F}$($\mathit{s}$) represents the complex frequency-domain term, which determines the frequency response of the loop. It can be seen from the denominator and numerator of $\mathit{F}$($\mathit{s}$) that the loop contributes two poles and two zeros. In general, a stable RVB requires the output resistance (${\mathit{R}}_{\mathrm{O}}$) of the high-gain cascode amplifier to realize ${\mathit{R}}_{\mathrm{O}}$ = ${{\mathit{gmr}}_{\mathrm{O}}}^2$, which indicates that ${\mathit{R}}_{\mathrm{O}}$ + 1/${\mathit{gm}}_2$ + $\mathit{R}$ ≈ ${\mathit{R}}_{\mathrm{O}}$ (${\mathit{R}}_{\mathrm{O}}$ >> 1/${\mathit{gm}}_2$ ≈ $\mathit{R}$). As a result, the denominator of $\mathit{F}$($\mathit{s}$) can be rewritten as

$$(s+{\displaystyle \frac{1}{{\omega }_{p1}}})(s+{\displaystyle \frac{1}{{\omega }_{p2}}})=(s+{\displaystyle \frac{1}{R_{\mathrm{O}}{C}_2}})\left[s+{\displaystyle \frac{1}{(\frac{1}{g{m}_4}+R)C_1}}\right].$$

(12)

As calculated in (12), the dominant pole ${\omega }_{\mathrm{p}1}$ is determined by the output resistance of the amplifier (${\mathit{R}}_{\mathrm{O}}$) and the gate-to-gate capacitor (${\mathit{C}}_2$). ${\mathit{R}}_{\mathrm{O}}$ and 1/${\mathit{gm}}_4$ are considered as around 0.1 GΩ and 0.1 kΩ. ${\mathit{C}}_1$, ${\mathit{C}}_2$, and $\mathit{R}$ are set to 10 pF, 30 pF, and 10 kΩ, respectively. The frequency of ${\omega }_{\mathrm{p}1}$ can be estimated at kilohertz. ${\omega }_{\mathrm{p}2}$ and two zeros are located in the high-frequency region around the gigahertz level according to (12) and (11).

The simulation results in Figure 13 present the magnitude and phase plot of the loop gain. As expected, the position of the dominant pole is around 0.3 kHz, and the loop approximates a single-pole system in the frequency range of 100 MHz. In addition, the sufficient phase margin is significant for the stability of the loop, and it is fortunate that the phase shift is only almost 90° within the gain crossover frequency.

4. Simulation Results

4.1. Driving Capability

The driving current of the output stage under the error voltage can intuitively reflect the driving capability and dynamic response speed of RVBs in pipelined ADCs. As can be seen from Figure 14a, ${\mathit{V}}_{\mathrm{REF}}$ is set to 1.4 V, and the output port of the proposed RVB is connected to a 1.4 V + $\Delta V$ DC voltage source. The magnitude of $\Delta I$ reflects the driving capability of the proposed RVB. To ensure that the proposed RVB drives the DAC array steadily under different manufacturing variations, the simulation results have been obtained under the following PVT process corners: Typical (TT), Slow (SS), Fast (FF), Slow-NMOS-Fast-PMOS (SNFP), and Fast-NMOS-Slow-PMOS (FNSP). Class-AB type milliampere-level $\Delta I$ is observed, which suggests that the proposed RVB is able to deal with both positive and negative $\Delta V$ evenly. Figure 14b shows 1000-run process and mismatch Monte Carlo (MC) results, which are employed to obtain the mean value ($\mu$) and the standard deviation ($\sigma$). Although $\sigma$ increases with the rise in $\Delta V$, the proposed RVB still behaves with high robustness during $\Delta V$ variation.

The output is observed by sweeping the load current source with a wide variation range in PVT corners simulation (Figure 15a) and MC simulation (Figure 15b). The output voltage error is expressed as: ${\mathit{V}}_{\mathrm{O},\mathrm{ERROR}}$ = (${\mathit{V}}_{\mathrm{O}}-1.4$)/1.4. In the output stage of Figure 11, ($\mathit{n}-1$)M4 and ($\mathit{n}-1$)M5 turn off when ${\mathit{I}}_{\mathrm{LOAD}}$ reaches ∼−30 mA and ∼18 mA, respectively. However, due to the Class-AB characteristics of the proposed RVB, ${\mathit{V}}_{\mathrm{O},\mathrm{ERROR}}$ does not increase abruptly after ($\mathit{n}-1$)M4 and ($\mathit{n}-1$)M5 turning off. Moreover, even the worst corner (FF process corner) has only 7.8% and −8.5% of ${\mathit{V}}_{\mathrm{O},\mathrm{ERROR}}$ when the ${\mathit{I}}_{\mathrm{LOAD}}$ reaches −10 mA and 10 mA as depicted in Figure 15a. Figure 15b still demonstrates the great robustness of the proposed RVB and smaller $\sigma$ in the charging process.

4.2. Transient Response

The proposed RVB is required to restore the voltage of sampling capacitors from the input voltage to the reference voltage accurately within an ultra-short time in high-speed pipelined ADCs. For evaluating the reference voltage settling performance of the proposed RVB in pipelined ADCs, the simulated circuit of transient response and the timing diagram are presented in Figure 16a. The sampling capacitance and the reference voltage are set to 9 pF and 1.4 V, respectively. $\Delta V$ is the voltage difference between the sampled input voltage (${\mathit{V}}_{\mathrm{S}}$($\mathit{t}$ = 0)) and 1.4 V, which is required to be overcome by the proposed RVB at $\mathit{t}$ = 0 to 2 ns. The simulation results in the TT process corner are illustrated in Figure 16b; the larger the $\Delta V$, the greater the difficulty in ${\mathit{V}}_{\mathrm{REF}}$ settling, and the longer the settling time. Due to the Class-AB characteristic of the proposed RVB, it is clear that $\Delta V$ (−0.4 V to 0.4 V) is settled evenly and effectively within 1 ns. The details in the dotted box are magnified. Despite the impact of non-ideal factors (e.g., parasitic capacitance) on overshoot, the small signal settling behavior broadly follows first-order RC settling (as shown in Figure 4).

According to Figure 16, in five process corners, Figure 17 shows the required settling times of the proposed RVB when the final settling error is constrained within 1 $\mathit{LSB}$ ($\mathit{LSB}$ is set to ${\mathit{V}}_{\mathrm{REF}}$/2¹⁰). In Figure 17a, it can be clearly observed that the proposed RVB buffers the desired reference voltage ($|{\mathit{V}}_{\mathrm{S}}-{\mathit{V}}_{\mathrm{REF}}| \le \mathit{LSB}$) within 0.68 ns (SS process corner) under the condition of $\Delta V$ (−0.4 V to 0.4 V). For a pipelined ADC, the settling time of the reference should not exceed half of the conversion time. In other words, the proposed RVB is prospective to be employed in the pipelined ADC with the precision of 10-bit and the speed of 735 MS/s. Figure 17b presents the expected $\mu$ and small $\sigma$ of settling time, which indicates the stability of the proposed RVB in high-speed and high-precision pipelined ADC applications.

4.3. Power Supply and Temperature Sensitivities

PSRR quantifies a circuit’s ability to suppress power supply fluctuations, which is a core indicator for analog circuit design. As illustrated in

Table 1. PSRR performance at different frequencies.

	TT	SS	FF	SNFP	FNSP	1000-Run MC ($\mathit{\mu }$)	1000-Run MC ($\mathit{\sigma }$)
PSRR@1 Hz (dB)	128.9	128.86	128.26	129.47	128.37	123.3	5.13
PSRR@1 kHz (dB)	107.25	107.46	108.59	108.06	106.45	99.57	2.61
PSRR@1 MHz (dB)	59.6	60.01	59.19	60.2	59.05	59.69	0.23

, PSRR is simulated as a function of frequency, and obviously, PSRR is stable in different process corners. The robustness of the proposed RVB is verified again by 1000-run MC simulation results of PSRR. Owing to the ($\mathit{n}-1$)M3 displayed in Figure 11, the gain of the power supply noise is attenuated. In the different process corners, the PSRR of the proposed RVB is equal to ∼129 dB at 1 Hz, ∼107 dB at 1 kHz, and ∼60 dB at 1 MHz. Therefore, it can be expected that the proposed RVB has sufficient attenuation for the injected noise from the power supply voltage.

The input voltage of the proposed RVB is still set to 1.4 V ($\mathit{I}$$\mathit{R}$ = 1.4 V in Figure 11), and the temperature sensitivity of its output voltage (${\mathit{V}}_{\mathrm{O},\mathrm{RVB}}$) is displayed in Figure 18. The temperature coefficient (TC) of five process corners can be obtained by Figure 18a: TC_TT ≈ TC_SS ≈ TC_FF ≈ TC_SF ≈ TC_FS ≈ 363 ppm/°C. High temperature sensitivity of R results in the large TC of ${\mathit{V}}_{\mathrm{O},\mathrm{RVB}}$. However, as shown in Figure 18b, the Monte Carlo simulation results prove that the proposed RVB itself is stable and robust.

5. Conclusions

In this work, a novel Class-AB RVB is proposed. The theoretical derivation demonstrates the loop stability of the proposed RVB. The simulation results indicate that the proposed RVB achieves not only wonderful driving capability but also excellent settling accuracy and speed. Moreover, high PSRR demonstrates that the output voltage of the proposed RVB is insensitive to the variations in the supply voltage.

Table 2. Performance summary and comparison.

	This Work	ASID 2014 [16]	MIXDES 2014 [17]	TCAS-II 2013 [32]	JSSC 2023 [22]	JSSC 2019 [21]	ICSICT 2024 [23]	APCCAS 2020 [30]
Techn. (nm)	180	180	180	65	28	65	180	28
${\mathit{V}}_{\mathrm{DD}}$ (V)	1.8	1.8	1.8	1.2	1.2	2.5	5	1
${\mathit{V}}_{\mathrm{REF}}$ (V)	1.4	0.5	0.5	N/A	1	1.2	2.5	0.75
RVB power (mW)	4.5	N/A	0.12	16.8	3.7	N/A	0.056	2.4
Settling time (ns)	0.68	1.549	19.3	N/A	0.05	N/A	1810	0.115
Load Cap. (pF)	9	N/A	3.7	4	1	2	0–20	2
PSRR (dB)	128.9 (1 Hz)	107.3 (1 Hz)	72	N/A	∼43 (3 GHz)	N/A	N/A	N/A

summarizes the performance of the proposed RVB. In comparison with the previous RVBs, although the power consumption of the proposed RVB increases inevitably owing to the replica-driving output stage with a large current, it is still only 4.5 mW. Fortunately, the proposed RVB achieves not only higher PSRR but also more outstanding driving capability for large capacitive loads. These properties indicate that the proposed RVB is feasible to be applied in high-speed and high-precision pipelined ADCs.