Bulk-Driven CMOS Differential Stages for Ultra-Low-Voltage Ultra-Low-Power Operational Transconductance Amplifiers: A Comparative Analysis

Abstract

Energy-efficient integrated circuits require scaled-down supply voltages, posing challenges for analog design, particularly for operational transconductance amplifiers (OTAs) essential in high-accuracy CMOS feedback systems. Below 1 V, gate-driven OTAs are limited in common-mode input range and minimum supply voltage. This work investigates CMOS Bulk-Driven (BD) sub-threshold techniques as an efficient alternative for ultra-low voltage (ULV) and ultra-low power (ULP) designs. Although BD overcomes MOS threshold voltage limitations, historical challenges like lower transconductance, latch-up, and layout complexity hindered its use. Recent advancements in CMOS processes and the need for ULP solutions have revived industrial interest in BD. Through theoretical analysis and computer simulations, we explore BD topologies for ULP OTA input stages, classifying them as tailed/tail-less and class A/AB, evaluating their effectiveness for robust analog design, while offering valuable insights for circuit designers.

1. Introduction

The relentless pursuit of energy efficiency forces integrated circuits (ICs) to operate with ever-decreasing supply voltages. However, this trend poses a significant challenge for analog design, particularly for OTAs, which are the workhorse circuits in many CMOS applications. Indeed, traditional gate-driven OTAs, often relying on the ubiquitous Long-Tailed Source-Coupled Pair (LTSCP) input stage, face limitations in maintaining a full-scale input range and operating effectively with low supply voltages due to inherent design constraints, especially concerning common-mode input range [1].

Low-frequency ULV and ULP analog circuits find usage in many applications, such as wearable devices, Internet of Things (IoT) sensors, wireless sensor networks, medical implantable devices, remote sensing, energy harvested systems, automotive, etc. [2,3,4,5,6,7]. In this framework, several design techniques are available in standard CMOS, including weak inversion operation [8,9,10], inverter-based [11,12,13,14] and fully digital approaches [15,16,17,18]. Furthermore, research extends to non-silicon technologies like carbon nanotube field-effect transistors (CNTFETs) [19,20].

An alternative to the CMOS gate-driven design approach is the body-driven, or bulk-driven, BD, technique which leverages the dependence of the drain current on the bulk-source voltage, avoiding threshold voltage, V_T, limitations [21,22,23,24,25]. While digital design has long utilized BD for purposes like leakage current reduction and compensation of V_T variations [26,27,28,29,30,31,32,33], its adoption in analog design remains limited. This is partly due to the persisting perception of the body effect as the origin of potential second-order negative effects in analog circuits like latch-up. Moreover, despite early works demonstrating the viability of the BD approach for analog applications thirty years ago [21], several drawbacks have limited its adoption within the constraints of industry standards, including

(a)

Lower transconductance, i.e., the bulk transconductance is lower than the gate counterpart. This translates to lower gain, lower gain-bandwidth product (GBW) and higher noise for a given standby current.

(b)

Access to bulk terminals. Both bulks of p- and n-MOS devices need to be accessible for full BD exploitation. This is not possible in early single-well technology.

(c)

Poor matching and large silicon area. Related to point (b), devices laid out in different wells can have poor matching characteristics and require non-minimum area.

(d)

Maintaining a safe bulk-source biasing voltage. This is to avoid the turn on of the bulk-source p-n junction.

(e)

Poor concomitant BD and subthreshold operation MOS transistor modeling [34]. Performance predictions through simulations may not be accurate under these circumstances.

Despite these drawbacks, the authors believe that CMOS processes and modeling improvements, together with the advance of the design art and the growing demand for ultra-low-voltage, high-swing, low-frequency solutions, make BD solutions nowadays ready for extensive use and general acceptance. In fact, nanoscale technologies make the impact of the analog area requirement in a mixed-signal IC less severe. The common availability of twin-tub CMOS technologies allows both p- and n-MOS bulk terminals to be accessible. Supply voltages lower than 0.5 V make it quite easy to avoid the bulk-source junction to sustain appreciable current and avoid latch up.

To bridge the gap between theoretical research and practical application, demonstrating the viability of BD techniques for robust ULV-ULP operation and high-performance analog circuits [35], this paper investigates BD solutions amenable for the implementation of operational transconductance amplifier’s (OTA) input stages. This first stage plays a critical role in defining the OTA performance as it significantly impacts parameters like common-mode input range, GBW, CMRR (Common-Mode Rejection Ratio), PSRR (Power Supply Rejection Ratio), offset, and noise. Subsequent gain stages, crucial for DC gain, current drive, and output swing, are typically implemented using conventional gate-driven techniques (e.g., common-source configurations), and, for this reason, will not be discussed in this paper. Specifically, here, we analyze BD input stage solutions exploiting MOS transistors in subthreshold regime [10,24,36,37,38,39,40], amenable for nanoampere-range quiescent current operation, particularly relevant for low-frequency ULV and ULP, battery-operated/battery-less applications, where minimizing power consumption is paramount.

The structure of the paper is the following. Section II presents the definition and some background by discussing basic topologies and their working principle. Section III explores improved circuits, deriving the differential transconductance key parameter for each topology. Two categories of topologies are identified: tailed and tail-less. These are further classified based on their operation as Class A or Class AB. Section IV validates the analysis through computer simulations, comparing the performance of different implementations in a reference common CMOS process. Section V concludes the paper by summarizing the findings and outlining future research directions.

2. Definitions and Background

2.1. Definitions

While utilizing the MOS gate as an input terminal for ULV ICs is constrained by the threshold voltage, operating transistors in the subthreshold region can partially mitigate this issue. However, fully overcoming this limitation requires exploiting the MOS bulk as the input terminal, albeit at the cost of reduced transconductance and input impedance, ultimately impacting gain, bandwidth, and noise performance. Eventually, optimal performance for ULV and ULP circuits is achieved by combining bulk-driven and subthreshold-biasing (weak inversion) techniques [41].

The drain current, i_D, of an n-channel MOS transistor operated in weak inversion depends on v_GS, v_BS and v_DS and can be expressed as

$$i_D={\displaystyle \frac{W}{L}}{I}_S{e}^{q{\displaystyle \frac{v_{GS}-V_{TH}}{nkT}}}\left(1-e^{-q{\displaystyle \frac{v_{DS}}{kT}}}\right)$$

(1)

where W/L is the aspect ratio, V_TH is the gate to source threshold voltage, I_S is the characteristic current given by $I_S=2n\mu C_{OX}{\left(kT/q\right)}^2$, T is the absolute temperature, k is the Boltzmann constant, q is the charge of the electron, μ is the electron mobility, C_OX is the oxide capacitance per unit area, and n is the slope factor with 1.1 < n < 1.5. In addition, the threshold voltage depends on the bulk-source voltage through the body effect, with γ the body effect coefficient and ${\varphi }_F$ the Fermi potential:

$$V_{TH}=V_{TO}+\gamma \left(\sqrt{2{\varphi }_F-v_{BS}}-\sqrt{2{\varphi }_F}\right)$$

(2)

If V_DS ≥ 3 kT/q, then the transistor will be in the saturation of the weak inversion region and the i_D dependence on v_DS can be neglected in (1). In the following designs, we will choose a minimum V_DS of 100 mV for all the transistors.

The gate transconductance, g_m, is the derivative of i_D with respect to v_GS at the operating point, hence we obtain

$$g_m=q{\displaystyle \frac{I_D}{nkT}}$$

(3)

whereas the bulk transconductance, g_mb, defined as the derivative of i_D with respect to v_BS at the operating point is

$$g_{mb}=\left(n-1\right)q{\displaystyle \frac{I_D}{nkT}}=\left(n-1\right)g_m$$

(4)

The relatively low ratio of g_mb to g_m, often between 0.1 and 0.4, highlights the importance of employing suitable techniques to boost the effective bulk transconductance when exploiting the MOSFET body as input terminal. This is particularly important for noise considerations. Indeed, the equivalent input noise voltage spectral density, S_v,in(f), in V²/Hz, for a body-driven MOSFET can be approximated as

$$S_{v,in}(f)\approx {\displaystyle \frac{4kT\gamma g_m}{g_{mb}^2}}+{\left({\displaystyle \frac{g_m}{g_{mb}}}\right)}^2{\displaystyle \frac{K_F}{WL{C}_{ox}f}}+4kT{R}_B={\displaystyle \frac{1}{{\left(n-1\right)}^2}}\left({\displaystyle \frac{4kT\gamma }{g_m}}+{\displaystyle \frac{K_F}{WL{C}_{ox}f}}\right)+4kT{R}_B$$

(5)

where k is the Boltzmann constant, T the absolute temperature (in Kelvin), γ the channel thermal noise coefficient (e.g., 2/3 for long channels, higher for short channels), K_F the flicker noise coefficient and R_B the equivalent series resistance of the body terminal. Both the input-referred thermal noise, scaled by $1/g_{mb}^2$, and flicker noise, scaled by (g_m/g_mb)², tend to be significantly larger than in a comparable gate-driven device. The noise from the body resistance (R_B) also adds directly, but it can usually be neglected.

2.2. Basic BD Differential Stage Topologies

This work categorizes the Bulk-Driven OTAs from the literature into two different classes: Tailed and Tail-less solutions. The schematic diagrams of two simple examples are shown in Figure 1, together with the associated current biasing strategy. Importantly, both circuits exhibit a rail-to-rail input common-mode range (0–V_DD). The low supply voltage allowed (V_DD ≤ 400 mV), effectively prevents significant forward biasing of the parasitic bulk-source junction, thereby minimizing bulk current. Finally, both circuits employ an active load, implemented as a current mirror (M₃–M₄), to convert the differential input voltage into a single-ended output voltage at the high-impedance output terminal.

The first solution shown in Figure 1a utilizes transistors M₁-M₂, forming the BD differential pair and M₅ as tail current source. Hence, it follows the classical approach, used in gate-driven topologies, with the tail current source that accurately sets the quiescent current of the input stage. Thanks to this, a high CMRR is achieved by reducing the effects of common mode disturbances on the output voltage, but it comes at the expense of the minimum supply voltage that must accommodate 2 V_DS + V_GS, as can be easily found by following the path from V_DD to ground through M₃ (that requires one V_GS) and M₁ and M₅ (that require one V_DS each). An additional biasing voltage V_G is also needed and a discussion on its influence on g_mb is found in [34]. Note also that this approach leads to a true differential pair resulting in an equal and opposite current change in the pair (i_D1 and i_D2) even when single input (e.g., v_in+) is applied while the other input is kept at a constant voltage. Finally, the fact that the maximum sinking and sourcing output current is constant and limited to [(W/L)₅/(W/L)₆]I_B dictates that only class A operation is possible. Regarding the small signal differential transconductance, G_md, and common-mode transconductance, G_mc, we have

$$G_{md}=g_{mb1,2}$$

(6)

$$G_{mc}=\epsilon {\displaystyle \frac{g_{mb1,2}}{1+2\left(g_{m1,2}+g_{mb1,2}\right)r_{d5}}}$$

(7)

where g_mb1 = g_mb2 = g_mb1,2 was considered, r_d5 is the output resistance of M₅ and a current transfer 1:(1 + ε) with ε << 1 is assumed in the current mirror from M₃ to M₄.

Due to supply voltage scaling with technology advancements, BD OTAs are increasingly adopting a tail-less architecture, saving V_DS headroom and advantageously enabling class-AB operation. Inherently, however, this approach leads to pseudo-differential operation, which results in a dominant change in one current of the pair (e.g., i_D1) when a single input (e.g., v_in+) is applied. It must be noted that in conventional gate-driven circuits, the pseudo-differential approach also leads to an ill-defined standby current that depends on the input common-mode level and causes in turn low CMRR. To tackle this problem, techniques like common mode feedback (CMFB), and common mode feedforward (CMFF) can be utilized [41,42,43,44,45,46]. In BD pseudo-differential OTAs, in contrast, this last issue is overcome, as quite good standby current control is achieved. Consider for this purpose the tail-less pseudo-differential BD OTA in Figure 1b. The input BD transistors M₁–M₂ are biased from their gate via voltage V_B that is obtained from diode-connected transistor M₅ biased through I_B. If the bulk terminal of M₅ is kept to the common mode voltage, V_CM, of v_in+ and v_in−, then the common-mode current of the pair is accurately set by the relation: I_D1,2 = I_B (W/L)_1,2/(W/L)₅. The supply voltage in this case must accommodate V_DS + V_GS as can be easily found by following the path from V_DD to ground through M₃ and M₁. The expressions of G_md and G_mc are

$$G_{md}=g_{mb1,2}$$

(8)

$$G_{mc}=\epsilon g_{mb1,2}$$

(9)

It is seen from (6)–(9) that while the differential transconductances are the same, the common-mode transconductance is adversely higher in (9) due to the absence of the tail current generator.

The equivalent input noise voltage (S_v,in) represents all noise sources within the transconductor referred back to its input (the body terminal). It is calculated by dividing the total output noise current spectral density (S_i,out) by the square of G_md and adding any noise sources directly present at the input.

The topologies in Figure 1 are simple examples, more efficient Tailed and Tail-less solutions are discussed below.

3. High Performance BD Input Stages

In this section, we will discuss three different types of Bulk-Driven input stages. These include tailed input stages, and within the tail-less category, we will distinguish between class-A and class-AB topologies. It is worth noting that unless otherwise specified, the transistor bulk terminals are connected to V_DD (for p-channel MOSFETs) and to V_SS (for n-channel MOSFETs).

3.1. Tailed Differential Stages

In the category of tailed BD differential stages, we have selected the three exemplifying topologies shown in Figure 2a–c.

Figure 2a depicts the BD OTA proposed in [47]. It utilizes M₁ and M₂ as the input transistors and M₅ as the tail current source. The active load includes the constant current sources M₆ and M₇, and the self-cascode current mirror made up of composite transistors M_3a–M_3b and M_4a–M_4b. This latter (composite) arrangement provides a high output-impedance cascode structure without the need for additional biasing elements. Here, the important requirement is that V_GS3b,4b must be lower than V_GS3a,4a by at least 3V_T to preserve saturation of M_3a and M_4a and this is obtained via larger aspect ratios for M_3b,4b compared to M_3a,4a. The minimum supply voltage is 3V_DS, as can be seen by following the path from V_DD to V_SS through M₅, M₂, and M_3a. The full differential transconductance is obtained thanks to the current mirror and is thus equal to g_mb1,2.

Figure 2b shows an improved version, originally proposed in [48], that utilizes M_1a and M_2a as cross-connected active loads degenerating the sources of M_1b and M_2b, respectively. The solution was then implemented in [49] utilizing the self-cascode current mirror M_3a–M_4b. The minimum supply voltage is 4V_DS. Due to the positive feedback provided, the degeneration boosts the overall transconductance. We can derive the following equation for the equivalent differential transconductance, G_md, using the small-signal equivalent model depicted in Figure 3:

$$G_{md}=(g_{m1\mathrm{a},2\mathrm{a}}-{\displaystyle \frac{1}{r_{d1\mathrm{a},2\mathrm{a}}}})\alpha -g_{mb1\mathrm{a},2\mathrm{a}}\approx \alpha g_{m1\mathrm{a},2\mathrm{a}}\approx {\displaystyle \frac{2g_{mb1,2}}{1-B}}$$

(10)

in which we set g_mb1,2 = g_mb1a,2a = g_mb1b,2b and

$$\alpha ={\displaystyle \frac{A}{1-B}}$$

(11)

where denoting as R the resistance seen at drain of M_1b,2b, A and B are given by

$$A={\displaystyle \frac{g_{mb1\mathrm{a},2\mathrm{a}}+\frac{g_{mb1\mathrm{b},2\mathrm{b}}}{1+\frac{R}{r_{d1\mathrm{b},2\mathrm{b}}}}}{\frac{g_{m1\mathrm{b},2\mathrm{b}}+g_{mb1\mathrm{b},2\mathrm{b}}+\frac{1}{r_{d1\mathrm{b},2\mathrm{b}}}}{1+\frac{R}{r_{d1\mathrm{b},2\mathrm{b}}}}+\frac{1}{r_{d1\mathrm{a},2\mathrm{a}}}}}\approx {\displaystyle \frac{2g_{mb1\mathrm{a},2\mathrm{a}}}{g_{m1\mathrm{b},2\mathrm{b}}}}$$

(12)

$$B={\displaystyle \frac{g_{m1\mathrm{a},2\mathrm{a}}}{\frac{g_{m1\mathrm{b},2\mathrm{b}}+g_{mb1\mathrm{b},2\mathrm{b}}+\frac{1}{r_{d1\mathrm{b},2\mathrm{b}}}}{1+\frac{R}{r_{d1\mathrm{b},2\mathrm{b}}}}+\frac{1}{r_{d1\mathrm{a},2\mathrm{a}}}}}$$

(13)

Figure 2. Examples of tailed BD differential stages: (a) [47], (b) [49], and (c) [50].

Figure 2. Examples of tailed BD differential stages: (a) [47], (b) [49], and (c) [50].

It is noteworthy that the positive feedback of the solution, responsible for 1 − B at the denominator in (11), may induce instability for B approaching 1. Therefore, B < 1 must be ensured. Moreover, the inclusion of MOSFET output resistance, r_d, improves the accuracy of this equation compared to that given in [48]. This is critical in short-channel technologies, where channel length modulation increases, making g_mb no longer negligible relative to 1/r_d while g_m greater than 1/r_d is still reasonable. Furthermore, the varying drain-source voltages necessitate the retention of distinct r_d values for M_1a,2a and M_1b,2b. Finally, for the approximation of (10), we assume g_m (and g_mb) are equal for M_1a,2a and M_1b,2b.

It is observed that (10) provides an improved transconductance compared to the original g_mb1,2 by approximately a factor of 2/(1 − B). In a well-designed circuit, 1−B can be set within the range of 0.1 to 0.3.

The last solution considered is the one proposed in [50] and illustrated in Figure 2c. It exploits the cross-connected transistors M_1b and M_2b derived from the two parallel BD pairs M_1a,1b, M_2a,2b with (W/L)_1a,2a = k (W/L)_1b,2b. The minimum supply voltage is 2 V_DS + V_GS1,2 that can equal 300 mV provided that V_GS1,2 = 100 mV. Observe that the tail current source is replaced by two flipped voltage followers (FVF) [51] implemented by M_1d–M_1b and M_2d–M_2b as variable tail current sources utilizing negative feedback and depending on the amplitude of input signals. Moreover, the cross-connection between the gates and drains of M_1b and M_2b increases the impedance at their drain terminals, which are in turn connected to the gates of M_1d and M_2d obtaining an equivalent transconductance boost, as given in (14), where parameters k, m and p, are the standby current ratios as illustrated in the same Figure 2c. Using k = 1, m = 1 and p = 0.25 we obtain a boosting factor of 5. Considering g_mb1a,1b = g_mb2a,2b = g_mb1,2 the overall differential transconductance is given as

$$G_{md}=2km\left(1+p\right)\left(1+k\right)g_{mb1,2}$$

(14)

3.2. Tail-Less Class-A Differential Stages

The second category of circuits studied in this review comprises class-A tail-less input stages. Four representative solutions have been selected and are illustrated in Figure 4a–d. Figure 4a, ref. [52], shows the simplest tail-less pseudo-differential input stage which exploits the bulk terminals of both p-channel (M₁–M₂) and n-channel (M₃–M₄) transistor couples. M₁ and M₂ are biased through V_B. Due to the fully differential output, the gate voltage of M₃ and M₄ is driven by a common-mode feedback voltage which also increases CMRR. The common-mode feedback circuit can be simply implemented using two large resistors connected between the gate and drain of M₃ and M₄, as shown in Figure 4d. More advanced solutions utilize an auxiliary error amplifier, with a specific implementation detailed in reference [52]. The differential transconductance (single-ended) is simply

$$G_{md}={\displaystyle \frac{g_{mb1,2}+g_{mb3,4}}{2}}$$

(15)

A simple topology that exploits local positive feedback offered by transistors M₇ and M₈ to boost the equivalent transconductance is shown in Figure 4b, ref. [53]. In this case, we obtain

$$G_{md}={\displaystyle \frac{g_{m4,6}{r}_{o1}}{1-\left(g_{m7,8}{r}_{o1}\right)}}{g}_{mb1,2}\approx {\displaystyle \frac{g_{m4,6}/g_{m3,5}}{1-\left(g_{m7,8}/g_{m3,5}\right)}}{g}_{mb1,2}$$

(16)

where $r_{o1}=r_{d1,2}\parallel r_{d3,5}\parallel r_{d7,8}\parallel {\displaystyle \frac{1}{g_{m3,5}}}\approx {\displaystyle \frac{1}{g_{m3,5}}}$.

To avoid G_md sign changes and stability problems, the ratio of g_m7,8/g_m3,5 should be kept below 1. This precaution is necessary because G_md ideally approaches infinity when g_m7,8 approaches g_m3,5, making the circuit highly sensitive to small variations.

Figure 4c shows a non-tailed BD stage in which the input voltage is applied to the four transistors M_1a,b and M_2a,b. Transistors M_4a,b are constant current sources and M_3a,b implement the current mirror for differential to single-ended conversion. An augmented transconductance is obtained by controlling the input transistors M_1a and M_1b both from their body and gate terminals [54]. For example, considering M_1a and M_2a, M_1a is driven from its bulk by v_in+ and also from its gate by a voltage approximately equal to −g_mb2a/g_m2a v_in− (simply consider that g_mb2a v_in− + g_m2av_gs = 0 at the drain of M_2a). Therefore, the equivalent transconductance of M_1a is 2g_mb1,2 like the overall equivalent differential transconductance of the circuit. Notably, this configuration achieves true differential operation, thereby surpassing the limitations of pseudo-differential approaches, thanks to its four input transistors.

The circuit in Figure 4d utilizes resistors R_A,B for common-mode feedback so that M₃ and M₄ conduct the same common-mode current of M₁ and M₂ [55]. Moreover, it exploits local positive feedback implemented by the cross connection of body and drain terminals of M₃ and M₄ which, together with the current mirror gain provided by M₃ to M₆ (M₄ to M₈) improves the equivalent transconductance as

$$G_{md}={\displaystyle \frac{g_{m6,8}{R}_{\mathrm{A},\mathrm{B}}\parallel r_{o1}}{1-g_{mb3,4}{R}_{\mathrm{A},\mathrm{B}}\parallel r_{o1}}}{g}_{mb1,2}$$

(17)

where $r_{o1}=r_{d1,2}\parallel r_{d3,4}$. This solution also ensures true differential operation, as explained in [55].

3.3. Tail-Less Class-AB Differential Stages

The preceding tail-less input stages operate in class A, i.e., their maximum output current is limited to the value of the standby current. This characteristic is also inherent to tailed topologies. However, the literature also presents tail-less implementations operating in class AB, capable of delivering output currents significantly exceeding their standby current. The following section explores three such circuits whose schematic diagrams are depicted in Figure 5a–c [56,57,58].

In Figure 5a two self-biasing transconductance cells (M_1a–M_4a and M_1b–M_4b) are used as BD tail-less input stages. Transistors M_5a,b are added in parallel to M_3a and M_3b, respectively, to increase controllability of the cells by reducing g_m3a,b and to avoid zero current condition. The second stage is made up of common source transistors M_6a,b (that are also body-driven to improve current driving capability) and cross-connected transistors M_7a,b that mirror the current in M_4a,b. The solution offers fully differential operation.

Due to the absence of tail current generators, to improve common-mode rejection the two transconductance cells must be designed symmetrically and well matched with each other to optimize common mode cancelation.

Assuming 1/r_d << g_m and g_m1a,b = g_m2a,b = g_m4a,b, the positive feedback of the self-biasing input cells leads to a high output impedance [56]. Indeed, the resistance seen at the output node of each transconductance cell, r_O1,O2, is expressed by

$$r_{O1,O2}\approx {\displaystyle \frac{1}{g_{m1\mathrm{a},\mathrm{b}}-g_{m3\mathrm{a},\mathrm{b}}}}$$

(18)

Since g_m3a,b < g_m1a,b, a positive and finite impedance is achieved. The value of this resistance is electrically controlled by g_m3a,b through voltage, V_B, at the gate of M_5a,5b. Assuming g_m6a = g_m6b the overall differential transconductance is given by

$$G_{md}\approx 2g_{m6}{r}_{O1,O2}{g}_{mb1,2}$$

(19)

In Figure 5b, the tail-less BD differential cell M₁-M₄ has its standby current set by V_B. The output common-mode voltage is set by diode-connected transistors M₉–M₁₀, which have zero DC current and thus exhibit very large small-signal resistance around the bias point, similar to R_A-B in Figure 4d [55]. These pseudo-resistors establish the common-mode voltage while minimizing the load effect at the output of the first stage. Although they may exhibit nonlinearity under large signal conditions, the output swing remains constrained, as the only node experiencing significant signal swing is the output, and the second stage M₅–M₈ provides high gain and differential to single conversion. The overall differential transconductance can be expressed as follows:

$$G_{md}={\displaystyle \frac{g_{m6,8}{r}_d}{1+g_{mb3,4}{r}_d}}{g}_{mb1,2}$$

(20)

where

$$r_d=r_{d1,2}\parallel r_{d3,4}\parallel r_{d9,10}$$

(21)

The last topology examined in this category shown in Figure 5c utilizes two matched transconductor cells, M_1a–M_4a and M_1b–M_4b, similar to those in Figure 5a with the only difference that M_4a,4b are diode-connected from body to drain (and not, as usual, from gate to the drain) [58]. The output resistance, r_o1,2, of these input cells is equal to

$$r_{o1,2}=r_{d2\mathrm{a},2\mathrm{b}}\parallel r_{d4\mathrm{a},4\mathrm{b}}\parallel \left({\displaystyle \frac{1}{g_{mb4\mathrm{a},4\mathrm{b}}}}\right)$$

(22)

A second transconductance stage, implemented by M₅–M₈, increases gain and also provides differential to single-ended conversion through BD unitary current mirror M₇–M₈. The overall differential transconductance is hence given as

$$G_{md}\approx 2g_{mb1,2}{g}_{m5,6}{r}_{o1,2}$$

(23)

The differential transconductance of all the input stages discussed is summarized for convenience in the second column of

Table 1. Summary of discussed solutions. Differential transconductance approximate equations, simulated values (obtained from simulation and from the approximated calculation), details of input transistors (aspect ratios, multiplicity, and type), standby currents, operating class, tailed/tail-less topology, and G_md/I_Q ratio.

Ref.	Differential Transconductance, Gmd		W/L of Input Transistors × Mult., Type	Standby Current, IQ [nA]	Class A/AB,	Gmd/IQ [V−1]
	Equation	Value [nA/V] @VCM = VDD/2 Simul. (Calc.)			Tailed(T)/ Tail-Less(TL)
[47]	$g_{mb1,2}$	44.5 (52.5)	1.9/0.18 × 2, pMOS	79	A, T	0.57
[49]	$\begin{array}{c}{\displaystyle \frac{2g_{mb1,2}}{1-B}},\\ \mathrm{where}\\ B={\displaystyle \frac{g_{m1\mathrm{a},2\mathrm{a}}}{\frac{g_{m1\mathrm{b},2\mathrm{b}}+g_{mb1\mathrm{b},2\mathrm{b}}+\frac{1}{r_{d1\mathrm{b},2\mathrm{b}}}}{1+\frac{R}{r_{d1\mathrm{b},2\mathrm{b}}}}+\frac{1}{r_{d1\mathrm{a},2\mathrm{a}}}}}\end{array}$	800 (1100)	40/0.18 × 2, pMOS and 2/0.18 × 2, pMOS	93	A, T	8.6
[50]	$2km\left(1+p\right)\left(1+k\right)g_{mb1,2}$, where k, m and p are current ratios in Figure 2c	394 (356)	60/2 × 4, pMOS	145	A, T	2.7
[52]	${\displaystyle \frac{g_{mb1,2}+g_{mb3,4}}{2}}$	74.6 (74.6)	3/1 × 2, nMOS and 9/1 × 2, pMOS	40	A, TL	1.9
[53]	${\displaystyle \frac{g_{m4,6}{r}_{o1}}{1-\left(g_{m7,8}{r}_{o1}\right)}}{g}_{mb1,2},$$\mathrm{where}{r}_{o1}=r_{d1,2}\parallel r_{d3,5}\parallel r_{d7,8}\parallel \left({\displaystyle \frac{1}{g_{m3,5}}}\right)$	2760 (2927)	7.5/0.18 × 2, pMOS	386	A, TL	7.2
[54]	$2g_{mb1}$	123 (132)	9/0.18 × 4, pMOS	82	A, TL	1.5
[55]	$\begin{array}{c}{\displaystyle \frac{g_{m6,8}{R}_{\mathrm{A},\mathrm{B}}\parallel r_{o1}}{1-g_{mb3,4}{R}_{\mathrm{A},\mathrm{B}}\parallel r_{o1}}}{g}_{mb1,2},\\ \mathrm{where}{r}_{o1}=r_{d1,2}\parallel r_{d3,4}\end{array}$	2420 (2500)	8/0.18 × 2, nMOS	1410	A, TL	1.7
[56]	$2{\displaystyle \frac{g_{m6}}{g_{m1}-g_{m3}}}{g}_{mb1,2}$	7550 (7700)	70/3 × 4, pMOS	1000	AB, TL	7.5
[57]	$\begin{array}{c}{\displaystyle \frac{g_{m6,8}{r}_d}{1+g_{mb3,4}{r}_d}}{g}_{mb1,2},\\ \mathrm{where}{r}_d=r_{d1,2}\parallel r_{d3,4}\parallel r_{d9,10}\end{array}$	4180 (4240)	0.6/3 × 2, nMOS	191	AB, TL	21.9
[58]	$2g_{mb1,2}{g}_{m5,6}{r}_{o1,2}$	2710 (3100)	7/2 × 4, pMOS	231	AB, TL	11.7

.

4. Comparison and Discussion

Previously discussed circuits were simulated with Cadence Spectre using the same 65 nm CMOS bulk technology from TSMC to obtain comparative performance parameters. For consistency, a supply voltage (V_DD) of 300 mV was used for all circuits, except for the circuit in Figure 2b [49], which required 400 mV. This ensured a MOS drain-source voltage of 100 mV at the operating point for all designs. The transistor dimensions are shown in the schematic diagrams, with labels adjacent to the corresponding transistors. The equivalent differential transconductance (G_md = i_out/v_d), common-mode transconductance (G_mcm = i_out/v_cm), and power-supply transconductance (G_mdd = i_out/v_dd) were evaluated using the configurations in Figure 6a, Figure 6b and Figure 6c, respectively.

In addition to the discussed G_md expressions, Table 1 shows the simulated G_md values (at V_CM = V_DD/2) and the corresponding calculated values. The latter were derived from approximate equations in Table 1 using the small-signal transconductances and output resistances obtained from the operating point simulation. As evident, there is a very good agreement between the simulated and calculated values, except for [49], which, however, provides a very accurate result if the compete Equations (10), (12) and (13) are used.

The third column of Table 1 provides the W/L, multiplicity factor, and channel type for the input BD transistors. The total standby current is presented in the fourth column, while the fifth column indicates the operating class and tail/tail-less topology. The G_md/I_Q ratio, displayed in the last column, facilitates a more effective comparison of G_md efficiency relative to current consumption across different solutions. Among the Class A topologies, those with positive feedback exhibit the highest G_md/I_Q ratios [49,53]. Local body-positive feedback in [55] appears less effective. Class AB solutions [57,58] are however the most efficient, with [57] achieving a G_md/I_Q of 21.9 V⁻¹, approximately twice that of [58] (11.7 V⁻¹).

In Figure 7a, Figure 8a, and Figure 9a, the short-circuit output current normalized to the total standby current is plotted as a function of the differential input voltage, for all configurations. V_CM = V_DD/2 was again set. The curves allow a graphical evaluation of the symmetrical behavior, current drive capability and linearity of the input stages.

In addition, circuit sensitivity to input common mode was assessed by plotting in Figure 7b, Figure 8b and Figure 9b the value of G_md/I_Q as a function of the DC CM input voltage, V_CM. Both plot types were obtained using the test bench in Figure 6a.

Results for the tailed configurations are presented in Figure 7. Figure 7a indicates that solutions [47,50] provide excellent current linearity which makes them well-suited for G_m-C filtering applications, where consistent transconductance is crucial for accurate filter response. Topology from [50] shows a steeper linear increase in normalized I_OUT compared to [47] as a result of the higher G_md and the highest current drive capability (80% of the tail current). Moreover, as can be seen from Figure 7b, ref. [50] provides almost ×3 G_md compared to [47] for the same current consumption. Both topologies are insensitive to input CM voltage value. Topology from [49], which is similar to [47] but uses positive feedback source degeneration, exhibits a notable G_md boosting. However, this comes at the cost of a reduced linear differential voltage range, with output current saturation occurring near ±100 mV. This limitation is not critical for input stages of high-gain amplifiers, as the virtual short at the inputs effectively mitigates the impact of the reduced linear range. Moreover, as from Figure 7b the transconductance is sensitive to the CM value, exhibiting nearly a ±10% G_md variation. Therefore, the overall DC gain and the gain-bandwidth product (G_md/C_C, where C_C is the frequency compensating capacitance) are functions of the common-mode input. Such variation, although limited, is of course not desirable, as it leads to inconsistent amplifier performance across different operating conditions. Another important trade-off not considered in this paper is that the transconductance boosting by means of partial positive feedback modifies the position of the secondary poles, thus reducing the maximum achievable bandwidth.

Finally, circuit sensitivity to temperature was assessed by plotting in Figure 7c the value of G_md/I_Q as a function of T in °C. V_CM = V_DD/2 was again set. Circuits in [49] shows the highest sensitivity to temperature with the largest percentual variations over the 0 to 120 °C range considered. Conversely, circuit in [47] shows the minimum variation with temperature.

Figure 8 is related to Tail-less Class A BD solutions. In Figure 8a, only solution [53] achieves a maximum current marginally exceeding I_Q, thus can be still considered within Class A topologies. Solutions [52,54,57] display a more consistent and linear slope compared to [54] throughout the differential input voltage range. Nevertheless, [53] demonstrates the highest slope (G_md) for a narrow input range, approximately ±100 mV. Figure 8b reveals that all configurations are affected by G_md/I_Q variations with common mode, spanning from 25% to 50%. Finally, Figure 8c depicts the value of G_md/I_Q as a function of T. V_CM = V_DD/2 was again set. Circuit in [53] shows the highest sensitivity to temperature, whereas circuit in [52] shows the minimum one.

Figure 9 is related to the second set of tail-less BD input stages, demonstrating their class AB behavior because I_out/I_Q values greater than the unity are achieved. Compared to class A solutions, a high transconductance is also attained. Specifically, the circuit in [58] operates only for negative v_d. This limitation arises from the BD current mirror M₇–M₈, seen in Figure 5c, where increased input current beyond the standby value raises the input voltage, driving M₇ out of saturation. The largest I_out/I_Q ratio is achieved by [57]. However, Figure 9b shows that all topologies exhibit varying transconductance with V_CM, with [57] displaying the most significant variation. Figure 9c shows that [58] has the highest sensitivity to temperature.

Table 2. Common-mode and power supply transconductance values of analyzed solutions with CMRR and PSRR at DC (mean and standard deviation, 1000 Monte Carlo iterations).

Class A/AB Tailed(T), Tail-Less(TL)	Ref.#	Gmcm [nA/V] @VCM = VDD/2	Gmdd [nA/V] @VCM = VDD/2	CMRR [dB] Mean/σ	PSRR [dB] Mean/σ
A,T	[47]	0.0545	1.2	59.3/6.6	32.4/8.5
	[49]	0.067	0.78	81.6/7.1	60.8/8.9
	[50]	0.0613	37.9	81.95/0.9	20.15/0.3
A,TL	[52]	3.78 *	22.8	25.9 */0.5	10.3/0.17
	[53]	40.3	438	37.5/5.4	15.7/0.58
	[54]	0.345	3.65	51.5/3.5	30.9/1.1
	[55]	49.7	50	34.96/6.4	33.8/1.3
AB,TL	[56]	7.07	65.3	60.6/1.8	41.3/0.35
	[57]	17.5	17.2	49.4/8.3	46.95/9.1
	[58]	13.6	46.3	42.4/4.1	29.7/5.8

* without common-mode feedback circuit.

shows in the third and fourth columns the value of G_mcm and G_mdd obtained again at V_CM = V_DD/2 (see Figure 6b,c). As expected, the lowest G_mcm values are achieved by Class A topologies [47,49,50]. However, only [47,49] display similarly competitive performance in G_mdd, while [50] provides one of the worst performances. In the same Table 2 we show CMRR (G_md/G_mcm) and PSRR (G_md/G_mdd) with their mean and standard deviation from 1000 Monte Carlo simulations at DC. The CMRR and PSRR of all circuits displayed nearly Gaussian behavior, enabling a meaningful use of statistical parameters. The Class A tailed solutions [49,50] yielded the highest CMRR with [50] the smallest standard deviation but it exhibited one of the lowest PSRR. Topology [49] showed also the highest PSRR, but both high CMRR and PSRR values are obtained at the cost of large variations attributed to its positive feedback mechanism. Of the tail-less solutions, [56] demonstrated the superior CMRR and the third best PSRR, while [57], ranking second for PSRR, presented a larger standard deviation. Figure 10a,b show, respectively, the statistical distribution of the magnitude of CMRR and PSRR, for the representative cases [49,50,56]. The larger standard deviation of [50] is apparent.

Corner simulations were also performed, and their results are summarized in

Table 3. Corner Simulation Results.

Ref.#	CMRR [dB]				PSRR [dB]
	FF	FS	SF	SS	FF	FS	SF	SS
[47]	42.63	59.09	51.09	48.22	22.32	22.61	21.74	19.62
[49]	59.39	69.93	69.84	76.19	44.45	46.79	51.26	52.06
[50]	82.41	83.04	82.32	86.56	18.19	20.47	19.51	20.96
[52]	23.05	25.49	25.44	26.95	9.53	10.57	10	10.74
[53]	52.8	29.39	75.46	30.11	11.92	14.19	15.73	16.55
[54]	67.11	65.63	44.93	45.45	31.31	31.96	33.38	34.94
[55]	46.43	46.39	25.85	25.62	38.01	38.89	35.8	30.76
[56]	64.97	66.07	55.83	56.54	42.45	42.33	41.01	41.45
[57]	41.51	35.86	43.75	64.81	36.23	32.68	33.8	37.07
[58]	27.43	33.98	34.41	32.65	12.07	19.78	17.81	15.05

. Comparing the solutions [53] and then [57] show the largest CMRR variation, whereas [50] presents the minimum change. PSRR is generally characterized by a smaller variation.

Finally, noise simulations were carried out. Equivalent input noise voltage for all configurations was evaluated at three frequencies (10 Hz, 100 Hz, and 10 kHz) and is reported in

Table 4. Noise Simulation Results.

Ref.#	$\mathbf{Input}\mathbf{Noise}\left[\mathsf{\mu }\mathbf{V}/\sqrt{\mathbf{H}\mathbf{z}}\right]$			FoM [Hz/V4]
	@ 10 Hz	@ 100 Hz	(White) @ 10 kHz	@ 10 Hz	@ 100 Hz	(White) @ 10 kHz
[47]	112	33	5.8	1.50 × 10−4	1.73 × 10−3	0.06
[49]	42.7	12.2	1.9	1.18 × 10−2	1.45 × 10−1	5.98
[50]	14	4.9	2.7	4.62 × 10−2	3.77 × 10−1	1.24
[52]	9	3	1.4	7.67 × 10−2	6.91 × 10−1	3.17
[53]	45.8	13.3	2.8	1.14 × 10−2	1.35 × 10−1	3.04
[54]	31.4	9.3	2.1	5.08 × 10−3	5.79 × 10−2	1.14
[55]	23	6.9	0.9	1.08 × 10−2	1.20 × 10−1	7.06
[56]	3	1.3	0.9	2.80	1.49 × 101	31.07
[57]	28.5	9.3	5	8.99 × 10−2	8.44 × 10−1	2.92
[58]	10.3	4	2.9	3.69 × 10−1	2.44	4.65

. The value at 10 kHz represents only white noise, while the values at 10 Hz and 100 Hz also include the flicker noise contribution. Solutions [55,56] exhibit the lowest white noise values, 0.9 $\mathsf{\mu }\mathrm{V}/\sqrt{\mathrm{Hz}}$. This is not surprising, as both circuits have the largest standby current consumption, 1.41 mA and 1.0 mA, respectively (from Table 1). For a fairer and more comprehensive comparison of the different topologies, a Figure of Merit (FoM) is introduced, as defined in (24):

$$FoM={\displaystyle \frac{G_{md}}{P_{DC}{S}_{v,in,\mathrm{white}}}}$$

(24)

It essentially quantifies how efficiently a transconductor provides its primary function (G_md) for a given amount of power consumed and noise generated. A higher FoM value indicates that the transconductor design achieves a more favorable trade-off. Solution [56] remains the best achieving an FoM value exceeding 31 Hz/V⁴). This is followed by [49,55]. When considering low-frequency noise, the best performance is achieved by [56,57,58] (in that order), i.e., the class-AB solutions.

5. Conclusions

This work aimed to bridge the gap between theoretical exploration and practical application of body-driven techniques for operational transconductance amplifier input stages, especially within the demanding constraints of ULV and ULP operation. The investigation into subthreshold-based BD input stages, categorized by topology (tailed and tail-less) and operating class (A and AB), has laid the groundwork for their potential in power-sensitive applications. The subsequent data considerations will present a detailed analysis of the simulated performance of these topologies, offering crucial insights into their practical limitations and advantages, thus substantiating the theoretical findings presented herein.

For achieving G_md efficiency (G_md/I_Q) and current drive, Class AB tail-less solutions [57,58] demonstrate the best performance, with [57] significantly outperforming the others. Among Class A topologies, positive feedback mechanisms in [49,53] lead to the best G_md/I_Q ratios. It is important to observe that unlike all other topologies that operate at 300 mV, ref. [49] requires a higher supply voltage of 400 mV. For achieving high CMRR, Class A tailed solutions [49,50] are the most effective, with [50] offering better robustness against process variations. Reference [56] provides a good balance of CMRR and PSRR on average, with low standard deviation. Also, for applications demanding high linearity, tailed Class A topologies, particularly [47,50], are advantageous. Regarding noise performance, class AB solutions offer the best performance, especially concerning flicker noise. An analysis of frequency performance—an aspect not covered in this paper—would also be relevant, as this performance is often limited in solutions that utilize feedback, especially positive feedback.

These findings underscore the importance of carefully selecting the appropriate body-driven input stage topology based on the specific performance requirements of the target application, considering the inherent trade-offs between gain, linearity, common-mode and power supply rejection, and robustness against process variations.