Low-Voltage Mixed-Signal CMOS Integrated Circuits for Emerging Applications

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: 20 July 2026 | Viewed by 4186

Special Issue Editors


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Guest Editor
Department of Information Engineering, University of Pisa, 56122 Pisa, Italy
Interests: mixed-signal integrated circuits; sensor interfaces; voltage references; current references; data converters; oscillators; cryogenic CMOS

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Guest Editor
Department of Information Engineering, University of Pisa, 56122 Pisa, Italy
Interests: MEMS devices; integrated sensors/actuators; sensor interfaces; mixed-signal integrated circuits
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Special Issue Information

Dear Colleagues,

Emerging electronic application fields have created a clear need for novel architectures and design methods that allow for mixed-signal integrated circuits to reliably operate in low-supply voltage conditions, ranging from just below one volt to a few hundred millivolts. Low-voltage operation is crucial to enable low-cost smart sensing systems for Internet of Things modules, wearable and implantable medical devices, and environmental monitoring nodes, often meant to operate relying only on low and inconstant energy-harvested supplies. Furthermore, low-supply conditions are pursued to optimize the efficiency of digital circuits in power-constrained applications. Finally, beyond these contexts, low-voltage design principles are also relevant to emerging cryogenic applications, such as space exploration, quantum computing and quantum sensing; due to the increase in MOSFET threshold voltage at cryogenic temperatures, reductions in the available voltage headroom and design strategies originally developed for low-voltage scenarios are highly applicable. Across such a diverse application framework, conventional circuit blocks find limited use, while inverter-like architectures, body-driving techniques, and deep-subthreshold biasing arise as the prevailing design strategies. This Special Issue seeks to explore circuit topologies and design methods, spanning both analog and digital domains, aiming to optimize integrated circuits for low-voltage low-power applications and foster advancements in next-generation electronic technologies. This Special Issues welcomes both original research articles and reviews that focus on, but are not limited to, the following topics:

  • Low-voltage analog and mixed-signal circuit blocks, including amplifiers, comparators, reference circuits, data converters, etc.;
  • Digital circuits optimized for low-voltage and/or low-power applications;
  • Low-power Internet of Things modules;
  • Smart sensing devices;
  • Wearable and implantable medical devices;
  • Cryogenic CMOS circuits deploying techniques originally devised for low-voltage scenarios.

Dr. Francesco Gagliardi
Dr. Massimo Piotto
Guest Editors

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Keywords

  • integrated circuit
  • low voltage
  • low power
  • inverter-like
  • body driving
  • subthreshold
  • sensor node
  • wearable devices
  • Internet of Things
  • cryo-CMOS

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Published Papers (4 papers)

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Research

18 pages, 664 KB  
Article
Efficient n-th Root Computation on Microcontrollers Employing Magic Constants and Modified Newton and Householder Methods
by Cezary J. Walczyk, Maciej Jurgielewicz and Jan L. Cieśliński
Electronics 2026, 15(1), 129; https://doi.org/10.3390/electronics15010129 - 26 Dec 2025
Viewed by 391
Abstract
With the growing number of applications in embedded systems—such as IoT modules, smart sensors, and wearable devices—there is an increasing demand for fast and accurate computations on resource-constrained platforms. In this paper, we present a new method for computing n-th roots in floating-point [...] Read more.
With the growing number of applications in embedded systems—such as IoT modules, smart sensors, and wearable devices—there is an increasing demand for fast and accurate computations on resource-constrained platforms. In this paper, we present a new method for computing n-th roots in floating-point arithmetic based on an initial estimate generated by a “magic constant,” followed by one or two iterations of a modified Newton–Raphson or Householder algorithm. For cubic and quartic roots, we provide C implementations operating in single-precision floating-point format. The proposed algorithms are evaluated in terms of maximum relative error and execution time on selected microcontrollers. They exhibit high accuracy and noticeably reduced computation time. For example, our methods for computing cubic roots outperform the standard library function cbrtf() in both speed and precision. The results may be useful in a variety of fields, including biomedical and biophysical applications, statistical analysis, and real-time image and signal processing. Full article
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18 pages, 612 KB  
Article
A Novel and Highly Versatile Voltage Monitoring Circuit Enabling Power Consumption and Area Minimization
by Elisabetta Moisello, Alessandro Cabrini, Andrea Tellatin, Edoardo Bonizzoni and Piero Malcovati
Electronics 2026, 15(1), 60; https://doi.org/10.3390/electronics15010060 - 23 Dec 2025
Viewed by 1342
Abstract
Voltage monitoring circuits are a fundamental block in energy-harvesting-powered applications, as typically the system operation has to be enabled only after a certain supply voltage is reached after a cold start or intermediate voltage levels have to be detected during start-up. The voltage [...] Read more.
Voltage monitoring circuits are a fundamental block in energy-harvesting-powered applications, as typically the system operation has to be enabled only after a certain supply voltage is reached after a cold start or intermediate voltage levels have to be detected during start-up. The voltage values of interest vary depending on the specific system; hence, a versatile voltage monitoring circuit scheme that can be easily adapted for the desired voltage is particularly appealing. Furthermore, in energy-harvesting-powered applications, special care must be paid to power consumption minimization, in order to ensure self-sustainability of the system, and to area occupation, thus enabling a small form factor and low cost. To address these requirements, this paper proposes a novel, highly versatile voltage-monitoring circuit for energy-harvesting-powered applications that minimizes power consumption and area occupation. Indeed, the proposed voltage monitor implementation, relying on cascaded PMOS-based and NMOS-based voltage detectors, can be easily adapted to any desired voltage level, also achieving high voltage levels to be detected by adding (multiple) diode-connected transistors in the first stage while maintaining the voltage monitor output rail-to-rail and avoiding static power consumption from the cascaded digital gates. The proposed solution, targeting a 800 mV voltage level to be detected, was designed in a 180 nm CMOS triple-well technology and extensively validated through simulations in Cadence Virtuoso. Furthermore, it was bench-marked with an implementation in the same process based on the standard voltage monitor scheme (including the necessary cascaded logic gates for achieving a rail-to-rail output) available in literature, showcasing a reduction up to about 1700× in power consumption and 3.87× in area occupation, considering a preliminary area estimation, when triple-well devices are employed, whereas, when relying only on standard devices, although no significat area benefit is obtained, a reduction of up to about 400× in power consumption is achieved. Full article
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13 pages, 11609 KB  
Article
A 12-bit 100 MSPS Full-Swing Current-Steering Digital-to-Analog Converter with Half-Power Supply Calibration Technique
by Kwangjin Park, Seung Gu Choi, Jintae Kim, Myungsik Kim, Hyunjin Song, Minkyu Song and Soo Youn Kim
Electronics 2025, 14(19), 3955; https://doi.org/10.3390/electronics14193955 - 8 Oct 2025
Viewed by 970
Abstract
We present a digital-to-analog converter (DAC) with full-swing DAC output and a proposed half-power supply calibration technique. To generate a full-swing DAC output, symmetric thermometer decoders and an output selector are implemented to select the appropriate current cell according to the output voltage [...] Read more.
We present a digital-to-analog converter (DAC) with full-swing DAC output and a proposed half-power supply calibration technique. To generate a full-swing DAC output, symmetric thermometer decoders and an output selector are implemented to select the appropriate current cell according to the output voltage range. Furthermore, to improve the linearity, we propose a half-power supply calibration circuit consisting of comparators and calibration counters to control the current of the current cells at the half-power supply voltage point, where the voltage mismatch typically occurs. The DAC was fabricated in a 28 nm CMOS process, with a full chip area of 0.95 mm × 0.93 mm. The measurement results demonstrate a maximum voltage mismatch improvement of 95% when using the proposed half-power supply calibration technique, with DNL and INL values of 0.39 and 1.15 LSB. The total power consumption was 73.8 mW at 100 MSPS, with analog and digital supply voltages of 1.8 and 1.0 V, respectively. Full article
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21 pages, 5551 KB  
Article
State-Space Modelling of Schottky Diode Rectifiers Including Parasitic and Coupling Effects up to the Terahertz Band
by Martins Aizanabor Odiamenhi, Haleh Jahanbakhsh Basherlou, Chan Hwang See, Naser Ojaroudi Parchin, Keng Goh and Hongnian Yu
Electronics 2025, 14(18), 3718; https://doi.org/10.3390/electronics14183718 - 19 Sep 2025
Cited by 5 | Viewed by 973
Abstract
A nonlinear state-space model for Schottky diode rectifiers is presented that incorporates junction dynamics, layout parasitic effects, and electromagnetic coupling effects. Unlike prior approaches, the model resolves conduction intervals under harmonic-rich excitation and integrates electromagnetic voltage–current feedback to capture field-induced perturbations at high [...] Read more.
A nonlinear state-space model for Schottky diode rectifiers is presented that incorporates junction dynamics, layout parasitic effects, and electromagnetic coupling effects. Unlike prior approaches, the model resolves conduction intervals under harmonic-rich excitation and integrates electromagnetic voltage–current feedback to capture field-induced perturbations at high frequencies. The framework was validated through the design of a 5.8 GHz rectifier, achieving 62% RF–DC efficiency at −10 dBm into a 500 Ω load, with close agreement between the simulation and measurement. The results confirm the model’s predictive accuracy and its utility for high-efficiency rectenna systems in microwave and terahertz applications. Full article
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