A Wide-Input-Range LDO with High Output Accuracy Based on Digital Trimming Technique

Abstract

Temperature is a crucial indicator in monitoring industrial operations. Two-wire temperature transmitters, known for their precise measurements, are extensively used in sectors like crude oil extraction, refining, and fine chemicals. These transmitters can handle a maximum input voltage of 36 V and output a current signal up to 20 mA, enhancing resistance to electromagnetic interference and line noise while improving system compatibility and safety. In contrast, traditional low-dropout linear regulators (LDOs) typically have an input voltage below 6 V and suffer from limitations such as low power supply rejection ratio (PSRR), inadequate current driving capability, and significant temperature drift. This paper proposes a wide-input-range LDO with enhanced output accuracy and digital trimming, designed using the 180 nm BCD process. It incorporates dynamic mismatch compensation, digital trimming, and a strong-drive buffer, achieving a broad input voltage range and high PSRR with minimal temperature drift. The input voltage spans 6 V to 60 V, the output voltage is 1.8 V, and the PSRR reaches 124.5 dB. Across a temperature range of −40 °C to 130 °C, the maximum output voltage error is only 0.3%. This makes it highly suitable for high-precision circuit power supplies in industrial process control.

1. Introduction

Two-wire temperature transmitters convert temperature-dependent voltage variations across a resistor into current signals for long-distance transmission. They commonly employ PT100 resistors, known for their precise resistance-temperature characteristics, as sensing elements. The output current signals are typically accurate to within 0.1% [1]. To detect subtle signal changes effectively, a stable processing environment is essential. The industry often uses high input voltages and large output currents, allowing these transmitters to operate within a 10 V to 36 V input range and output current signals from 4 mA to 20 mA. This imposes design challenges on the voltage withstand and current driving capabilities of the power management module. Traditional low-dropout linear regulators (LDOs), with input voltages ranging from 1.8 V to 6 V, generally fail to meet these requirements [2]. As two-wire temperature transmitters evolve, the impact of high-frequency ripple voltage from power lines on system accuracy has become more pronounced. The PSRR of traditional LDOs is constrained by loop gain, and enhancing loop gain compromises LDO stability, complicating the maintenance of high PSRR alongside a stable output voltage. Consequently, wide-input-range LDOs with high PSRR and strong current driving capabilities are increasingly employed in two-wire temperature transmitter systems [3,4].

In designing wide-input-range LDOs, the primary research focus is enhancing both input voltage range and output accuracy while maintaining a high power supply rejection ratio (PSRR). Techniques commonly employed in wide-input-range LDOs include current compensation, dual-loop, and two-stage voltage regulation technologies. Current compensation technique encompasses base current compensation at the error amplifier’s input and current buffer compensation at its output. Base current compensation leverages the PNP transistor’s β value to determine output voltage, mitigating feedback resistor thermal noise and ensuring LDO output accuracy. However, its line regulation rate is 35 μV/V, making it sensitive to input voltage fluctuations [5]. Current buffer compensation maintains loop stability under high gain or large load capacitance through zero-pole tracking, yet its power supply ripple rejection is suboptimal, with PSRR below 90 dB [6,7]. Dual-loop technique features a two-stage loop with a flipped voltage follower (FVF)-based fast-response loop and a high-gain loop. It achieves fast transient response and high output accuracy but has a limited input voltage range, with only a 10 V difference between its upper and lower limits [8,9,10,11,12]. Wide-input-range LDOs generally comprise several modules. Except for the high-voltage to low-voltage conversion module, which requires high-voltage connectivity, the other modules must function in a low-voltage environment. To shield these low-voltage modules from high-voltage exposure and mitigate the effects of power supply ripple, noise, or impulses, a secondary voltage regulation technique is commonly employed. A pre-regulator module at the system input isolates the low-voltage modules from high input voltage, converting it into multiple low voltages that act as reference or bias voltages for these modules. However, current secondary voltage regulation structures lack a compensation mechanism for circuit mismatch. Consequently, sudden load current changes can cause output overshoot voltages of up to 85 mV [13].

While the previous wide-input-range LDOs offer advantages over traditional LDOs, such as enhanced high-voltage tolerance and output accuracy, they fall short in managing output voltage temperature drift. This limitation restricts their applicability in extreme temperature conditions.

To address these issues, this paper proposes a wide-input-range LDO incorporating a temperature trimming technique. The LDO features a two-stage design: a high-voltage control circuit and a voltage stabilization circuit. The high-voltage control circuit employs dynamic mismatch compensation and a simplified Brokaw structure, effectively minimizing output voltage fluctuations and improving PSRR and transient response when input voltage or load current shifts occur. The voltage stabilization circuit utilizes digital trimming via a switched resistor array, a strong-drive buffer and a high-precision Cascode error amplifier, mitigating temperature drift, enhancing system bandwidth, and further improving the PSRR. This enables the LDO to consistently deliver a 1.8 V output across varying operating temperatures, making it ideal for powering digital circuits in industrial field measurements.

2. High-voltage Control Circuit Architecture and Implementation

Figure 1 shows the specific architecture of the high-voltage control circuit, which includes two parts: the step-down circuit and the output stage.

Figure 1. Block diagram and practical circuit implementation of the proposed LDO.

2.1. Step-Down Circuit

Figure 1 illustrates the step-down circuit, which utilizes a dynamic adaptive compensation technique to reduce input voltages from 6 V to 60 V to a 5 V power supply (V₅) and deliver a 3.5 V bias voltage (V_3D5) for subsequent modules. Unlike conventional LDOs that use bandgap reference voltage sources, this circuit employs high-voltage-resistant devices, enabling both bias voltage provision and high-voltage control.

The diode D1 is a Zener diode. Upon reaching its reverse breakdown voltage, it undergoes reverse breakdown, causing a sharp increase in reverse current while maintaining a stable voltage across its terminals [14]. Consequently, diode D1 stabilizes the voltage at node A at 5.7 V. This stabilization ensures a consistent voltage drop across resistor R1, allowing it to function as a constant current source to limit the current. M1 is a voltage regulator employing a high-voltage depletion-type NMOS. When the input voltage is below M1’s breakdown voltage, V₅ mirrors the input voltage. If the input exceeds M1’s voltage, M1 caps V₅ at 5V, supplying power to subsequent circuits. Capacitor C1, connected to M1’s gate, mitigates circuit overshoot voltage. Q3, Q4, and R3 constitute a constant current source, supplying bias current to the following circuits. Q1, Q2, R2, and R3 form a proportional current mirror. Differential pair transistors Q1 and Q2 may suffer from mismatch due to process errors or environmental factors, causing a deviation of I₂/I₁ from the ideal 1/3 ratio.

Unlike the traditional current bias circuit, Q3, Q4, and R3 function as both a constant current source and a dynamic mismatch compensation mechanism for the current mirror, addressing mismatch issues and reducing temperature drift [15,16]. Q3 and Q4 establish a positive feedback loop. In the branch containing Q1, any change in the collector current I₁ of Q1 leads to a corresponding change in the collector current I₃ of Q3. This positive feedback loop causes I₃ to amplify the response of the collector current I₂ of Q2 to changes in I₁, thereby enhancing the accuracy of the proportional current mirror. R3 is in series with the emitter of Q4, creating a negative feedback loop. In the branch containing Q2, if temperature fluctuations and process variations reduce the currents I₂ and the collector current I₄ of Q4, the voltage drop across R3 increases. This reduces the base-emitter voltage V_BE2 of Q2, thereby mitigating the change in current amplitude. Simultaneously, R3 dampens V_IN fluctuations, stabilizing I₁ and I₂. Together, Q3, Q4, and R3 form a coordinated mismatch compensation system using both positive and negative feedback. If the base-emitter voltage V_BE1 of Q1 is slightly less than V_BE2, the positive feedback reduces I₂, while R3, through negative feedback, adjusts I₄, aligning I₁ and I₂ closer to the ideal proportional mirror.

Under the condition of considering the mismatch error, the ratio of I₁ to I₂ can be expressed as

$${\displaystyle \frac{I_2}{I_1}}={\displaystyle \frac{1}{3}}+\mathrm{\Delta }\gamma \cdot (1-A_{\mathrm{F}}\cdot \beta )$$

(1)

In the formula, β (0 < β < 1) represents the attenuation coefficient for negative feedback on error, A_F denotes the positive feedback gain, and Δγ indicates the mismatch error of I₂/I₁. When A_F × β ≈ 1, Δγ is significantly reduced, allowing I₂/I₁ to approach the ideal value of 1/3.

2.2. Simplified Brokaw Output Stage

In the step-down circuit, the M2 transistor functions as both a proportional current mirror load and a source of 3.5 V bias voltage (V_3D5) for the subsequent circuit. Following two stages of proportional mirroring, I₂ flows through the branch containing Q6 and R4, establishing a bias voltage of 1.2 V (V_BIAS). However, V_BIAS is notably influenced by the current ripple voltage, potentially diminishing the LDO’s PSRR.

The reference voltage V_REF at the output of the simplified Brokaw output stage is

$$V_{\mathrm{REF}}=V_{\mathrm{G}0}-\left[V_{\mathrm{G}0}-V_{\mathrm{BE}}\left(T_{\mathrm{r}}\right)\right]{\displaystyle \frac{T}{T_{\mathrm{r}}}}-\left(\eta -\xi \right)V_{\mathrm{T}}\ln \left({\displaystyle \frac{T}{T_{\mathrm{r}}}}\right)+2{\displaystyle \frac{R_6}{R_5}}{V}_{\mathrm{T}}\ln \mathrm{n}$$

(2)

In the formula, V_G0 represents the reference temperature T_r and the silicon bandgap voltage, T_r is 300 K. After simplification, we obtain

$$V_{\mathrm{REF}}=V_{\mathrm{BE}9}+2{\displaystyle \frac{V_{\mathrm{T}}{R}_6\ln \mathrm{n}}{R_5}}$$

(3)

Figure 1 illustrates the proposed simplified Brokaw output stage, which streamlines the second-stage circuit of the traditional Brokaw structure [17,18]. The high-voltage control circuit and boost transistor M4 function as a clamping circuit to lower static power consumption. A low-pass filter, consisting of R7 and C2, is employed to eliminate high-frequency noise, enhancing power supply ripple rejection (PSRR) in the high-frequency range. The PSRR achieves 70.74 dB at 1 MHz.

3. Voltage Stabilization Circuit Architecture and Implementation

Figure 1 illustrates the proposed LDO voltage stabilization circuit, comprising an error amplifier, a strong-drive buffer, voltage-dividing feedback resistors (R8 and R_F), a switching resistor array, and a compensation capacitor C3. The error amplifier’s architecture, detailed in Figure 2, includes three stages: a start-up circuit, a current biasing stage, and an output stage. The output stage employs a wide-swing, high-precision Cascode structure with PMOS input-pair transistors. The differential pair within the internal current reference, along with R2, establishes a negative feedback mechanism that significantly mitigates the impact of power supply voltage fluctuations on the output, thereby enhancing the PSRR and providing a robust loop frequency response and a broad input common-mode voltage range. The LDO’s output voltage V_O is

$$V_{\mathrm{O}}=V_{\mathrm{REF}}\times ({\displaystyle \frac{R_{\mathrm{F}}+R_{\mathrm{S}}}{R_8+R_{\mathrm{F}}+R_{\mathrm{S}}}})$$

(4)

Figure 2. Structure of the error amplifier.

In the formula, R_S represents the output resistance value of the resistor switch array (Res_Switch), which is controlled by the three-digit binary signal S_<3:0>, and the output voltage is jointly determined by the feedback resistor network and V_REF.

3.1. Strong-Drive Buffer

Figure 1 illustrates the strong-drive buffer proposed in this paper, comprising two identical stages: a feedback stage and an output stage. The output stage’s load transistor, MP, also functions as the LDO system’s power transistor. In this two-stage design, all pairs of MOS transistors, except for M6 and MP, share identical W/L ratios, ensuring V_BF accurately mirrors minor output voltage variations. The power transistor MP features a large W/L ratio to handle high load currents, while M6’s smaller W/L ratio precisely mimics the feedback loop’s low current. This configuration decouples the feedback loop from the system output, shielding it from load noise interference. Consequently, the feedback loop can employ a low-current strategy that is highly sensitive to load noise, thus minimizing the system’s quiescent current. This approach enhances current efficiency while maintaining robust current-driving capability.

This buffer, utilizing the pole separation technique [19,20,21], offers dynamic compensation under varying loads, outperforming traditional source followers. In the feedback stage, an increase in load current leads to an increase in I_P, a decrease in voltage at point B, and an increase in current I_D14 through M14. Consequently, the current through the current mirror formed by M15 and M8 rises, resulting in a higher current I_D7 through M7. This escalation causes M7’s transconductance g_m7 to increase with the load current, similarly elevating the transconductance g_m6 of the feedback output transistor. Based on the same structure, the output impedance R_O of the buffer’s output stage is:

$$R_{\mathrm{O}}={\displaystyle \frac{1}{g_{m11}+g_{m\mathrm{P}}}}$$

(5)

Formula (5) demonstrates that this strongly driven buffer effectively reduces the output resistance R_O as the load current rises, thus elevating the frequency of the output pole. Figure 3 compares the loop frequency responses before and after compensation. Initially, the low-frequency pole p* splits into two high-frequency poles, p₂ and p₃, enhancing the loop’s gain-bandwidth product (GBW).

Figure 3. Diagram of frequency compensation.

3.2. Digital Temperature Trimming

Figure 1 illustrates the digital temperature trimming technique proposed in this paper. The temperature regulation is accomplished by integrating a switch resistance array, Res_Switch, within the voltage stabilizing circuit. This system interfaces with a temperature sensor, control logic module, I2C control module, and off-chip EEPROM [22], all external to the LDO. The temperature sensor is based on a 16-bit Σ-Δ ADC architecture, and the data reading from the off-chip EEPROM is based on the I2C bus protocol [23,24,25]. The switch resistor array, Res_Switch, is governed by the four-bit binary signal S_<3:0>. To balance system scale and output accuracy, the LDO’s output voltage is trimmed every 10 °C across the operating range of −40 °C to 130 °C, resulting in 18 trimming points. Prior to activation, a post-layout simulation of the LDO’s output voltage is performed. At each trimming point, S_<3:0> is adjusted to minimize error, and these values are stored in separate units of the off-chip EEPROM. Upon activation, the temperature sensor outputs various control signals, Ku_<15:0>, to the control logical module at different temperatures. When the control logical module receives the Ku_<15:0> for a specific trimming point, it interfaces with the I2C control module. This module retrieves the corresponding S_<3:0> from the off-chip EEPROM and writes it to its internal register. The S_<3:0> is then sent to the switch resistor array to trim the output voltage according to temperature. It is noteworthy that the values of S_<3:0> at the trimming points of 20 °C and 30 °C are identical, ensuring a unique S_<3:0> value at the room temperature of 27 °C when all other conditions are identical.

Figure 4 illustrates the structure of the switch resistor array, Res_Switch. A 4-16 decoder translates S into a 16-bit thermometer code, where each bit, from the 1st to the 16th, maps to signals I₀ through I₁₅. When the control signal represents a decimal number n (0 ≤ n ≤ 15), the signal In transitions from low to high, activating the NMOS switch Mn. The series resistors R through Rn are then connected to the feedback loop, determining the total output resistance R_S, as expressed in the formula

$$R_{\mathrm{S}}={\displaystyle \sum _0^{\mathrm{n}}{R}_{\mathrm{n}}}\left(0\le \mathrm{n} \le 15\right)$$

(6)

Figure 4. Structure of the switch resistor array.

3.3. Loop Small-Signal Analysis

Figure 5 presents the small-signal equivalent circuit of the voltage regulator module loop. The output node of the first-stage amplifier features two cascaded two-stage amplifier branches. In the diagram, g_m1 denotes the transconductance of the error amplifier, g_m6 and g_m7 represent the transconductance of M6 and M7, respectively, g_mP is the transconductance of the power transistor, and g_m11 is the transconductance of M11. The output resistances are R_oa for the error amplifier, R_o6 for M6, R_o7 for M7, and R_o11 for M11. The output capacitances are C_oa for the error amplifier, C_o6 for M6, C_o7 for M7, and C_o11 for M11. R_O and C_L are the load resistance and capacitance at the output terminal. In the small-signal loop analysis, only the series branch of g_m6 and g_m7, which includes feedback, is considered.

Figure 5. The small-signal equivalent circuit diagram of the voltage stabilizing module.

Solving the nodal current equations yields the system transfer function as follows:

$$T(s)={\displaystyle \frac{V_{\mathrm{BF}}(s)}{V_{\mathrm{IN}}(s)}}=-{\displaystyle \frac{g_{m1}{g}_{m6}{g}_{m7}{R}_{oa}{R}_{o6}{R}_{o7}{R}_9}{(R_8+R_9)\left[1+s{R}_{oa}(C_{oa}+C_3)\right]\left[1+s{R}_{o6}{C}_{o6}\right]\left[1+s{R}_{o7}{C}_{o7}\right]}}$$

(7)

In Figure 3, three poles are depicted, which can be derived from the formula. With the addition of compensation capacitor C₃, the first pole’s frequency shifts rightward on the coordinate axis, enhancing the phase margin and system stability. The system’s DC gain is

$$A_{\mathrm{DC}}=-{\displaystyle \frac{g_{m1}{g}_{m6}{g}_{m7}{R}_{oa}{R}_{o6}{R}_{o7}{R}_9}{R_8+R_9}}$$

(8)

The gain-bandwidth product (GBW) of the system is given by the following formula:

$$\mathrm{GBW}=|A_{\mathrm{DC}}|\cdot f_{p1}={\displaystyle \frac{g_{m1}{g}_{m6}{g}_{m7}{R}_{o6}{R}_{o7}{R}_9}{2\pi (R_8+R_9)(C_{oa}+C_3)}}$$

(9)

4. Simulation Results and Discussion

The LDO circuit proposed in this paper is fabricated using the 180 nm 1P4M BCD process. The power transistor MP employs a deep P-well NMOS transistor to suppress parasitic effects. A photograph of the transmitter chip containing the proposed LDO is shown in Figure 6. The chip size is 5.88 mm², and all on-chip digital modules are powered by the proposed LDO.

Figure 6. Photo of transmitter chip containing LDO proposed in this paper.

Figure 7 and Figure 8 illustrate the loop stability of the voltage regulator circuit across different process corners and temperatures, with load currents from 0.1 mA to 100 mA and an input voltage of 60 V. Post-layout simulation results reveal that, irrespective of process variations and environmental conditions, the DC gain spans 80.5 dB to 100.3 dB, the minimum GBW is 875 kHz, and the phase margin is at least 61.5° (more than 60°), confirming superior loop stability. Figure 9 demonstrates that at load currents of 0.2 mA (light load), 1 mA (medium load), and 50 mA (heavy load), the PSRR ranges from 118.6 dB to 124.5 dB, underscoring the LDO’s robust power supply ripple rejection.

Figure 7. Loop gains under different process corners, temperatures, and load currents. (a) TT, 27 °C; (b) FF, 130 °C; (c) SS, −40 °C.

Figure 8. Phase margins under different process corners, temperatures, and load currents. (a) TT, 27 °C; (b) FF, 130 °C; (c) SS, −40 °C.

Figure 9. PSRR under different load current levels.

Figure 10 illustrates the load and line regulation of the LDO, with a maximum line regulation of 44.2 mA and a maximum load regulation of 0.5 μV/V. Figure 11 demonstrates that across the temperature range of −40 °C to 130 °C, the maximum output voltage error decreases from 1.6% to 0.3% post-trimming, validating the effectiveness of the proposed digital trimming technique in mitigating temperature-induced voltage drift. Figure 12 depicts the LDO’s load transient response, showing an output overshoot of 32.7 mV and an undershoot of 47.2 mV when the load current changes from 0.1 mA to 100 mA at an input voltage of 6 V. At 60 V input, the loop maintains a rapid response, swiftly stabilizing the output. Figure 13 illustrates the quiescent current of the LDO across various input voltages and load currents. Across different process corners and operating temperatures, the maximum load current reaches 44.7 μA, while the minimum is 14.8 μA, highlighting its low quiescent power consumption. Figure 14 presents Monte Carlo simulation results of the LDO output voltage, aligning closely with test results under the TT process corner.

Figure 10. (a) Line regulation of the LDO; (b) load regulation of the LDO.

Figure 11. Verification of the temperature trimming function of the LDO.

Figure 12. Load transient response of the LDO: (a) input voltage is 6 V; (b) input voltage is 60 V.

Figure 13. The quiescent current of the LDO under different input voltages and load currents: (a) in the input voltage range of 6 V to 60 V; (b) in the load current range of 0.1 mA to 100 mA.

Figure 14. Monte Carlo simulation of the output voltage of the LDO.

Table 1 presents the performance of the proposed LDO alongside comparable designs and products. The LDO demonstrates significant advantages in the input voltage range and PSRR compared to similar types. It effectively balances current driving capability and current efficiency and also includes a temperature trimming function.

Table 1. Simulation performance of proposed LDO and comparison with other LDOs.

Parameter	This Work	[10]	[5]	[26]	[27]
Technology (nm)	180	250	180	180	-
Input Voltage (V)	6–60	3.6–15	2.3–20	1.8–2.5	3–40
Output Voltage (V)	1.8	3.3	0.1–19.7	1.6–2.3	3.3 & 5
Maximum Load Current ILOAD (mA)	100	50	500	200	500
PSRR (dB)	124.5	65	106	40.5	65
Load Regulation (mV/mA)	0.194	0.052	0.0008	0.055	0.03
Line Regulation (μV/V)	0.5	237	35	4860	169.2
Undershoot (mV)	47.2	52	2.56	78	-
Overshoot (mV)	32.7	50	1.6	30	-
Quiescent Current IQ (μA)	36.9	3	2000	0.9–160	17
Current Efficiency (%) *	99.96	99.99	99.6	99.92	-
Temperature Trimming	Yes	No	No	No	No

* Current Efficiency = I_LOAD/(I_LOAD + I_Q).

5. Conclusions

This paper proposes a low-dropout regulator (LDO) with digital temperature trimming, designed to meet the power supply needs of two-wire temperature transmitters. Fabricated using a 180 nm BCD process, the LDO provides a 1.8 V output. It features a two-stage design comprising the high-voltage control circuit and the voltage stabilization circuit. The high-voltage control circuit accommodates input voltages from 6 V to 60 V through dynamic mismatch compensation and a simplified Brokaw output stage. An RC low-pass filter at the output suppresses power supply ripple and enhances the power supply rejection ratio (PSRR). The voltage stabilization circuit includes a strong-drive buffer, supporting a maximum load current of 100 mA, and dynamically adjusts output impedance with the output transistor’s drain current to improve stability. A high-precision Cascode error amplifier further improves the PSRR to 124.5 dB. Digital trimming via a switched resistor array significantly reduces output voltage temperature drift. The LDO maintains a maximum output voltage error of just 0.3% across −40 °C to 130 °C, making it ideal for industrial temperature measurement circuits.