Search for Articles:
Title / Keyword
Author / Affiliation / Email
Journal
Article Type
 
 
Advanced Search
 
Section
Special Issue
Volume
Issue
Number
Page
 
3.6
1.6
Journals
JLPEA
Special Issues
Low Power Memory/Memristor Devices and Systems vol.2
share announcement

Low Power Memory/Memristor Devices and Systems vol.2

A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: closed (15 March 2023) | Viewed by 6840

Special Issue Editors

Dr. Alexander Serb

E-Mail Website
Guest Editor
School of Engineering, The University of Edinburgh, Edinburgh EH9 3FB, UK
Interests: electronic circuits; neuromorphic engineering; computational neuroscience
Special Issues, Collections and Topics in MDPI journals
Dr. Adnan Mehonic

E-Mail Website
Guest Editor
Department of Electronic & Electrical Engineering, University College London, London WC1E 7JE, UK
Interests: functional materials; nanoelectronics; memristors; energy-efficient novel computing paradigms
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Nowadays, it is true more than ever that energy considerations are a strong driver of hardware technology in applications ranging from the largest servers to the smallest sensors. Concurrently, the proliferation of AI is demanding ever more memory in order to handle the extreme workloads of its ever-expanding models.

A key part of the solution to this set of increasing pressures lies in the evolution of emerging technologies, such as memrsitive devices. They provide ultra-compact, ultra-low-power memory, both digital and analogue, with all that that implies: the abilities to hold memory, store artificial neural network weights, trim conventional circuits and much more.

In this Special Issue, we continue to seek papers that address the challenges of modern circuit design using memrsitive devices, from the finest grain of manufacturing and operating memrsitive devices, through circuit design using memristors, to the highest level of designing entire systems underpinned by memrsitive technology.

Dr. Alexander Serb
Dr. Adnan Mehonic
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1800 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Benefits of Publishing in a Special Issue

  • Ease of navigation: Grouping papers by topic helps scholars navigate broad scope journals more efficiently.
  • Greater discoverability: Special Issues support the reach and impact of scientific research. Articles in Special Issues are more discoverable and cited more frequently.
  • Expansion of research network: Special Issues facilitate connections among authors, fostering scientific collaborations.
  • External promotion: Articles in Special Issues are often promoted through the journal's social media, increasing their visibility.
  • e-Book format: Special Issues with more than 10 articles can be published as dedicated e-books, ensuring wide and rapid dissemination.

Further information on MDPI's Special Issue polices can be found here.

Published Papers (2 papers)

Download All Papers
Order results
Result details
Show export options expand_more Show export options expand_less
Select all
Export citation of selected articles as:

Research

15 pages, 7128 KiB  
Article
Exploring Topological Semi-Metals for Interconnects
by Satwik Kundu, Rupshali Roy, M. Saifur Rahman, Suryansh Upadhyay, Rasit Onur Topaloglu, Suzanne E. Mohney, Shengxi Huang and Swaroop Ghosh
J. Low Power Electron. Appl. 2023, 13(1), 16; https://doi.org/10.3390/jlpea13010016 - 9 Feb 2023
Cited by 3 | Viewed by 3594
Abstract
The size of transistors has drastically reduced over the years. Interconnects have likewise also been scaled down. Today, conventional copper (Cu)-based interconnects face a significant impediment to further scaling since their electrical conductivity decreases at smaller dimensions, which also worsens the signal delay [...] Read more.
The size of transistors has drastically reduced over the years. Interconnects have likewise also been scaled down. Today, conventional copper (Cu)-based interconnects face a significant impediment to further scaling since their electrical conductivity decreases at smaller dimensions, which also worsens the signal delay and energy consumption. As a result, alternative scalable materials such as semi-metals and 2D materials were being investigated as potential Cu replacements. In this paper, we experimentally showed that CoPt can provide better resistivity than Cu at thin dimensions and proposed hybrid poly-Si with a CoPt coating for local routing in standard cells for compactness. We evaluated the performance gain for DRAM/eDRAM, and area vs. performance trade-off for D-Flip-Flop (DFF) using hybrid poly-Si with a thin film of CoPt. We gained up to a 3-fold reduction in delay and a 15.6% reduction in cell area with the proposed hybrid interconnect. We also studied the system-level interconnect design using NbAs, a topological semi-metal with high electron mobility at the nanoscale, and demonstrated its advantages over Cu in terms of resistivity, propagation delay, and slew rate. Our simulations revealed that NbAs could reduce the propagation delay by up to 35.88%. We further evaluated the potential system-level performance gain for NbAs-based interconnects in cache memories and observed an instructions per cycle (IPC) improvement of up to 23.8%. Full article
(This article belongs to the Special Issue Low Power Memory/Memristor Devices and Systems vol.2)
►▼ Show Figures

Figure 1

25 pages, 1252 KiB  
Article
A Spintronic 2M/7T Computation-in-Memory Cell
by Atousa Jafari, Christopher Münch and Mehdi Tahoori
J. Low Power Electron. Appl. 2022, 12(4), 63; https://doi.org/10.3390/jlpea12040063 - 6 Dec 2022
Viewed by 2559
Abstract
Computing data-intensive applications on the von Neumann architecture lead to significant performance and energy overheads. The concept of computation in memory (CiM) addresses the bottleneck of von Neumann machines by reducing the data movement in the computing system. Emerging resistive non-volatile memory technologies, [...] Read more.
Computing data-intensive applications on the von Neumann architecture lead to significant performance and energy overheads. The concept of computation in memory (CiM) addresses the bottleneck of von Neumann machines by reducing the data movement in the computing system. Emerging resistive non-volatile memory technologies, as well as volatile memories (SRAM and DRAM), can be used to realize architectures based on the CiM paradigm. In this paper, we propose a hybrid cell design to provide the opportunity for CiM by combining the magnetic tunnel junction (MTJ) and the conventional 6T-SRAM cell. The cell performs CiM operations based on stateful in-array computation, which has better scalability for multiple operands compared with stateless computation in the periphery. Various logic operations such as XOR, OR, and IMP can be performed with the proposed design. In addition, the proposed cell can also operate as a conventional memory cell to read and write volatile as well as non-volatile data. The obtained simulation results show that the proposed CiM-A design can increase the performance of regular memory architectures by reducing the delay by 8 times and the energy by 13 times for database query applications consisting of consecutive bitwise operations with minimum overhead. Full article
(This article belongs to the Special Issue Low Power Memory/Memristor Devices and Systems vol.2)
►▼ Show Figures

Figure 1

Show export options expand_more Show export options expand_less
Select all
Export citation of selected articles as:
 
Displaying articles 1-2
Back to TopTop