Open AccessArticle
A Low-Power Mixed-Signal Differential In-Memory Matrix–Vector Computing Circuit Architecture with RISC-V Control for Edge AI
by
David Ng, King Hang Lam, Si Qi Bu, Wen Chin Lo, Chi Hong Chan, Roy Ng, Sunny Chan, Matt Mak, Hugo Wong, Steve Chim, Patrick Chang, Raymond Chik, Steven Wong and Wai Ming To
J. Low Power Electron. Appl. 2026, 16(3), 22; https://doi.org/10.3390/jlpea16030022 (registering DOI) - 24 Jun 2026
Abstract
Analog in-memory computing (AIMC) has emerged as a promising approach to mitigate the Von Neumann bottleneck in matrix operations, which are common in deep learning applications. However, the practical implementation of resistive crossbar arrays is limited by challenges in signed weight representation, conductance
[...] Read more.
Analog in-memory computing (AIMC) has emerged as a promising approach to mitigate the Von Neumann bottleneck in matrix operations, which are common in deep learning applications. However, the practical implementation of resistive crossbar arrays is limited by challenges in signed weight representation, conductance quantization, and device nonlinearity. This paper presents a differential mixed-signal architecture for accurate signed matrix–vector multiplication (MVM), integrated with a RISC-V microcontroller for edge inference applications. A structured digital-to-analog mapping framework encodes quantized neural network weights into programmable conductance values while preserving arithmetic correctness. The design employs voltage-mode input encoding, differential current summation, and transimpedance-based readout followed by analog-to-digital conversion, enabling single-cycle signed accumulation without duplicating crossbar resources. A 32 × 16 dual-layer prototype crossbar was fabricated and experimentally characterized. Measurements demonstrate a mean absolute percentage error (MAPE) below 1% within the linear operating region and below 4% over the full-scale conductance range. These results validate the robustness of the proposed mapping methodology and confirm the feasibility of hybrid analog–digital acceleration for edge AI systems. Consequently, this discrete prototype serves as a physical verification platform for the AIMC approach, providing valuable insights for more efficient mixed-signal computing integrated circuit (IC) designs.
Full article
►▼
Show Figures
