Special Issue "New Applications and Architectures Based on FPGA/SoC"

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: 31 January 2020.

Special Issue Editors

Prof. Dr. Ignacio Bravo
E-Mail Website
Guest Editor
Electronics Department, University of Alcala, Madrid 28871, Spain
Interests: smart sensors; FPGAs; embedded design; WSN; data mining
Special Issues and Collections in MDPI journals
Prof. Dr. Alfredo Gardel
E-Mail Website
Guest Editor
Department of Electronics, University of Alcala, Madrid 28871, Spain
Interests: Digital electronic systems; computer vision; IR indoor positioning
Special Issues and Collections in MDPI journals
Prof. Dr. José Luis Lázaro
E-Mail Website
Guest Editor
Department of Electronics, University of Alcala, Madrid 28871, Spain
Interests: local position systems (LPS); infrared sensors; sensors deployment; intelligent spaces; multisensorial data fusion

Special Issue Information

Dear Colleagues,

We are living in a digital world with continuous technological evolution. Within the field of electronic devices, one relevant example is FPGAs (field programmable gate arrays). FPGAs are providing us with new features, optimizing their use in specific scenarios since the beginning of the century. Hardware advantages related to communications, signal and image processing, etc., have been implemented on chips, causing unreliable performance and speed-ups twenty years ago. For this reason, new electronics devices based on FPGAs are very common. One evolution of FPGAs for application to these devices in more and more scenarios, are SoCs (system on chip). These devices combine the benefits of software applications with hardware implementations.

There is still a long path with regard to development tools. It is now possible to connect microprocessors with FPGA resources through SoCs. Thus, advantages from the software environment like operating systems, high level functions or specific drivers to co-work with ad-hoc peripherals can be merged. Also, a new trend concerning FPGA design is developing. There are new tools for designers to accelerate the design time and to take advantage of high-level tools applied to the design of FPGAs/SoCs. This is the case for C2Gates tools that allow us to program these devices in highly abstract languages like C or C++.

The research community is taking advantage of these devices for the development of prototypes or even final products with a high TRL (technology readiness level) with a short design time. Thus, new applications are being implemented and new architectures based on these devices are being developed.

This Special Issue is focused on sharing and showing new designs based on FPGAs and SoCs applying new development tools. The list of topics includes but is not limited to:

  • Using C2Gates tools applied to FPGA/SoC approaches.
  • Applying multiple FPGA/SoC approaches to Big Data applications.
  • Design of new architectures for a specific purpose based on SoC/FPGA solutions.
  • New algorithms based on new FPGA/SoC generations to improve the speed-up of platforms based on non-parallel execution.
  • Analysis and/or comparison of FPGAs, GPUs, Clusters, MPSoCs, etc., for a specific domain.
  • New approaches for software–hardware co-design oriented to the best performance and optimization.
  • Designs based on SoCs working multi-processors with FPGA resources.
  • Hybrid architectures composed with FPGAs applied to real scenarios.

Prof. Dr. Ignacio Bravo
Prof. Dr. Alfredo Gardel
Prof. Dr. José Luis Lázaro
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All papers will be peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Published Papers (9 papers)

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Research

Open AccessArticle
DrawerPipe: A Reconfigurable Pipeline for Network Processing on FPGA-Based SmartNIC
Electronics 2020, 9(1), 59; https://doi.org/10.3390/electronics9010059 - 31 Dec 2019
Abstract
In the public cloud, FPGA-based SmartNICs are widely deployed to accelerate network functions (NFs) for datacenter operators. We argue that with the trend of network as a service (NaaS) in the cloud is also meaningful to accelerate tenant NFs to meet performance requirements. [...] Read more.
In the public cloud, FPGA-based SmartNICs are widely deployed to accelerate network functions (NFs) for datacenter operators. We argue that with the trend of network as a service (NaaS) in the cloud is also meaningful to accelerate tenant NFs to meet performance requirements. However, in pursuit of high performance, existing work such as AccelNet is carefully designed to accelerate specific NFs for datacenter providers, which sacrifices the flexibility of rapidly deploying new NFs. For most tenants with limited hardware design ability, it is time-consuming to develop NFs from scratch due to the lack of a rapidly reconfigurable framework. In this paper, we present a reconfigurable network processing pipeline, i.e., DrawerPipe, which abstracts packet processing into multiple “drawers” connected by the same interface. NF developers can easily share existing modules with other NFs and simply load core application logic in the appropriate “drawer” to implement new NFs. Furthermore, we propose a programmable module indexing mechanism, namely PMI, which can connect “drawers” in any logical order, to perform distinct NFs for different tenants or flows. Finally, we implemented several highly reusable modules for low-level packet processing, and extended four example NFs (firewall, stateful firewall, load balancer, IDS) based on DrawerPipe. Our evaluation shows that DrawerPipe can easily offload customized packet processing to FPGA with high performance up to 100 Mpps and ultra-low latency (<10 µs). Moreover, DrawerPipe enables modular development of NFs, which is suitable for rapid deployment of NFs. Compared with individual NF development, DrawerPipe reduces the line of code (LoC) of the four NFs above by 68%. Full article
(This article belongs to the Special Issue New Applications and Architectures Based on FPGA/SoC)
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Open AccessArticle
Fast Scalable Architecture of a Near-ML Detector for a MIMO-QSM Receiver
Electronics 2019, 8(12), 1509; https://doi.org/10.3390/electronics8121509 - 09 Dec 2019
Abstract
This paper presents a proposal for an architecture in FPGA for the implementation of a low complexity near maximum likelihood (Near-ML) detection algorithm for a multiple input-multiple output (MIMO) quadrature spatial modulation (QSM) transmission system. The proposed low complexity detection algorithm is based [...] Read more.
This paper presents a proposal for an architecture in FPGA for the implementation of a low complexity near maximum likelihood (Near-ML) detection algorithm for a multiple input-multiple output (MIMO) quadrature spatial modulation (QSM) transmission system. The proposed low complexity detection algorithm is based on a tree search and a spherical detection strategy. Our proposal was verified in the context of a MIMO receiver. The effects of the finite length arithmetic and limited precision were evaluated in terms of their impact on the receiver bit error rate (BER). We defined the minimum fixed point word size required not to impact performance adversely for n T transmit antennas and n R receive antennas. The results showed that the proposal performed very near to optimal with the advantage of a meaningful reduction in the complexity of the receiver. The performance analysis of the proposed detector of the MIMO receiver under these conditions showed a strong robustness on the numerical precision, which allowed having a receiver performance very close to that obtained with floating point arithmetic in terms of BER; therefore, we believe this architecture can be an attractive candidate for its implementation in current communications standards. Full article
(This article belongs to the Special Issue New Applications and Architectures Based on FPGA/SoC)
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Open AccessArticle
Memory Optimization for Bit-Vector-Based Packet Classification on FPGA
Electronics 2019, 8(10), 1159; https://doi.org/10.3390/electronics8101159 - 12 Oct 2019
Cited by 1
Abstract
High-performance packet classification algorithms have been widely studied during the past decade. Bit-Vector-based algorithms proposed for FPGA can achieve very high throughput by decomposing rules delicately. However, the relatively large memory resources consumption severely hinders applications of the algorithms extensively. It is noteworthy [...] Read more.
High-performance packet classification algorithms have been widely studied during the past decade. Bit-Vector-based algorithms proposed for FPGA can achieve very high throughput by decomposing rules delicately. However, the relatively large memory resources consumption severely hinders applications of the algorithms extensively. It is noteworthy that, in the Bit-Vector-based algorithms, stringent memory resources in FPGA are wasted to store relatively plenty of useless wildcards in the rules. We thus present a memory-optimized packet classification scheme named WeeBV to eliminate the memory occupied by the wildcards. WeeBV consists of a heterogeneous two-dimensional lookup pipeline and an optimized heuristic algorithm for searching all the wildcard positions that can be removed. It can achieve a significant reduction in memory resources without compromising the high throughput of the original Bit-Vector-based algorithms. We implement WeeBV and evaluate its performance by simulation and FPGA prototype. Experimental results show that our approach can save 37% and 41% memory consumption on average for synthetic 5-tuple rules and OpenFlow rules respectively. Full article
(This article belongs to the Special Issue New Applications and Architectures Based on FPGA/SoC)
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Open AccessArticle
Design and Implementation of CPU & FPGA Co-Design Tester for SDN Switches
Electronics 2019, 8(9), 950; https://doi.org/10.3390/electronics8090950 - 28 Aug 2019
Cited by 2
Abstract
The southbound protocol of Software Defined Networking (SDN) enables the direct access into SDN switches which accelerates the innovation and deployment of network functions in the data plane. Correspondingly, SDN switches that support the new southbound protocol and provide high performance are developed [...] Read more.
The southbound protocol of Software Defined Networking (SDN) enables the direct access into SDN switches which accelerates the innovation and deployment of network functions in the data plane. Correspondingly, SDN switches that support the new southbound protocol and provide high performance are developed continuously. Therefore, there is an increasing need for testing tools to test such equipment in terms of protocol correctness and performance. However, existing tools have deficiencies in flexibility for verifying the novel southbound protocol, time synchronization between the two planes, and supporting more testing functions with less resource consumption. In this paper, we present the concept of CPU & FPGA co-design Tester (CFT) for SDN switches, which provides flexible APIs for test cases of the control plane and high performance for testing functions in the data plane. We put forward an efficient scheduling algorithm to integrate the control plane and the data plane into a single pipeline which fundamentally solves the time asynchronization between these two planes. Due to the reconfigurable feature of our proposed pipeline, it becomes possible to perform different testing functions in one pipeline. Through a prototype implementation and evaluation, we reveal that the proposed CFT can verify the protocol correctness of SDN switches on the control plane while providing no-worse performance for tests on the data plane compared with commercial testers. Full article
(This article belongs to the Special Issue New Applications and Architectures Based on FPGA/SoC)
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Open AccessArticle
SoC Design Based on a FPGA for a Configurable Neural Network Trained by Means of an EKF
Electronics 2019, 8(7), 761; https://doi.org/10.3390/electronics8070761 - 08 Jul 2019
Cited by 5
Abstract
This work presents a configurable architecture for an artificial neural network implemented with a Field Programmable Gate Array (FPGA) in a System on Chip (SoC) environment. This architecture can reproduce the transfer function of different Multilayer Feedforward Neural Network (MFNN) configurations. The functionality [...] Read more.
This work presents a configurable architecture for an artificial neural network implemented with a Field Programmable Gate Array (FPGA) in a System on Chip (SoC) environment. This architecture can reproduce the transfer function of different Multilayer Feedforward Neural Network (MFNN) configurations. The functionality of this configurable architecture relies on a single perceptron, multiplexers, and memory blocks that allow routing, storing, and processing information. The extended Kalman filter is the training algorithm that obtains the optimal weight values for the MFNN. The presented architecture was developed using Verilog Hardware Description Language, which permits designing hardware with a fair number of logical resources, and facilitates the portability to different FPGAs models without compatibility problems. A SoC that mainly incorporates a microprocessor and a FPGA is proposed, where the microprocessor is used for configuring the the MFNN and to enable and disable some functional blocks in the FPGA. The hardware was tested with measurements from a GaN class F power amplifier, using a 2.1 GHz Long Term Evolution signal with 5 MHz of bandwidth. In particular, a special case of an MFNN with two layers, i.e., a real-valued nonlinear autoregressive with an exogenous input neural network, was considered. The results reveal that a normalized mean square error value of −32.82 dB in steady-state was achievable, with a 71.36% generalization using unknown samples. Full article
(This article belongs to the Special Issue New Applications and Architectures Based on FPGA/SoC)
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Open AccessArticle
High-Performance Time Server Core for FPGA System-on-Chip
Electronics 2019, 8(5), 528; https://doi.org/10.3390/electronics8050528 - 11 May 2019
Abstract
This paper presents the complete design and implementation of a low-cost, low-footprint, network time protocol server core for field programmable gate arrays. The core uses a carefully designed modular architecture, which is fully implemented in hardware using digital circuits and systems. Most remarkable [...] Read more.
This paper presents the complete design and implementation of a low-cost, low-footprint, network time protocol server core for field programmable gate arrays. The core uses a carefully designed modular architecture, which is fully implemented in hardware using digital circuits and systems. Most remarkable novelties introduced are a hardware-optimized timekeeping algorithm implementation, and a full-hardware protocol stack and automatic network configuration. As a result, the core is able to achieve similar accuracy and performance to typical high-performance network time protocol server equipment. The core uses a standard global positioning system receiver as time reference, has a small footprint and can easily fit in a low-range field-programmable chip, greatly scaling down from previous system-on-chip time synchronization systems. Accuracy and performance results show that the core can serve hundreds of thousands of network time clients with negligible accuracy degradation, in contrast to state-of-the-art high-performance time server equipment. Therefore, this core provides a valuable time server solution for a wide range of emerging embedded and distributed network applications such as the Internet of Things and the smart grid, at a fraction of the cost and footprint of current discrete and embedded solutions. Full article
(This article belongs to the Special Issue New Applications and Architectures Based on FPGA/SoC)
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Open AccessArticle
Compact Convolutional Neural Network Accelerator for IoT Endpoint SoC
Electronics 2019, 8(5), 497; https://doi.org/10.3390/electronics8050497 - 05 May 2019
Cited by 1
Abstract
As a classical artificial intelligence algorithm, the convolutional neural network (CNN) algorithm plays an important role in image recognition and classification and is gradually being applied in the Internet of Things (IoT) system. A compact CNN accelerator for the IoT endpoint System-on-Chip (SoC) [...] Read more.
As a classical artificial intelligence algorithm, the convolutional neural network (CNN) algorithm plays an important role in image recognition and classification and is gradually being applied in the Internet of Things (IoT) system. A compact CNN accelerator for the IoT endpoint System-on-Chip (SoC) is proposed in this paper to meet the needs of CNN computations. Based on analysis of the CNN structure, basic functional modules of CNN such as convolution circuit and pooling circuit with a low data bandwidth and a smaller area are designed, and an accelerator is constructed in the form of four acceleration chains. After the acceleration unit design is completed, the Cortex-M3 is used to construct a verification SoC and the designed verification platform is implemented on the FPGA to evaluate the resource consumption and performance analysis of the CNN accelerator. The CNN accelerator achieved a throughput of 6.54 GOPS (giga operations per second) by consuming 4901 LUTs without using any hardware multipliers. The comparison shows that the compact accelerator proposed in this paper makes the CNN computational power of the SoC based on the Cortex-M3 kernel two times higher than the quad-core Cortex-A7 SoC and 67% of the computational power of eight-core Cortex-A53 SoC. Full article
(This article belongs to the Special Issue New Applications and Architectures Based on FPGA/SoC)
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Open AccessArticle
An Effective FPGA Solver on Probability Distribution and Preprocessing
Electronics 2019, 8(3), 333; https://doi.org/10.3390/electronics8030333 - 18 Mar 2019
Abstract
The Boolean satisfiability (SAT) problem is the key problem in computer theory and application. A novel algorithm is introduced to implement a SLS hardware solver called probSAT+. The algorithm has no complex heuristic, and it only depends on the concepts of preprocessing technology, [...] Read more.
The Boolean satisfiability (SAT) problem is the key problem in computer theory and application. A novel algorithm is introduced to implement a SLS hardware solver called probSAT+. The algorithm has no complex heuristic, and it only depends on the concepts of preprocessing technology, probability distribution and centralized search. Through constraining the initial assignments of the variables, the number of flipped variables was reduced while the solver finding a solution. Moreover, the algorithm no longer adopts some non-continuous if-then-else decisions, but depends on a single continuous function f(x,v). The flipping probability is not obtained by complex calculations, instead being selected by looking up tables, which effectively improves the performance of the solver. As far as we know, the probability distribution selection strategy descripted by hardware description language is firstly adopted by hardware SAT solver, which can be easily transplanted to any programmable logic device. The experimental results show that the probSAT+ solver is generally lower than the advanced software solver in the number of flips (up to 9.8 × 10 6 ), and the speedup is approximately 2.6 times with single thread, which shows that the probSAT+ has better results with fewer variables flipping times when a solution can be found. In addition, the success ratio of the solver in finding a solution of the problem in a suitable time is 100%. Full article
(This article belongs to the Special Issue New Applications and Architectures Based on FPGA/SoC)
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Open AccessArticle
Hardware RTOS: Custom Scheduler Implementation Based on Multiple Pipeline Registers and MIPS32 Architecture
Electronics 2019, 8(2), 211; https://doi.org/10.3390/electronics8020211 - 14 Feb 2019
Cited by 1
Abstract
The task context switch operation, the inter-task synchronization and communication mechanisms, as well as the jitter occurred in treating aperiodic events, are crucial factors in implementing real-time operating systems (RTOS). In practice and literature, several solutions can be identified for improving the response [...] Read more.
The task context switch operation, the inter-task synchronization and communication mechanisms, as well as the jitter occurred in treating aperiodic events, are crucial factors in implementing real-time operating systems (RTOS). In practice and literature, several solutions can be identified for improving the response speed and performance of real-time systems. Software implementations of RTOS-specific functions can generate significant delays, adversely affecting the deadlines required for certain applications. This paper presents an original implementation of a dedicated processor, based on multiple pipeline registers, and a hardware support for a dynamic scheduler with the following characteristics: performs unitary event management, provides access to architecture shared resources, prioritizes and executes the multiple events expected by the same task. The paper also presents a method through which interrupts are assigned to tasks. Through dedicated instructions, the integrated hardware scheduler implements tasks synchronization with multiple prioritized events, thus ensuring an efficient functioning of the processor in the context of real-time control. Full article
(This article belongs to the Special Issue New Applications and Architectures Based on FPGA/SoC)
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