Analog and Digital Circuit Design Techniques and Systems for Machine Learning

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Artificial Intelligence".

Deadline for manuscript submissions: closed (31 January 2020) | Viewed by 6694

Special Issue Editor

Department of Electrical Engineering, University at Buffalo (State University of New York), Buffalo, NY 14260, USA
Interests: analog/mixed-signal integrated circuits; machine learning; hardware security

Special Issue Information

Dear Colleagues,

In recent years, machine learning has emerged as a ubiquitous tool for analysis of data and providing actionable insights across a wide range of applications from healthcare, automotive, and environmental monitoring to agriculture. While traditionally, machine learning algorithms are designed to run on computers or server nodes in data centers, there is lot of research interest in incorporating machine learning algorithms in embedded systems as well as accelerating machine learning algorithms through better hardware and hardware–software co-design. Applications of embedded systems with machine learning are in edge/sensor nodes, where incorporation of artificial intelligence can reduce transmission bandwidth and improve security while providing inference capability at the sensor node with reduced latency. At the data center end, better hardware designs can improve throughput and reduce energy consumption through novel circuits/architecture/devices beyond conventional computing.

The aim of this Special Issue is to seek high-quality contributions that highlight circuit and system level techniques to improve energy, throughput, and security of machine learning systems for emerging applications. The topics of interest include but are not limited to:

  1. Analog signal processing circuits and algorithms for machine learning applications;
  2. Machine learning circuits for wearable health monitors;
  3. Machine learning architectures and circuits using emerging devices and circuits, e.g., non-volatile memory devices, compute-in-memory, etc.;
  4. Neuromorphic computing, e.g., spiking neural networks;
  5. Advances in system design and machine learning to improve performance and security;
  6. Circuit design for low-cost recurrent neural networks, including echo states.

Dr. Arindam Sanyal
Guest Editor

Manuscript Submission Information

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Keywords

  • circuit design
  • machine learning
  • wearable health monitor
  • neuromorphic computing
  • in-memory computing
  • echo state
  • spiking neural network
  • artificial neural network

Published Papers (2 papers)

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Research

10 pages, 16911 KiB  
Article
A Fully-Integrated Analog Machine Learning Classifier for Breast Cancer Classification
by Sanjeev T. Chandrasekaran, Ruobing Hua, Imon Banerjee and Arindam Sanyal
Electronics 2020, 9(3), 515; https://doi.org/10.3390/electronics9030515 - 20 Mar 2020
Cited by 9 | Viewed by 2949
Abstract
We propose a fully integrated common-source amplifier based analog artificial neural network (ANN). The performance of the proposed ANN with a custom non-linear activation function is demonstrated on the breast cancer classification task. A hardware-software co-design methodology is adopted to ensure good matching [...] Read more.
We propose a fully integrated common-source amplifier based analog artificial neural network (ANN). The performance of the proposed ANN with a custom non-linear activation function is demonstrated on the breast cancer classification task. A hardware-software co-design methodology is adopted to ensure good matching between the software AI model and hardware prototype. A 65 nm prototype of the proposed ANN is fabricated and characterized. The prototype ANN achieves 97% classification accuracy when operating from a 1.1 V supply with an energy consumption of 160 fJ/classification. The prototype consumes 50 μ W power and occupies 0.003 mm 2 die area. Full article
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12 pages, 790 KiB  
Article
Time-Encoding-Based Ultra-Low Power Features Extraction Circuit for Speech Recognition Tasks
by Eric Gutierrez, Carlos Perez, Fernando Hernandez and Luis Hernandez
Electronics 2020, 9(3), 418; https://doi.org/10.3390/electronics9030418 - 29 Feb 2020
Cited by 5 | Viewed by 2770
Abstract
Current trends towards on-edge computing on smart portable devices requires ultra-low power circuits to be able to make feature extraction and classification tasks of patterns. This manuscript proposes a novel approach for feature extraction operations in speech recognition/voice activity detection tasks suitable for [...] Read more.
Current trends towards on-edge computing on smart portable devices requires ultra-low power circuits to be able to make feature extraction and classification tasks of patterns. This manuscript proposes a novel approach for feature extraction operations in speech recognition/voice activity detection tasks suitable for portable devices. Whereas conventional approaches are based on either completely analog or digital structures, we propose a “hybrid” approach by means of voltage-controlled-oscillators. Our proposal makes use of a bank a band-pass filters implemented with ring-oscillators to extract the features (energy within different frequency bands) of input audio signals and digitize them. Afterwards, these data will input a digital classification stage such as a neural network. Ring-oscillators are structures with a digital nature, which makes them highly scalable with the possibility of designing them with minimum length devices. Additionally, due to their inherent phase integration, low-frequency band-pass filters can be implemented without large capacitors. Consequently, we strongly benefit from power consumption and area savings. Finally, our proposal may incorporate the analog-to-digital converter into the structure of the own features extractor circuit to make the full conversion of the raw data when triggered. This supposes a unique advantage with respect to other approaches. The architecture is described and proposed at system-level, along with behavioral simulations made to check whether the performance is the expected one or not. Then the structure is designed with a 65-nm CMOS process to estimate the power consumption and area on a silicon implementation. The results show that our solution is very promising in terms of occupied area with a competitive power consumption in comparison to other state-of-the-art solutions. Full article
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