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Digital and Analog Circuits and Applications Based on TFET Transistors

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A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: closed (31 December 2021) | Viewed by 15068

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Dr. Marco Lanuzza

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Guest Editor

Department of Computer Engineering, Modeling, Electronics and Systems (DIMES), University of Calabria, 87036 Arcavacata, Italy
Interests: ultralow-power CMOS digital and analog design; arithmetic circuits; reconfigurable computing and the design of digital/mixed-signal/analog circuits in emerging technologies
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Dr. Sebastiano Strangio

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Guest Editor

Department of Information Engineering (DII), University of Pisa, 56122 Pisa, Italy
Interests: emerging technologies for ultralow-voltage devices and non-volatile memories; circuits for innovative computing applications; CMOS image sensors
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Special Issue Information

Dear Colleagues,

The steep subthreshold swing of TFETs has been demonstrated by many experimental reports. In the future, TFET transistors may enable the realization of ultralow-power digital and analog functional applications in edge devices, where a limited amount of energy is available to feed electronic circuits. The design of circuits aiming at exploiting the steep turn-on transition of TFETs is currently of great interest. In fact, there is still the need to completely understand the implications of TFET-inherent properties such as the unidirectional conduction, the p-i-n forward biasing issue, and the relatively low current in the ON state. Special topologies and architectures are required to translate TFET performance—demonstrated only at device level to date—to real advantages at system level. The aim of this Special Issue is to collect reports on TFET potentiality to outperform CMOS at low voltages, with an emphasis on TFET circuit topologies for memory cells, digital logic, and analog and mixed-signal architectures. Papers discussing circuit design criteria and strategies to overcome TFET issues are also welcome.

Topics of Interest:

Tunneling Field Effect Transistors (Tunnel FETs, T-FETs);
T-FET circuits for energy efficient computing and information processing;
Energy-Efficient computing and information processing with T-FET transistor circuits and architectures;
TFET-based memories;
Mixed T-FET CMOS designs.

Dr. Marco Lanuzza
Dr. Sebastiano Strangio
Guest Editors

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Published Papers (4 papers)

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Research

12 pages, 2328 KiB

Open AccessArticle

Performance Benchmarking of TFET and FinFET Digital Circuits from a Synthesis-Based Perspective

by Mateo Rendón, Christian Cao, Kevin Landázuri, Esteban Garzón, Luis Miguel Prócel and Ramiro Taco

Electronics 2022, 11(4), 632; https://doi.org/10.3390/electronics11040632 - 18 Feb 2022

Cited by 6 | Viewed by 4091

Abstract

Miniaturization and portable devices have reshaped the electronic device landscape, emphasizing the importance of high performance while maintaining energy efficiency to ensure long battery life. FinFET and Tunnel-FET technologies have emerged as attractive alternatives to overcome the limitations of supply voltage scaling for ultra-low power applications. This work compares the performance of 10 nm FinFET- and TFET-based digital circuits from basic logic gates up to an 8k gates low-power microprocessor. When compared with their FinFET-based counterparts, the TFET-based logic gates have lower leakage power when operated below 300 mV, show higher input capacitance, and exhibit a reduced propagation delay under different fan-in and fan-out conditions. Our comparative study was extended to the synthesis of an MSP-430 microprocessor through standard cell libraries built particularly for this work. It is demonstrated that the TFET-based synthesized circuits operating at ultra-low voltages achieve a higher performance in terms of speed at the cost of increased power consumption. When the speed requirements are relaxed, the TFET-based designs are the most energy-efficient alternative. It is concluded that the TFET is an optimal solution for ultra-low voltage design. Full article

(This article belongs to the Special Issue Digital and Analog Circuits and Applications Based on TFET Transistors)

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14 pages, 3093 KiB

Open AccessFeature PaperArticle

From 32 nm to TFET Technology: New Perspectives for Ultra-Scaled RF-DC Multiplier Circuits

by Lionel Trojman, Eduardo Holguin, Marco Villegas, Luis-Miguel Procel and Ramiro Taco

Electronics 2022, 11(4), 525; https://doi.org/10.3390/electronics11040525 - 10 Feb 2022

Cited by 1 | Viewed by 1906

Abstract

In this present work, different Cross-Coupled Differential Drive (CCDD) CMOS bridge rectifiers are designed using either 32 nm or Tunnel-FET (TFET) technology. Commercial PDK has been used for the 32 nm technology, while lookup tables (LUT) resulting from a physics model have been applied for the TFET. To consider the parasitic effects for the circuit performances, the 32 nm-based circuits have been laid out, while a parasitic model has been included in the TFET LUT for circuit implementation. In this work, the post-layout simulations, including parasitic, demonstrate for conventional CCDD circuits that TFET technology has a larger dynamic range (DR) (>60%) and better 1 V-sensitivity than the 32 nm planar technology has. Note that, in this case, the figure of merit defined by the Voltage Conversion Efficiency (VCE) and Power Conversion Efficiency (PCE) remains somewhat similar. On the other hand, topology proposing better VCE at the cost of low PCE shows lower performance than expected in 32 nm than in reported data for larger technology nodes (e.g., 180 nm). The TFET-based circuit shows a PCE of 70%, VCE of 82% with an 8 dB DR (>60%), and the best 1 V-sensitivity in this work. Because of the low-bias condition and the good reverse current blocking (unidirectional channel), the TFET offers new perspectives for RF-DC rectifier/multiplier topology, which are usually limited with planar technology. Full article

(This article belongs to the Special Issue Digital and Analog Circuits and Applications Based on TFET Transistors)

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11 pages, 951 KiB

Open AccessEditor’s ChoiceArticle

Ultralow Voltage FinFET- Versus TFET-Based STT-MRAM Cells for IoT Applications

by Esteban Garzón, Marco Lanuzza, Ramiro Taco and Sebastiano Strangio

Electronics 2021, 10(15), 1756; https://doi.org/10.3390/electronics10151756 - 22 Jul 2021

Cited by 14 | Viewed by 3912

Abstract

Spin-transfer torque magnetic tunnel junction (STT-MTJ) based on double-barrier magnetic tunnel junction (DMTJ) has shown promising characteristics to define low-power non-volatile memories. This, along with the combination of tunnel FET (TFET) technology, could enable the design of ultralow-power/ultralow-energy STT magnetic RAMs (STT-MRAMs) for future Internet of Things (IoT) applications. This paper presents the comparison between FinFET- and TFET-based STT-MRAM bitcells operating at ultralow voltages. Our study is performed at the bitcell level by considering a DMTJ with two reference layers and exploiting either FinFET or TFET devices as cell selectors. Although ultralow-voltage operation occurs at the expense of reduced reading voltage sensing margins, simulations results show that TFET-based solutions are more resilient to process variations and can operate at ultralow voltages (<0.5

V

), while showing energy savings of 50% and faster write switching of 60%. Full article

(This article belongs to the Special Issue Digital and Analog Circuits and Applications Based on TFET Transistors)

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10 pages, 4306 KiB

Open AccessArticle

Electrostatic Discharge Characteristics of SiGe Source/Drain PNN Tunnel FET

by You Wang, Yu Mao, Qizheng Ji, Ming Yang, Zhaonian Yang and Hai Lin

Electronics 2021, 10(4), 454; https://doi.org/10.3390/electronics10040454 - 11 Feb 2021

Cited by 2 | Viewed by 3064

Abstract

Gate-grounded tunnel field effect transistors (ggTFETs) are considered as basic electrostatic discharge (ESD) protection devices in TFET-integrated circuits. ESD test method of transmission line pulse is used to deeply analyze the current characteristics and working mechanism of Conventional TFET ESD impact. On this basis, a SiGe Source/Drain PNN (P+N+N+) tunnel field effect transistors (TFET) was proposed, which was simulated by Sentaurus technology computer aided design (TCAD) software. Simulation results showed that the trigger voltage of SiGe PNN TFET was 46.3% lower, and the failure current was 13.3% higher than Conventional TFET. After analyzing the simulation results, the parameters of the SiGe PNN TFET were optimized. The single current path of the SiGe PNN TFET was analyzed and explained in the case of gate grounding. Full article

(This article belongs to the Special Issue Digital and Analog Circuits and Applications Based on TFET Transistors)

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