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AI-Enhanced Mixed-Signal Simulation and EDA for Integrated Circuit Design Using...
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AI-Enhanced Mixed-Signal Simulation and EDA for Integrated Circuit Design Using CMOS Technologies

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: 15 October 2026 | Viewed by 3626

Special Issue Editors

Dr. Zhaori Bi

E-Mail Website
Guest Editor
College of Integrated Circuits & Micro-Nano Electronics, Fudan University, Shanghai 201203, China
Interests: fusion circuit design; circuit performance optimization; medical AI applications
Dr. Zhiang Wang

E-Mail Website
Guest Editor
College of Integrated Circuits & Micro-Nano Electronics, Fudan University, Shanghai 201203, China
Interests: physical design; GPU-accelerated EDA; machine learning for EDA
Dr. Keren Zhu

E-Mail Website
Guest Editor
College of Integrated Circuits & Micro-Nano Electronics, Fudan University, Shanghai 201203, China
Interests: custom circuit layout automation; machine learning for EDA; CAD for emerging technologies

Special Issue Information

Dear Colleagues,

The relentless scaling of CMOS technologies and increasing demand for high-performance integrated circuits present formidable challenges in design complexity, verification time, and yield optimization. This Special Issue explores groundbreaking advances in artificial intelligence-driven electronic design automation (EDA) specifically tailored for RF and analog CMOS circuit design, with emphasis on mixed-signal simulation innovations.

We seek contributions addressing the convergence of AI/ML techniques with traditional RF/analog CMOS design methodologies across the following three domains: (1) intelligent mixed-signal simulation frameworks that handle the unique challenges of RF/analog circuits in advanced CMOS nodes; (2) machine learning applications for automated synthesis, optimization, and verification of RF/analog building blocks, such as LNAs, VCOs, PLLs, and data converters; and (3) AI-native EDA solutions that transform conventional IC design flows through predictive modeling and intelligent automation.

Key topics include physics-aware neural networks for IC behavioral modeling, AI-accelerated electromagnetic simulation, machine learning for process variation analysis in CMOS technologies, automated layout generation for analog/RF circuits, intelligent parasitic-aware optimization, and deep learning approaches for signal integrity analysis in mixed-signal systems.

Dr. Zhaori Bi
Dr. Zhiang Wang
Dr. Keren Zhu
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 250 words) can be sent to the Editorial Office for assessment.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • AI-native EDA
  • IC design automation
  • mixed-signal circuit design
  • machine learning for analog/RF design
  • intelligent circuit simulation

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Published Papers (5 papers)

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Research

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26 pages, 646 KB  
Article
An Improved Self-Adaptive Inertial Projection and Contraction Algorithm for Mixed-Cell-Height Circuit Legalization
by Luxin Wang, Chencan Zhou and Qinqin Shen
Electronics 2026, 15(8), 1720; https://doi.org/10.3390/electronics15081720 - 18 Apr 2026
Viewed by 217
Abstract
In advanced technology nodes, mixed-cell-height circuit designs have become increasingly prevalent, posing significant challenges for legalization. We first formulate the legalization as a class of variational inequality (VI) problems defined over convex sets and then employ an existing self-adaptive inertial projection and contraction [...] Read more.
In advanced technology nodes, mixed-cell-height circuit designs have become increasingly prevalent, posing significant challenges for legalization. We first formulate the legalization as a class of variational inequality (VI) problems defined over convex sets and then employ an existing self-adaptive inertial projection and contraction algorithm (SIPCA) to solve it. Building upon this framework, we further propose an improved self-adaptive inertial projection and contraction algorithm (SIPCA_IP) by incorporating the subgradient extragradient technique to enhance convergence efficiency and numerical stability. The proposed method preserves the advantages of projection and contraction schemes for handling VIs with nonsymmetric positive semidefinite system matrices while demonstrating faster convergence and improved robustness compared with the baseline SIPCA. Moreover, a rigorous convergence analysis is established to provide theoretical guarantees for the effectiveness of the proposed method. Numerical experiments demonstrate that the proposed method effectively addresses the mixed-cell-height legalization problem and provides a rigorous and extensible framework for solving related quadratic optimization problems. Full article
(This article belongs to the Special Issue AI-Enhanced Mixed-Signal Simulation and EDA for Integrated Circuit Design Using CMOS Technologies)
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20 pages, 1575 KB  
Article
Topology-Aware Admission Control for Dynamic Load Balancing in NUMA-Based Parallel RTL Simulation
by Xin Huang, Guangrong Li, Fan Yang and Zhaori Bi
Electronics 2026, 15(8), 1672; https://doi.org/10.3390/electronics15081672 - 16 Apr 2026
Viewed by 332
Abstract
Parallel discrete-event simulation (PDES) of register-transfer-level (RTL) designs on multi-socket NUMA platforms demand dynamic load balancing to mitigate barrier-induced tail latency. However, the ultra-fine event granularity of RTL simulation makes migration cost non-negligible, and the non-uniform memory hierarchy of NUMA turns migration cost [...] Read more.
Parallel discrete-event simulation (PDES) of register-transfer-level (RTL) designs on multi-socket NUMA platforms demand dynamic load balancing to mitigate barrier-induced tail latency. However, the ultra-fine event granularity of RTL simulation makes migration cost non-negligible, and the non-uniform memory hierarchy of NUMA turns migration cost into a topology-dependent variable rather than a constant. Existing approaches either ignore this topology dependence or rely on heuristic thresholds that lack theoretical justification. This paper formulates NUMA-aware dynamic load balancing as a constrained optimization problem in which the migration cost is an explicit function of the socket locality between the source and destination cores. We introduce a unified net benefit function G(m,i→j,f) that jointly captures the tail-latency reduction, migration overhead, and cache warm-up penalty for migrating module m from core i to core j at frequency f. We prove that G is jointly concave in migration scale and frequency, yielding two analytical results: (i) a closed-form admission inequality that prescribes when migration is strictly beneficial, and (ii) a conservative fixed-frequency design rule that guides the choice of a global epoch length for the proposed epoch-based controller. We further show that when the initial static partition satisfies a bounded-quality condition, the total migration volume is provably bounded, formalizing the intuition that restraint is optimal, not merely conservative. We implement the proposed topology-aware admission control (TAC) framework in TACVS (Topology-Aware Admission Control Verilog Simulator), our event-driven parallel RTL simulation prototype. Experiments on four open-source RTL designs running on a 2-socket NUMA platform show that TAC reduces the tail-latency ratio by 18.0% on average (up to 28.5%) and improves normalized throughput by 27.1% on average (up to 34.1%) relative to topology-oblivious baselines. An ablation study further shows that admission control and cooldown are critical for performance, with throughput dropping by 15.9% and 22.8% on average (up to 22.4% and 32.5%) when each is removed, respectively. Full article
(This article belongs to the Special Issue AI-Enhanced Mixed-Signal Simulation and EDA for Integrated Circuit Design Using CMOS Technologies)
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21 pages, 667 KB  
Article
CSF: Fixed-Outline Floorplanning Based on the Conjugate Subgradient Algorithm and Assisted by Q-Learning
by Xinyan Meng, Huabin Cheng, Yu Chen, Jianguo Hu and Ning Xu
Electronics 2025, 14(24), 4893; https://doi.org/10.3390/electronics14244893 - 12 Dec 2025
Viewed by 532
Abstract
Analytical floorplanning algorithms are prone to local convergence and struggle to generate high-quality results; therefore, this paper proposes a nonsmooth analytical placement model and develops a Q-learning-assisted conjugate subgradient algorithm (CSAQ) for efficient floorplanning that addresses these issues. By integrating a population-based strategy [...] Read more.
Analytical floorplanning algorithms are prone to local convergence and struggle to generate high-quality results; therefore, this paper proposes a nonsmooth analytical placement model and develops a Q-learning-assisted conjugate subgradient algorithm (CSAQ) for efficient floorplanning that addresses these issues. By integrating a population-based strategy and an adaptive step size adjustment driven by Q-learning, the CSAQ strikes a balance between exploration and exploitation to avoid suboptimal solutions in fixed-outline floorplanning scenarios. Experimental results on the MCNC and GSRC benchmarks demonstrate that the proposed CSAQ not only effectively solves global placement planning problems but also significantly outperforms existing constraint graph-based legalization methods, as well as the improved variants, in terms of the efficiency of generating legal floorplans. For hard module-only placement scenarios, it exhibits competitive performance compared to the state-of-the-art algorithms. Full article
(This article belongs to the Special Issue AI-Enhanced Mixed-Signal Simulation and EDA for Integrated Circuit Design Using CMOS Technologies)
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18 pages, 776 KB  
Article
A Hybrid Neural Network for Efficient Rectilinear Steiner Minimum Tree Construction
by Zhigang Li, Xinxin Zhang, Zhiwei Tan, Chunyu Peng, Xiulong Wu and Ming Zhu
Electronics 2025, 14(19), 3931; https://doi.org/10.3390/electronics14193931 - 3 Oct 2025
Viewed by 1354
Abstract
Efficient routing optimization remains a pivotal challenge in Electronic Design Automation (EDA), as it profoundly influences circuit performance, power consumption, and manufacturing cost. The Rectilinear Steiner Minimum Tree (RSMT) problem plays a crucial role in this process by minimizing the routing length through [...] Read more.
Efficient routing optimization remains a pivotal challenge in Electronic Design Automation (EDA), as it profoundly influences circuit performance, power consumption, and manufacturing cost. The Rectilinear Steiner Minimum Tree (RSMT) problem plays a crucial role in this process by minimizing the routing length through the introduction of Steiner points. This paper proposes a reinforcement learning-driven RSMT construction model that incorporates a novel Selective Kernel Transformer Network (SKTNet) encoder to enhance feature representation. SKTNet integrates a Selective Kernel Convolution (SKConv) and an improved Macaron Transformer to improve multi-scale feature extraction and global topology modeling. Additionally, Self-Critical Sequence Training (SCST) is employed to optimize the policy by leveraging a greedy-decoded baseline sequence for the advantage computation. Experimental results demonstrate superior performance over state-of-the-art methods in wirelength optimization. Ablation studies further validate the contribution of this model, highlighting its effectiveness and scalability for routing. Full article
(This article belongs to the Special Issue AI-Enhanced Mixed-Signal Simulation and EDA for Integrated Circuit Design Using CMOS Technologies)
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Review

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24 pages, 18960 KB  
Review
A Systematic Taxonomy and Comparative Analysis of Mixed-Signal Simulation Methods: From Classical SPICE to AI-Enhanced Approaches
by Jian Yu, Hairui Zhu, Jiawen Yuan and Lei Jiang
Electronics 2026, 15(8), 1687; https://doi.org/10.3390/electronics15081687 - 16 Apr 2026
Viewed by 428
Abstract
Mixed-signal simulation is indispensable for verifying modern integrated circuits that tightly couple analog and digital subsystems, yet the field lacks a unified framework for systematically comparing its diverse methodologies. This paper addresses that gap by proposing a novel three-axis taxonomy that classifies simulation [...] Read more.
Mixed-signal simulation is indispensable for verifying modern integrated circuits that tightly couple analog and digital subsystems, yet the field lacks a unified framework for systematically comparing its diverse methodologies. This paper addresses that gap by proposing a novel three-axis taxonomy that classifies simulation methods along abstraction level, solver methodology, and analysis type, together with a comparative evaluation framework based on five quantitative metrics: accuracy, throughput, capacity, convergence reliability, and scalability. Applying this framework, we systematically compare thirteen classical method categories—spanning SPICE, FastSPICE, RF/periodic steady-state, behavioral modeling, co-simulation, and model order reduction—and eight AI/ML approaches including Gaussian process surrogates, graph neural networks, physics-informed neural networks, Bayesian optimization, and reinforcement learning. Our analysis reveals a clear maturity stratification: classical methods remain the only signoff-accurate approaches, Bayesian optimization represents the most industrially validated AI contribution with integration across all three major EDA platforms, while Neural ODE solvers and LLM-based design tools remain at the research stage. We identify a persistent academic-to-industry gap driven by foundry model complexity, limited benchmark diversity, and topology-specific overfitting. The proposed taxonomy and comparative framework provide practitioners with structured guidance for simulation method selection and highlight specific research directions needed to bridge the gap between AI promise and industrial deployment. Full article
(This article belongs to the Special Issue AI-Enhanced Mixed-Signal Simulation and EDA for Integrated Circuit Design Using CMOS Technologies)
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