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AI-Enhanced Mixed-Signal Simulation and EDA for Integrated Circuit Design Using...
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AI-Enhanced Mixed-Signal Simulation and EDA for Integrated Circuit Design Using CMOS Technologies

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: 15 March 2026 | Viewed by 1199

Special Issue Editors

Dr. Zhaori Bi

E-Mail Website
Guest Editor
College of Integrated Circuits & Micro-Nano Electronics, Fudan University, Shanghai 201203, China
Interests: fusion circuit design; circuit performance optimization; medical AI applications
Dr. Zhiang Wang

E-Mail Website
Guest Editor
College of Integrated Circuits & Micro-Nano Electronics, Fudan University, Shanghai 201203, China
Interests: physical design; GPU-accelerated EDA; machine learning for EDA
Dr. Keren Zhu

E-Mail Website
Guest Editor
College of Integrated Circuits & Micro-Nano Electronics, Fudan University, Shanghai 201203, China
Interests: custom circuit layout automation; machine learning for EDA; CAD for emerging technologies

Special Issue Information

Dear Colleagues,

The relentless scaling of CMOS technologies and increasing demand for high-performance integrated circuits present formidable challenges in design complexity, verification time, and yield optimization. This Special Issue explores groundbreaking advances in artificial intelligence-driven electronic design automation (EDA) specifically tailored for RF and analog CMOS circuit design, with emphasis on mixed-signal simulation innovations.

We seek contributions addressing the convergence of AI/ML techniques with traditional RF/analog CMOS design methodologies across the following three domains: (1) intelligent mixed-signal simulation frameworks that handle the unique challenges of RF/analog circuits in advanced CMOS nodes; (2) machine learning applications for automated synthesis, optimization, and verification of RF/analog building blocks, such as LNAs, VCOs, PLLs, and data converters; and (3) AI-native EDA solutions that transform conventional IC design flows through predictive modeling and intelligent automation.

Key topics include physics-aware neural networks for IC behavioral modeling, AI-accelerated electromagnetic simulation, machine learning for process variation analysis in CMOS technologies, automated layout generation for analog/RF circuits, intelligent parasitic-aware optimization, and deep learning approaches for signal integrity analysis in mixed-signal systems.

Dr. Zhaori Bi
Dr. Zhiang Wang
Dr. Keren Zhu
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 250 words) can be sent to the Editorial Office for assessment.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • AI-native EDA
  • IC design automation
  • mixed-signal circuit design
  • machine learning for analog/RF design
  • intelligent circuit simulation

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Published Papers (2 papers)

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Research

21 pages, 667 KB  
Article
CSF: Fixed-Outline Floorplanning Based on the Conjugate Subgradient Algorithm and Assisted by Q-Learning
by Xinyan Meng, Huabin Cheng, Yu Chen, Jianguo Hu and Ning Xu
Electronics 2025, 14(24), 4893; https://doi.org/10.3390/electronics14244893 - 12 Dec 2025
Viewed by 126
Abstract
Analytical floorplanning algorithms are prone to local convergence and struggle to generate high-quality results; therefore, this paper proposes a nonsmooth analytical placement model and develops a Q-learning-assisted conjugate subgradient algorithm (CSAQ) for efficient floorplanning that addresses these issues. By integrating a population-based strategy [...] Read more.
Analytical floorplanning algorithms are prone to local convergence and struggle to generate high-quality results; therefore, this paper proposes a nonsmooth analytical placement model and develops a Q-learning-assisted conjugate subgradient algorithm (CSAQ) for efficient floorplanning that addresses these issues. By integrating a population-based strategy and an adaptive step size adjustment driven by Q-learning, the CSAQ strikes a balance between exploration and exploitation to avoid suboptimal solutions in fixed-outline floorplanning scenarios. Experimental results on the MCNC and GSRC benchmarks demonstrate that the proposed CSAQ not only effectively solves global placement planning problems but also significantly outperforms existing constraint graph-based legalization methods, as well as the improved variants, in terms of the efficiency of generating legal floorplans. For hard module-only placement scenarios, it exhibits competitive performance compared to the state-of-the-art algorithms. Full article
(This article belongs to the Special Issue AI-Enhanced Mixed-Signal Simulation and EDA for Integrated Circuit Design Using CMOS Technologies)
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18 pages, 776 KB  
Article
A Hybrid Neural Network for Efficient Rectilinear Steiner Minimum Tree Construction
by Zhigang Li, Xinxin Zhang, Zhiwei Tan, Chunyu Peng, Xiulong Wu and Ming Zhu
Electronics 2025, 14(19), 3931; https://doi.org/10.3390/electronics14193931 - 3 Oct 2025
Viewed by 676
Abstract
Efficient routing optimization remains a pivotal challenge in Electronic Design Automation (EDA), as it profoundly influences circuit performance, power consumption, and manufacturing cost. The Rectilinear Steiner Minimum Tree (RSMT) problem plays a crucial role in this process by minimizing the routing length through [...] Read more.
Efficient routing optimization remains a pivotal challenge in Electronic Design Automation (EDA), as it profoundly influences circuit performance, power consumption, and manufacturing cost. The Rectilinear Steiner Minimum Tree (RSMT) problem plays a crucial role in this process by minimizing the routing length through the introduction of Steiner points. This paper proposes a reinforcement learning-driven RSMT construction model that incorporates a novel Selective Kernel Transformer Network (SKTNet) encoder to enhance feature representation. SKTNet integrates a Selective Kernel Convolution (SKConv) and an improved Macaron Transformer to improve multi-scale feature extraction and global topology modeling. Additionally, Self-Critical Sequence Training (SCST) is employed to optimize the policy by leveraging a greedy-decoded baseline sequence for the advantage computation. Experimental results demonstrate superior performance over state-of-the-art methods in wirelength optimization. Ablation studies further validate the contribution of this model, highlighting its effectiveness and scalability for routing. Full article
(This article belongs to the Special Issue AI-Enhanced Mixed-Signal Simulation and EDA for Integrated Circuit Design Using CMOS Technologies)
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