Special Issue "Modeling and Design of Integrated CMOS Circuit"

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Microelectronics".

Deadline for manuscript submissions: 31 October 2021.

Special Issue Editors

Dr. Laurent Artola
E-Mail Website
Guest Editor
Department of Physics Instrumentation Environment and Space (ONERA/DPHY), Université de Toulouse, F-31055 Toulouse, France
Interests: electronic reliability; single event effects; radiation effects; semiconductor device; modelling
Special Issues and Collections in MDPI journals
Prof. Dr. Ricardo Reis
E-Mail Website
Guest Editor
Instituto de Informática of the Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, Brazil
Interests: microelectronics; electronic design automation; physical design; VLSI design; design of circuits tolerant to radiation effects; systems on chip

Special Issue Information

Dear Colleagues,

One of the main challenges for the electronic research field is to cope with the rapidly progressing technology which, today, reaches the nanometer scale and ultra-low voltages. The areas of interest of this Special Issue include the modeling and design of innovative chips and embedded systems. Emerging technologies have raised relevant topics related to performances, power, and reliability that to need to be investigated.

The topics of this Special Issue are dedicated but not limited to the following:

System-on-a-chip;

multiprocessor systems;

network-on-a-chip;

low-voltage and low-power systems;

Internet of Things sensor;

analog–digital convertor/digital–analog converter;

clock network;

emerging type of memories;

CMOS image sensors

Dr. Laurent Artola
Prof. Dr. Ricardo Reis
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All papers will be peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1800 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Semiconductor Device
  • Innovative design
  • Simulation
  • Reliability
  • Low-power voltage

Published Papers (2 papers)

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Research

Article
Runtime Analysis of Area-Efficient Uniform RO-PUF for Uniqueness and Reliability Balancing
Electronics 2021, 10(20), 2504; https://doi.org/10.3390/electronics10202504 - 14 Oct 2021
Viewed by 168
Abstract
The main issue of ring oscillator physical unclonable functions (RO-PUF) is the existence of unstable ROs in response to environmental variations. The RO pairs with close frequency differences tend to contribute bit flips, reducing the reliability. Research on improving reliability has been carried [...] Read more.
The main issue of ring oscillator physical unclonable functions (RO-PUF) is the existence of unstable ROs in response to environmental variations. The RO pairs with close frequency differences tend to contribute bit flips, reducing the reliability. Research on improving reliability has been carried out over the years. However, it has led to other issues, such as decreasing the uniqueness and increasing the area utilized. Therefore, this paper proposes a uniform RO-PUF, requiring a smaller area than a conventional design, aiming to balance reliability and uniqueness. We analyzed RO runtimes to increase reliability. In general, our method (uniqueness = 47.48%, reliability = 99.16%) performs better than previously proposed methods for a similar platform (Altera), and the reliability is as good as the latest methods using the same IC technology (28 nm). Moreover, the reliability is higher than that of RO-PUF with challenge and response pair (CRP) enhancements. The evaluation was performed in longer runtimes, where the pulses produced by ROs exceeded the counter capacity. This work recommends choosing ranges of the runtime of RO for better performance. For the 11-stage ROs, the range should be 1.598–4.30 ms, or 6.12–8.61 ms, or 12.24–12.91 ms. Meanwhile, for the 20-stage, the range should be 2.717–8.37 ms, or 10.97–16.74 ms, or 21.93–25.10 ms. Full article
(This article belongs to the Special Issue Modeling and Design of Integrated CMOS Circuit)
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Article
Pre-Emphasis Pulse Design for Random-Access Memory
Electronics 2021, 10(12), 1454; https://doi.org/10.3390/electronics10121454 - 17 Jun 2021
Viewed by 373
Abstract
This paper describes how one can reduce the memory access time with pre-emphasis (PE) pulses even in non-volatile random-access memory. Optimum PE pulse widths and resultant minimum word-line (WL) delay times are investigated as a function of column address. The impact of the [...] Read more.
This paper describes how one can reduce the memory access time with pre-emphasis (PE) pulses even in non-volatile random-access memory. Optimum PE pulse widths and resultant minimum word-line (WL) delay times are investigated as a function of column address. The impact of the process variation in the time constant of WL, the cell current, and the resistance of deciding path on optimum PE pulses are discussed. Optimum PE pulse widths and resultant minimum WL delay times are modeled with fitting curves as a function of column address of the accessed memory cell, which provides designers with the ability to set the optimum timing for WL and BL (bit-line) operations, reducing average memory access time. Full article
(This article belongs to the Special Issue Modeling and Design of Integrated CMOS Circuit)
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