Special Issue "Recent Advances in Field-Programmable Logic and Applications"

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Microelectronics".

Deadline for manuscript submissions: closed (30 October 2020).

Special Issue Editor

Prof. Dr. João Canas Ferreira
E-Mail Website
Guest Editor
INESC TEC and Faculty of Engineering of the University of Porto, 4200-465 Porto, Portugal
Interests: reconfigurable computing; hardware accelerators; power-aware embedded computing platforms; application-specific digital systems; hardware DSP for telecommunications
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Special Issue Information

Dear Colleagues,

The end of Dennard scaling and Moore’s law has led to the rise of heterogeneous systems, which, in combination with the emergence of very active fields like Machine Learning and Big Data Analytics, have extraordinarily broadened the potential applicability of field-programmable logic. Reconfigurable platforms can now be employed over an impressive range of applications that goes from smart, self-adaptive embedded systems near the edge of the cloud to the data centers at its core, and includes the communication links in between. In this challenging environment, field-programmable logic enables new tradeoffs between performance, power efficiency, security, flexibility and dependability. Simultaneously, device architectures and development tools have been evolving to meet the new challenges.

This special issue will bring together high-quality contributions that highlight novel approaches and recent breakthroughs in all areas related to programmable logic (technology, architectures, EDA tools and methodologies) as well as emerging application domains ranging from embedded systems up to data centers. The topics covered by the Special Issue include, but are not limited to, the following: 

  • Device technology for field-programmable logic: programmable memories interconnect devices, circuits and switches, and emerging technologies.
  • Reconfigurable heterogeneous platforms: FPGA/PMPSoC and CGRA architectures; overlays; hardware acceleration frameworks.
  • Programmable logic in the data center: CPU/FPGA communication; memory interfaces; FPGA virtualization; operating system services.
  • Design methodologies and tools: high-level synthesis, hardware/software co-design; debugging and profiling; programming languages and frameworks; modelling and validation techniques; binary compilation.
  • Dynamic reconfiguration: tools and techniques; run-time reconfigurable processor architectures; evolvable hardware and adaptive computing.
  • High performance applications: machine learning, large-scale data analytics, stream processing, database acceleration, machine vision, graphics, cryptography, robotics, and manufacturing systems.
  • Reconfigurable heterogeneous hardware for security applications: IP protection, certification and validation of configuration information, protection against side-channel attacks.  

Prof. Dr. João Canas Ferreira
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All papers will be peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1800 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Reconfigurable computing technology
  • FPGA/PMPSoC architectures
  • Hardware accelerators
  • Heterogeneous reconfigurable platform architectures
  • CAD and High-level synthesis tools and methodologies for reconfigurable platforms
  • Dynamic reconfiguration
  • Domain-specific reconfigurable computing
  • Programmable logic in the data center and big data analytics
  • Programmable logic for machine learning in embedded and HPC systems
  • Security of reconfigurable platforms

Published Papers (6 papers)

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Research

Article
Transparent Control Flow Transfer between CPU and Accelerators for HPC
Electronics 2021, 10(4), 406; https://doi.org/10.3390/electronics10040406 - 07 Feb 2021
Viewed by 561
Abstract
Heterogeneous platforms with FPGAs have started to be employed in the High-Performance Computing (HPC) field to improve performance and overall efficiency. These platforms allow the use of specialized hardware to accelerate software applications, but require the software to be adapted in what can [...] Read more.
Heterogeneous platforms with FPGAs have started to be employed in the High-Performance Computing (HPC) field to improve performance and overall efficiency. These platforms allow the use of specialized hardware to accelerate software applications, but require the software to be adapted in what can be a prolonged and complex process. The main goal of this work is to describe and evaluate mechanisms that can transparently transfer the control flow between CPU and FPGA within the scope of HPC. Combining such a mechanism with transparent software profiling and accelerator configuration could lead to an automatic way of accelerating regular applications. In this work, a mechanism based on the ptrace system call is proposed, and its performance on the Intel Xeon+FPGA platform is evaluated. The feasibility of the proposed approach is demonstrated by a working prototype that performs the transparent control flow transfer of any function call to a matching hardware accelerator. This approach is more general than shared library interposition at the cost of a small time overhead in each accelerator use (about 1.3 ms in the prototype implementation). Full article
(This article belongs to the Special Issue Recent Advances in Field-Programmable Logic and Applications)
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Article
SW-VHDL Co-Verification Environment Using Open Source Tools
Electronics 2020, 9(12), 2104; https://doi.org/10.3390/electronics9122104 - 10 Dec 2020
Viewed by 570
Abstract
The verification of complex digital designs often involves the use of expensive simulators. The present paper proposes an approach to verify a specific family of complex hardware/software systems, whose hardware part, running on an FPGA, communicates with a software counterpart executed on an [...] Read more.
The verification of complex digital designs often involves the use of expensive simulators. The present paper proposes an approach to verify a specific family of complex hardware/software systems, whose hardware part, running on an FPGA, communicates with a software counterpart executed on an external processor, such as a user/operator software running on an external PC. The hardware is described in VHDL and the software may be described in any computer language that can be interpreted or compiled into a (Linux) executable file. The presented approach uses open source tools, avoiding expensive license costs and usage restrictions. Full article
(This article belongs to the Special Issue Recent Advances in Field-Programmable Logic and Applications)
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Article
FPGA-Based Solution for On-Board Verification of Hardware Modules Using HLS
Electronics 2020, 9(12), 2024; https://doi.org/10.3390/electronics9122024 - 30 Nov 2020
Viewed by 640
Abstract
High-Level Synthesis (HLS) tools provide facilities for the development of specialized hardware accelerators (HWacc). However, the verification stage is still the longest phase in the development life-cycle. Unlike in the software industry, HLS tools lack testing frameworks that could cover the whole design [...] Read more.
High-Level Synthesis (HLS) tools provide facilities for the development of specialized hardware accelerators (HWacc). However, the verification stage is still the longest phase in the development life-cycle. Unlike in the software industry, HLS tools lack testing frameworks that could cover the whole design flow, especially the on-board verification stage of the generated RTL. This work introduces a framework for on-board verification of HLS-based modules by using reconfigurable systems and Docker containers with the aim to automate the verification process and preserve a clean testing environment, making the testbed reusable across different stages of the design flow. Moreover, our solution features a mechanism to check timing requirements of the HWacc. We have applied our solution to the C-kernels of the CHStone Benchmark on a Zedboard, in which the on-board verification process has been accelerated up to four times. Full article
(This article belongs to the Special Issue Recent Advances in Field-Programmable Logic and Applications)
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Article
Exploration of FPGA-Based Hardware Designs for QR Decomposition for Solving Stiff ODE Numerical Methods Using the HARP Hybrid Architecture
Electronics 2020, 9(5), 843; https://doi.org/10.3390/electronics9050843 - 19 May 2020
Viewed by 1091
Abstract
In this article, we focus on the acceleration of a chemical reaction simulation that relies on a system of stiff ordinary differential equation (ODEs) targeting heterogeneous computing systems with CPUs and field-programmable gate arrays (FPGAs). Specifically, we target an essential kernel of the [...] Read more.
In this article, we focus on the acceleration of a chemical reaction simulation that relies on a system of stiff ordinary differential equation (ODEs) targeting heterogeneous computing systems with CPUs and field-programmable gate arrays (FPGAs). Specifically, we target an essential kernel of the coupled chemistry aerosol-tracer transport model to the Brazilian developments on the regional atmospheric modeling system (CCATT-BRAMS). We focus on a linear solve step using the QR factorization based on the modified Gram-Schmidt method as the basis of the ODE solver in this application. We target Intel hardware accelerator research program (HARP) architecture with the OpenCL programming environment for these early experiments. Our design exploration reveals a hardware design that is up to 4 times faster than the original iterative Jacobi method used in this solver. Still, even with hardware support, the overall performance of our QR-based hardware is lower than its original software version. Full article
(This article belongs to the Special Issue Recent Advances in Field-Programmable Logic and Applications)
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Article
A Parallel Connected Component Labeling Architecture for Heterogeneous Systems-on-Chip
Electronics 2020, 9(2), 292; https://doi.org/10.3390/electronics9020292 - 08 Feb 2020
Cited by 2 | Viewed by 991
Abstract
Connected component labeling is one of the most important processes for image analysis, image understanding, pattern recognition, and computer vision. It performs inherently sequential operations to scan a binary input image and to assign a unique label to all pixels of each object. [...] Read more.
Connected component labeling is one of the most important processes for image analysis, image understanding, pattern recognition, and computer vision. It performs inherently sequential operations to scan a binary input image and to assign a unique label to all pixels of each object. This paper presents a novel hardware-oriented labeling approach able to process input pixels in parallel, thus speeding up the labeling task with respect to state-of-the-art competitors. For purposes of comparison with existing designs, several hardware implementations are characterized for different image sizes and realization platforms. The obtained results demonstrate that frame rates and resource efficiency significantly higher than existing counterparts are achieved. The proposed hardware architecture is purposely designed to comply with the fourth generation of the advanced extensible interface (AXI4) protocol and to store intermediate and final outputs within an off-chip memory. Therefore, it can be directly integrated as a custom accelerator in virtually any modern heterogeneous embedded system-on-chip (SoC). As an example, when integrated within the Xilinx Zynq-7000 X C7Z020 SoC, the novel design processes more than 1.9 pixels per clock cycle, thus furnishing more than 30 2k × 2k labeled frames per second by using 3688 Look-Up Tables (LUTs), 1415 Flip Flops (FFs), and 10 kb of on-chip memory. Full article
(This article belongs to the Special Issue Recent Advances in Field-Programmable Logic and Applications)
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Article
Quantitative Analysis of Multistage Switching Networks for Embedded Programmable Devices
Electronics 2019, 8(3), 272; https://doi.org/10.3390/electronics8030272 - 01 Mar 2019
Cited by 3 | Viewed by 1380
Abstract
This paper analyzes the properties of a class of congestion-free multistage switching networks (MSSNs) are butterfly-based and suitable for embedded programmable devices, which require sustaining static multicast connectivity. These MSSNs are fully synthesizable and enable the design of programmable IPs with typical size [...] Read more.
This paper analyzes the properties of a class of congestion-free multistage switching networks (MSSNs) are butterfly-based and suitable for embedded programmable devices, which require sustaining static multicast connectivity. These MSSNs are fully synthesizable and enable the design of programmable IPs with typical size in the order of 1 KLUT, coupling flexibility with fast turn-around time. The non-blocking property for static connection of this class of MSSN is discussed. Our analysis shows pros and cons of adopting radix-2 or radix-4 MSSN structures, as well as the impact of bypass-paths to make the network fully hierarchical and locality-aware thanks also to a dedicated programming strategy. Implementation experiments carried out on STM CMOS 65 nm technology show the availability of various area-speed trade-offs, resulting in a range of ≃2× in frequency and a range of ≃ 4 × in area. Depending on the specific application-field, an optimal interconnect definition is thus achieved without compromising the routability properties. In this respect, the paper proposes a simplified application-driven model for evaluation of the best MSSN, including bypass-adoption and radix selection. Full article
(This article belongs to the Special Issue Recent Advances in Field-Programmable Logic and Applications)
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