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Article

A Parallel Connected Component Labeling Architecture for Heterogeneous Systems-on-Chip

1
Department of Mechanical, Energy and Management Engineering, University of Calabria, 87036 Arcavacata di Rende, Italy
2
Department of Informatics, Modeling, Electronics and System Engineering, University of Calabria, 87036 Arcavacata di Rende, Italy
*
Author to whom correspondence should be addressed.
Electronics 2020, 9(2), 292; https://doi.org/10.3390/electronics9020292
Received: 20 December 2019 / Revised: 4 February 2020 / Accepted: 6 February 2020 / Published: 8 February 2020
(This article belongs to the Special Issue Recent Advances in Field-Programmable Logic and Applications)
Connected component labeling is one of the most important processes for image analysis, image understanding, pattern recognition, and computer vision. It performs inherently sequential operations to scan a binary input image and to assign a unique label to all pixels of each object. This paper presents a novel hardware-oriented labeling approach able to process input pixels in parallel, thus speeding up the labeling task with respect to state-of-the-art competitors. For purposes of comparison with existing designs, several hardware implementations are characterized for different image sizes and realization platforms. The obtained results demonstrate that frame rates and resource efficiency significantly higher than existing counterparts are achieved. The proposed hardware architecture is purposely designed to comply with the fourth generation of the advanced extensible interface (AXI4) protocol and to store intermediate and final outputs within an off-chip memory. Therefore, it can be directly integrated as a custom accelerator in virtually any modern heterogeneous embedded system-on-chip (SoC). As an example, when integrated within the Xilinx Zynq-7000 X C7Z020 SoC, the novel design processes more than 1.9 pixels per clock cycle, thus furnishing more than 30 2k × 2k labeled frames per second by using 3688 Look-Up Tables (LUTs), 1415 Flip Flops (FFs), and 10 kb of on-chip memory. View Full-Text
Keywords: connected component labeling; hardware accelerator; heterogeneous SoC; Filed Programmable Gate Arrays (FPGAs) connected component labeling; hardware accelerator; heterogeneous SoC; Filed Programmable Gate Arrays (FPGAs)
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MDPI and ACS Style

Perri, S.; Spagnolo, F.; Corsonello, P. A Parallel Connected Component Labeling Architecture for Heterogeneous Systems-on-Chip. Electronics 2020, 9, 292. https://doi.org/10.3390/electronics9020292

AMA Style

Perri S, Spagnolo F, Corsonello P. A Parallel Connected Component Labeling Architecture for Heterogeneous Systems-on-Chip. Electronics. 2020; 9(2):292. https://doi.org/10.3390/electronics9020292

Chicago/Turabian Style

Perri, Stefania, Fanny Spagnolo, and Pasquale Corsonello. 2020. "A Parallel Connected Component Labeling Architecture for Heterogeneous Systems-on-Chip" Electronics 9, no. 2: 292. https://doi.org/10.3390/electronics9020292

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