Special Issue "FPGA and Reconfigurable Computing"

A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: closed (31 December 2017) | Viewed by 6825

Special Issue Editor

Prof. Dr. João Canas Ferreira
E-Mail Website
Guest Editor
INESC TEC and Faculty of Engineering of the University of Porto, 4200-465 Porto, Portugal
Interests: reconfigurable computing; hardware accelerators; power-aware embedded computing platforms; application-specific digital systems; hardware DSP for telecommunications
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Special Issue Information

Dear Colleagues,

The pervasive use of electronics in many areas of human activity (personal, professional and social) has led to a remarkable expansion of the scope and importance of power- or energy-constrained computing environments. This has happened in traditional areas like telecommunications and health care, but also in new areas like well-being, gaming and leisure. Energy, power and thermal constraints have a large impact on the design of ever more complex adaptive embedded and cyber-physical systems in these domains. The challenges created by this trend are being met in part by flexible heterogeneous and reconfigurable computing platforms in order to achieve new levels of power or energy efficiency while processing growing amounts of data with increasingly sophisticated algorithms. In this context, specialized accelerators and dynamically reconfigurable hardware have also been finding increasing application. This Special Issue of the JLPEA is dedicated to advances in all aspects of low-power reconfigurable computing from new reconfigurable fabrics in emerging technologies up to system-level monitoring and run-time management infrastructures, including new circuits and architectures for FPGAs and CGRAs, reconfigurable hardware accelerators and new applications of dynamic reconfiguration. Original contributions from the following non-exhaustive list of topics are solicited: 

  • emerging low-power technologies and circuits for reconfigurable computing;
  • (non-volatile) memory technologies for configuration storage;
  • nanoscale reconfigurable computing platforms;
  • low-power FPGA or CGRA circuits and architectures;
  • reconfigurable low-power hardware accelerators;
  • dynamic reconfiguration for low-power: methodologies, system architectures and algorithms;
  • EDA tools and algorithms for low-power FPGA or CGRA systems;
  • run-time support systems for power-aware reconfiguration management;
  • power- or energy-constrained applications of reconfigurable computing. 

Prof. Dr. João Canas Ferreira
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1600 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • low-power FPGA and CGRA architectures
  • dynamic reconfiguration for low-power
  • nanoscale reconfigurable fabrics
  • power-constrained run-time reconfiguration management
  • heterogeneous reconfigurable systems

Published Papers (1 paper)

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Research

Article
Energy-Efficient FPGA-Based Parallel Quasi-Stochastic Computing
J. Low Power Electron. Appl. 2017, 7(4), 29; https://doi.org/10.3390/jlpea7040029 - 17 Nov 2017
Cited by 6 | Viewed by 6512
Abstract
The high performance of FPGA (Field Programmable Gate Array) in image processing applications is justified by its flexible reconfigurability, its inherent parallel nature and the availability of a large amount of internal memories. Lately, the Stochastic Computing (SC) paradigm has been found to [...] Read more.
The high performance of FPGA (Field Programmable Gate Array) in image processing applications is justified by its flexible reconfigurability, its inherent parallel nature and the availability of a large amount of internal memories. Lately, the Stochastic Computing (SC) paradigm has been found to be significantly advantageous in certain application domains including image processing because of its lower hardware complexity and power consumption. However, its viability is deemed to be limited due to its serial bitstream processing and excessive run-time requirement for convergence. To address these issues, a novel approach is proposed in this work where an energy-efficient implementation of SC is accomplished by introducing fast-converging Quasi-Stochastic Number Generators (QSNGs) and parallel stochastic bitstream processing, which are well suited to leverage FPGA’s reconfigurability and abundant internal memory resources. The proposed approach has been tested on the Virtex-4 FPGA, and results have been compared with the serial and parallel implementations of conventional stochastic computation using the well-known SC edge detection and multiplication circuits. Results prove that by using this approach, execution time, as well as the power consumption are decreased by a factor of 3.5 and 4.5 for the edge detection circuit and multiplication circuit, respectively. Full article
(This article belongs to the Special Issue FPGA and Reconfigurable Computing)
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