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Article

Transparent Control Flow Transfer between CPU and Accelerators for HPC

INESC TEC and Faculty of Engineering, University of Porto, 4200-465 Porto, Portugal
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Academic Editor: Akash Kumar
Electronics 2021, 10(4), 406; https://doi.org/10.3390/electronics10040406
Received: 7 January 2021 / Revised: 30 January 2021 / Accepted: 2 February 2021 / Published: 7 February 2021
(This article belongs to the Special Issue Recent Advances in Field-Programmable Logic and Applications)
Heterogeneous platforms with FPGAs have started to be employed in the High-Performance Computing (HPC) field to improve performance and overall efficiency. These platforms allow the use of specialized hardware to accelerate software applications, but require the software to be adapted in what can be a prolonged and complex process. The main goal of this work is to describe and evaluate mechanisms that can transparently transfer the control flow between CPU and FPGA within the scope of HPC. Combining such a mechanism with transparent software profiling and accelerator configuration could lead to an automatic way of accelerating regular applications. In this work, a mechanism based on the ptrace system call is proposed, and its performance on the Intel Xeon+FPGA platform is evaluated. The feasibility of the proposed approach is demonstrated by a working prototype that performs the transparent control flow transfer of any function call to a matching hardware accelerator. This approach is more general than shared library interposition at the cost of a small time overhead in each accelerator use (about 1.3 ms in the prototype implementation). View Full-Text
Keywords: heterogeneous computing; reconfigurable computing; transparent acceleration; FPGA; HPC heterogeneous computing; reconfigurable computing; transparent acceleration; FPGA; HPC
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MDPI and ACS Style

Granhão, D.; Canas Ferreira, J. Transparent Control Flow Transfer between CPU and Accelerators for HPC. Electronics 2021, 10, 406. https://doi.org/10.3390/electronics10040406

AMA Style

Granhão D, Canas Ferreira J. Transparent Control Flow Transfer between CPU and Accelerators for HPC. Electronics. 2021; 10(4):406. https://doi.org/10.3390/electronics10040406

Chicago/Turabian Style

Granhão, Daniel, and João Canas Ferreira. 2021. "Transparent Control Flow Transfer between CPU and Accelerators for HPC" Electronics 10, no. 4: 406. https://doi.org/10.3390/electronics10040406

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