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Electronics
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Electrical Characterization, Modeling and Simulation of CMOS Memory Devices
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Electrical Characterization, Modeling and Simulation of CMOS Memory Devices

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: closed (1 April 2022) | Viewed by 19462

Special Issue Editor

Prof. Dr. Gino Giusi

E-Mail Website
Guest Editor
Department of Engineering, University of Messina, 98166 Messina, Italy
Interests: experimental methods, characterization, modeling and simulation of electronic devices

Special Issue Information

Dear Colleagues,

The memory systems of modern digital devices are increasingly becoming the center of attention for the research community and the semiconductor industry. On one hand, it is necessary to push forward with the development of new technologies for the digital devices of the future, like MRAMs, STT-RAMs and PCRAMs. On the other hand, it is necessary to consolidate the current technology through the search for new materials and architectures compatible with the current CMOS process in order to guarantee the integration of logic and memory in the same chip. In this context, this Special Issue aims to present studies on new materials and architectures for memory devices, conducted using methods of electrical characterization, modeling and device simulation and focused on consolidated themes such as non-volatile NAND flash and discrete-trap memories. Fully compatible technological options for the near future, such as resistive RAM memories, one-transistor (1T) and MIMCAP based DRAMs, will also be considered.

Prof. Dr. Gino Giusi
Guest Editor

Manuscript Submission Information

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Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • CMOS memory devices
  • modeling and numerical simulation
  • electrical material and devices characterization
  • device fabrication
  • bi-dimensional materials
  • One Transistor (1T) DRAMs
  • Metal-Insulator-Metal Capacitors (MIMCAPs)
  • Resistive Memories (Re-RAMs)
  • NAND Flash Memories
  • discrete traps memories

Published Papers (6 papers)

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Research

17 pages, 1393 KiB  
Article
Read Reference Calibration and Tracking for Non-Volatile Flash Memories
by Johann-Philipp Thiers, Daniel Nicolas Bailon, Jürgen Freudenberger and Jianjie Lu
Electronics 2021, 10(18), 2306; https://doi.org/10.3390/electronics10182306 - 19 Sep 2021
Cited by 4 | Viewed by 2370
Abstract
The performance and reliability of nonvolatile NAND flash memories deteriorate as the number of program/erase cycles grows. The reliability also suffers from cell-to-cell interference, long data retention time, and read disturb. These processes effect the read threshold voltages. The aging of the cells [...] Read more.
The performance and reliability of nonvolatile NAND flash memories deteriorate as the number of program/erase cycles grows. The reliability also suffers from cell-to-cell interference, long data retention time, and read disturb. These processes effect the read threshold voltages. The aging of the cells causes voltage shifts which lead to high bit error rates (BER) with fixed predefined read thresholds. This work proposes two methods that aim on minimizing the BER by adjusting the read thresholds. Both methods utilize the number of errors detected in the codeword of an error correction code. It is demonstrated that the observed number of errors is a good measure for the voltage shifts and is utilized for the initial calibration of the read thresholds. The second approach is a gradual channel estimation method that utilizes the asymmetrical error probabilities for the one-to-zero and zero-to-one errors that are caused by threshold calibration errors. Both methods are investigated utilizing the mutual information between the optimal read voltage and the measured error values. Numerical results obtained from flash measurements show that these methods reduce the BER of NAND flash memories significantly. Full article
(This article belongs to the Special Issue Electrical Characterization, Modeling and Simulation of CMOS Memory Devices)
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12 pages, 4296 KiB  
Article
Floating Body DRAM with Body Raised and Source/Drain Separation
by Gino Giusi
Electronics 2021, 10(6), 706; https://doi.org/10.3390/electronics10060706 - 17 Mar 2021
Cited by 2 | Viewed by 2053
Abstract
One-Transistor (1T) DRAMs are one of the potential replacements for conventional 1T-1C dynamic memory cells for future scaling of embedded and stand-alone memory architectures. In this work, a scaled (channel length 10nm) floating body 1T memory device architecture with ultra-thin body is studied, [...] Read more.
One-Transistor (1T) DRAMs are one of the potential replacements for conventional 1T-1C dynamic memory cells for future scaling of embedded and stand-alone memory architectures. In this work, a scaled (channel length 10nm) floating body 1T memory device architecture with ultra-thin body is studied, which uses a combined approach of a body raised storage region and separated source/drain regions having the role to reduce thermal and field enhanced band-to-band recombination. The physical mechanisms along the geometry and bias scaling are discussed in order to address the requirements of embedded or stand-alone applications. Two-dimensional device simulations show that, with proper optimization of the geometry and bias, the combined approach allows the increase of the retention time and of the programming window by more than one order of magnitude. Full article
(This article belongs to the Special Issue Electrical Characterization, Modeling and Simulation of CMOS Memory Devices)
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14 pages, 6746 KiB  
Article
Influence of Common Source and Word Line Electrodes on Program Operation in SuperFlash Memory
by Ivan Mazzetta and Fernanda Irrera
Electronics 2021, 10(3), 337; https://doi.org/10.3390/electronics10030337 - 1 Feb 2021
Cited by 1 | Viewed by 2490
Abstract
A theoretical study of the influence of word line and common source electrodes on the program operation in shrank SuperFlash memory is proposed. Numerical simulations demonstrate that the literature model defined for previous nodes is not always suitable, due to the continuous cell [...] Read more.
A theoretical study of the influence of word line and common source electrodes on the program operation in shrank SuperFlash memory is proposed. Numerical simulations demonstrate that the literature model defined for previous nodes is not always suitable, due to the continuous cell physical size reduction and to the consequent increment of capacitive coupling between the floating gate and adjacent electrodes. To get a deeper insight, an analytical model of the electric field in the region of source side injection is proposed. This model describes the impact of the cell physical and electrical parameters on the vertical and horizontal field components and highlights the strong dependence of the carrier injection on the technology node. Furthermore, the numerical and analytical models estimate the influence of the word line and common source electrodes on the time-to-program, the floating gate potential and the source side injection efficiency, taking into consideration, at the same time, their possible impact on the cell reliability. Full article
(This article belongs to the Special Issue Electrical Characterization, Modeling and Simulation of CMOS Memory Devices)
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11 pages, 1833 KiB  
Article
Analysis of State-of-the-Art Spin-Transfer-Torque Nonvolatile Flip-Flops Considering Restore Yield in the Near/Sub-Threshold Voltage Region
by Gwang Hui Choi and Taehui Na
Electronics 2020, 9(12), 2118; https://doi.org/10.3390/electronics9122118 - 11 Dec 2020
Cited by 1 | Viewed by 2003
Abstract
Recently, the leakage power consumption of Internet of Things (IoT) devices has become a main issue to be tackled, due to the fact that the scaling of process technology increases the leakage current in the IoT devices having limited battery capacity, resulting in [...] Read more.
Recently, the leakage power consumption of Internet of Things (IoT) devices has become a main issue to be tackled, due to the fact that the scaling of process technology increases the leakage current in the IoT devices having limited battery capacity, resulting in the reduction of battery lifetime. The most effective method to extend the battery lifetime is to shut-off the device during standby mode. For this reason, spin-transfer-torque magnetic-tunnel-junction (STT-MTJ) based nonvolatile flip-flop (NVFF) is being considered as a strong candidate to store the computing data. Since there is a risk that the MTJ resistance may change during the read operation (i.e., the read disturbance problem), NVFF should consider the read disturbance problem to satisfy reliable data restoration. To date, several NVFFs have been proposed. Even though they satisfy the target restore yield of 4σ, most of them do not take the read disturbance into account. Furthermore, several recently proposed NVFFs which focus on the offset-cancellation technique to improve the restore yield have obvious limitation with decreasing the supply voltage (VDD), because the offset-cancellation technique uses switch operation in the critical path that can exacerbate the restore yield in the near/sub-threshold region. In this regard, this paper analyzes state-of-the-art STT-MTJ based NVFFs with respect to the voltage region and provides insight that a simple circuit having no offset-cancellation technique could achieve a better restore yield in the near/sub-threshold voltage region. Monte–Carlo HSPICE simulation results, using industry-compatible 28 nm model parameters, show that in case of VDD of 0.6 V, complex NVFF circuits having offset tolerance characteristic have a better restore yield, whereas in case of VDD of 0.4 V with sizing up strategy, a simple NVFF circuit having no offset tolerance characteristic has a better restore yield. Full article
(This article belongs to the Special Issue Electrical Characterization, Modeling and Simulation of CMOS Memory Devices)
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14 pages, 8578 KiB  
Article
Partial Isolation Type Buried Channel Array Transistor (Pi-BCAT) for a Sub-20 nm DRAM Cell Transistor
by Jin-sung Lee, Jin-hyo Park, Geon Kim, Hyun Duck Choi and Myoung Jin Lee
Electronics 2020, 9(11), 1908; https://doi.org/10.3390/electronics9111908 - 13 Nov 2020
Cited by 5 | Viewed by 5171
Abstract
In this paper, we propose a new buried channel array transistor structure to solve the problem of current leakage occurring in the capacitors of dynamic random-access memory (DRAM) cells. This structure has a superior off current performance compared with three previous types of [...] Read more.
In this paper, we propose a new buried channel array transistor structure to solve the problem of current leakage occurring in the capacitors of dynamic random-access memory (DRAM) cells. This structure has a superior off current performance compared with three previous types of structures. In particular, the proposed buried channel array transistor has a 43% lower off current than the conventional asymmetric doping structure. Here, we show the range of the effective buried insulator parameter according to the depth of the buried gate, and we effectively show the range of improvement for the off current. Full article
(This article belongs to the Special Issue Electrical Characterization, Modeling and Simulation of CMOS Memory Devices)
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10 pages, 6949 KiB  
Article
Robust Offset-Cancellation Sense Amplifier for an Offset-Canceling Dual-Stage Sensing Circuit in Resistive Nonvolatile Memories
by Taehui Na
Electronics 2020, 9(9), 1403; https://doi.org/10.3390/electronics9091403 - 30 Aug 2020
Cited by 6 | Viewed by 4316
Abstract
With technology scaling, achieving a target read yield of resistive nonvolatile memories becomes more difficult due to increased process variation and decreased supply voltage. Recently, an offset-canceling dual-stage sensing circuit (OCDS-SC) has been proposed to improve the read yield by canceling the offset [...] Read more.
With technology scaling, achieving a target read yield of resistive nonvolatile memories becomes more difficult due to increased process variation and decreased supply voltage. Recently, an offset-canceling dual-stage sensing circuit (OCDS-SC) has been proposed to improve the read yield by canceling the offset voltage and utilizing a double-sensing-margin structure. In this paper, an offset-canceling zero-sensing-dead-zone sense amplifier (OCZS-SA) combined with the OCDS-SC is proposed to significantly improve the read yield. The OCZS-SA has two major advantages, namely, offset voltage cancellation and a zero sensing dead zone. The Monte Carlo HSPICE simulation results using a 65-nm predictive technology model show that the OCZS-SA achieves 2.1 times smaller offset voltage with a zero sensing dead zone than the conventional latch-type SAs at the cost of an increased area overhead of 1.0% for a subarray size of 128 × 16. Full article
(This article belongs to the Special Issue Electrical Characterization, Modeling and Simulation of CMOS Memory Devices)
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