System-on-Chip (SoC) and Field-Programmable Gate Array (FPGA) Design, 2nd Edition

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: 15 May 2026 | Viewed by 442

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Guest Editor
Department of Electronics, Information and Bioengineering, Politecnico di Milano, 20133 Milano, Italy
Interests: digital electronic; time-to-digital converter; digital-to-time converter; field programmable gate array; system-on-chip
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Dear Colleagues,

The evolution of digital technology is firmly steered by key concepts such as field-programmable gate arrays (FPGAs) and the evolution of system-on-chip (SoC). These pivotal elements seamlessly integrate programmable logic, creating a potent synergy that manifests in spatial and temporal computing. While SoCs stand as a milestone in technological evolution, incorporating processors and reconfigurable logic areas, FPGAs emerge as fundamental devices for the rapid development of complex digital circuits. Together, SoCs and FPGAs create an ecosystem that not only accelerates the time to market but also opens the doors to a new computing paradigm, where flexibility and spatial–temporal optimization are at the forefront of digital innovation. The significance of these FPGA and SoC architectures extends beyond mere computing power, influencing the design of advanced devices in sectors such as artificial intelligence, the Internet of Things, and robotics, radically transforming how we interact with technology in our daily lives.

Prof. Dr. Nicola Lusardi
Guest Editor

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Keywords

  • system-on-chip (SoC)
  • field-programmable gate arrays (FPGAs)
  • real-time processing
  • programmable temporal computing
  • programmable parallel computing
  • time mode

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Research

23 pages, 5413 KB  
Article
Hardware/Software Partitioning Based on Area and Memory Metrics: Application to a Fuzzy Controller Algorithm for a DC Motor
by Diego Hernán Gaytán Rivas, Jorge Rivera and Susana Ortega-Cisneros
Electronics 2025, 14(24), 4908; https://doi.org/10.3390/electronics14244908 - 13 Dec 2025
Viewed by 181
Abstract
In hardware/software (HW/SW) partitioning, the most commonly established objectives are execution time, power consumption, and hardware area. Surprisingly, memory usage, a critical resource in embedded systems, has received limited attention as a primary optimization objective. Moreover, the few studies that consider memory rarely [...] Read more.
In hardware/software (HW/SW) partitioning, the most commonly established objectives are execution time, power consumption, and hardware area. Surprisingly, memory usage, a critical resource in embedded systems, has received limited attention as a primary optimization objective. Moreover, the few studies that consider memory rarely provide an explicit, design-time estimation method. This work proposes a methodology for obtaining memory usage as a design metric, along with an objective function tailored to evaluate memory usage in systems-on-chip featuring a hard processor core and a Field-Programmable Gate Array suitable for a HW/SW partitioning problem. To validate the proposed methodology, HW/SW partitioning was carried out for a PD-type fuzzy control algorithm targeting a DC motor. The optimization problem was solved using the Non-dominated Sorting Genetic Algorithm II. The results demonstrate the feasibility and accuracy of the proposed approach, achieving more than 97.5% accuracy in predicting memory and hardware resource consumption. Additionally, the functional performance of the selected partition configuration was validated in real-time, where the tracking of different reference signals for the velocity of the motor was successfully achieved. Full article
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