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System-on-Chip (SoC) and Field-Programmable Gate Array (FPGA) Design, 2nd Edition
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System-on-Chip (SoC) and Field-Programmable Gate Array (FPGA) Design, 2nd Edition

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: 20 December 2026 | Viewed by 3012

Editor

Prof. Dr. Nicola Lusardi

E-Mail Website
Guest Editor
Department of Electronics, Information and Bioengineering, Politecnico di Milano, 20133 Milano, Italy
Interests: digital electronic; time-to-digital converter; digital-to-time converter; field programmable gate array; system-on-chip
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

The evolution of digital technology is firmly steered by key concepts such as field-programmable gate arrays (FPGAs) and the evolution of system-on-chip (SoC). These pivotal elements seamlessly integrate programmable logic, creating a potent synergy that manifests in spatial and temporal computing. While SoCs stand as a milestone in technological evolution, incorporating processors and reconfigurable logic areas, FPGAs emerge as fundamental devices for the rapid development of complex digital circuits. Together, SoCs and FPGAs create an ecosystem that not only accelerates the time to market but also opens the doors to a new computing paradigm, where flexibility and spatial–temporal optimization are at the forefront of digital innovation. The significance of these FPGA and SoC architectures extends beyond mere computing power, influencing the design of advanced devices in sectors such as artificial intelligence, the Internet of Things, and robotics, radically transforming how we interact with technology in our daily lives.

Prof. Dr. Nicola Lusardi
Guest Editor

Manuscript Submission Information

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Keywords

  • system-on-chip (SoC)
  • field-programmable gate arrays (FPGAs)
  • real-time processing
  • programmable temporal computing
  • programmable parallel computing
  • time mode

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Related Special Issue

Published Papers (3 papers)

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Research

26 pages, 3845 KB  
Article
On the Edge-Computing-Oriented Inference of Radial Basis Function-Based Kolmogorov–Arnold Networks
by Georgios Venitourakis, Ioannis Koutoulas, Konstantina Sofia Charalampeli, Maria Eleni Patsi, Christoforos Kachris and Dionysios Reisis
Electronics 2026, 15(12), 2498; https://doi.org/10.3390/electronics15122498 - 6 Jun 2026
Viewed by 423
Abstract
The emerging Kolmogorov–Arnold networks (KANs) have set a new standard in machine learning (ML) tasks by prevailing over traditionally deployed multilayer perceptrons (MLPs) thanks to their enhanced interpretability through activation function learning, while they require increased computational complexity and memory footprint. Radial-basis function [...] Read more.
The emerging Kolmogorov–Arnold networks (KANs) have set a new standard in machine learning (ML) tasks by prevailing over traditionally deployed multilayer perceptrons (MLPs) thanks to their enhanced interpretability through activation function learning, while they require increased computational complexity and memory footprint. Radial-basis function (RBF)-based KAN models maintain high performance over other variants of KANs with considerable size reduction and consequently more efficient execution. Aiming at effectively supporting the inference of RBF-KANs on Internet-of-Things (IoT) devices, this paper focuses on edge-oriented computing and introduces a soft intellectual property (IP) core, written in hardware description language (HDL), targeting the execution of such networks on all-programmable systems-on-chip (APSoC). The proposed design is fully pipelined and runtime configurable, allowing for real-time inference and latency-sensitive neural network deployment on-the-fly. A testbench reveals up to 43.6× speedup when compared with a commercial edge central processing unit (CPU) and consumes considerably less power. The core’s adaptable design enables efficient allocation of resources and meets diverse throughput demands, making it well-suited for a broad range of IoT applications. Full article
(This article belongs to the Special Issue System-on-Chip (SoC) and Field-Programmable Gate Array (FPGA) Design, 2nd Edition)
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19 pages, 1607 KB  
Article
Real-Time Bird Audio Detection with a CNN-RNN Model on a SoC-FPGA
by Rodrigo Lopes da Silva, Gustavo Jacinto, Mário Véstias and Rui Policarpo Duarte
Electronics 2026, 15(2), 354; https://doi.org/10.3390/electronics15020354 - 13 Jan 2026
Viewed by 1313
Abstract
Monitoring wildlife has become increasingly important for understanding the evolution of species and ecosystem health. Acoustic monitoring offers several advantages over video-based approaches, enabling continuous 24/7 observation and robust detection under challenging environmental conditions. Deep learning models have demonstrated strong performance in audio [...] Read more.
Monitoring wildlife has become increasingly important for understanding the evolution of species and ecosystem health. Acoustic monitoring offers several advantages over video-based approaches, enabling continuous 24/7 observation and robust detection under challenging environmental conditions. Deep learning models have demonstrated strong performance in audio classification. However, their computational complexity poses significant challenges for deployment on low-power embedded platforms. This paper presents a low-power embedded system for real-time bird audio detection. A hybrid CNN–RNN architecture is adopted, redesigned, and quantized to significantly reduce model complexity while preserving classification accuracy. To support efficient execution, a custom hardware accelerator was developed and integrated into a Zynq UltraScale+ ZU3CG FPGA. The proposed system achieves an accuracy of 87.4%, processes up to 5 audio samples per second, and operates at only 1.4 W, demonstrating its suitability for autonomous, energy-efficient wildlife monitoring applications. Full article
(This article belongs to the Special Issue System-on-Chip (SoC) and Field-Programmable Gate Array (FPGA) Design, 2nd Edition)
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23 pages, 5413 KB  
Article
Hardware/Software Partitioning Based on Area and Memory Metrics: Application to a Fuzzy Controller Algorithm for a DC Motor
by Diego Hernán Gaytán Rivas, Jorge Rivera and Susana Ortega-Cisneros
Electronics 2025, 14(24), 4908; https://doi.org/10.3390/electronics14244908 - 13 Dec 2025
Viewed by 661
Abstract
In hardware/software (HW/SW) partitioning, the most commonly established objectives are execution time, power consumption, and hardware area. Surprisingly, memory usage, a critical resource in embedded systems, has received limited attention as a primary optimization objective. Moreover, the few studies that consider memory rarely [...] Read more.
In hardware/software (HW/SW) partitioning, the most commonly established objectives are execution time, power consumption, and hardware area. Surprisingly, memory usage, a critical resource in embedded systems, has received limited attention as a primary optimization objective. Moreover, the few studies that consider memory rarely provide an explicit, design-time estimation method. This work proposes a methodology for obtaining memory usage as a design metric, along with an objective function tailored to evaluate memory usage in systems-on-chip featuring a hard processor core and a Field-Programmable Gate Array suitable for a HW/SW partitioning problem. To validate the proposed methodology, HW/SW partitioning was carried out for a PD-type fuzzy control algorithm targeting a DC motor. The optimization problem was solved using the Non-dominated Sorting Genetic Algorithm II. The results demonstrate the feasibility and accuracy of the proposed approach, achieving more than 97.5% accuracy in predicting memory and hardware resource consumption. Additionally, the functional performance of the selected partition configuration was validated in real-time, where the tracking of different reference signals for the velocity of the motor was successfully achieved. Full article
(This article belongs to the Special Issue System-on-Chip (SoC) and Field-Programmable Gate Array (FPGA) Design, 2nd Edition)
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