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J. Low Power Electron. Appl., Volume 9, Issue 1 (March 2019)

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Open AccessArticle A 50.5 ns Wake-Up-Latency 11.2 pJ/Inst Asynchronous Wake-Up Controller in FDSOI 28 nm
J. Low Power Electron. Appl. 2019, 9(1), 8; https://doi.org/10.3390/jlpea9010008
Received: 7 December 2018 / Revised: 6 February 2019 / Accepted: 7 February 2019 / Published: 14 February 2019
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Abstract
Due to low activity in Internet of Things (IoT) applications, systems tend to leverage low power modes in order to reduce their power consumption. Normally-off computing thus arose, consisting in having turned off most part of a system’s power supply, while dynamically turning [...] Read more.
Due to low activity in Internet of Things (IoT) applications, systems tend to leverage low power modes in order to reduce their power consumption. Normally-off computing thus arose, consisting in having turned off most part of a system’s power supply, while dynamically turning on components as the application needs it. As wake up sources may be diverse, simple controllers are integrated to handle smart wake up schemes. Therefore, to prevent overconsumption while transitioning to running mode, fast wake up sequences are required. An asynchronous 16-bit Reduced Instruction Set Computer (RISC) Wake-up Controller (WuC) is proposed demonstrating 50.5 [email protected] Million Instructions Per Second (MIPS)@0.6 V wake-up latency, drastically reducing the overall wake-up energy of IoT systems. A clockless implementation of the controller saves the booting time and the power consumption of a clock generator, while providing high robustness to environmental variations such as supply voltage level. The WuC is also able to run simple tasks with a reduced Instruction Set Architecture (ISA) and achieves as low as 11.2 pJ/inst @0.5 V in Fully Depleted Silicon On Insulator (FDSOI) 28 nm. Full article
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Open AccessArticle DoS Attack Detection and Path Collision Localization in NoC-Based MPSoC Architectures
J. Low Power Electron. Appl. 2019, 9(1), 7; https://doi.org/10.3390/jlpea9010007
Received: 27 November 2018 / Revised: 31 January 2019 / Accepted: 1 February 2019 / Published: 5 February 2019
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Abstract
Denial of Service (DoS) attacks are an increasing threat for Multiprocessor System-on-Chip (MPSoC) architectures. By exploiting the shared resources on the chip, an attacker is able to prevent completion or degrade the performance of a task. This is extremely dangerous for MPSoCs used [...] Read more.
Denial of Service (DoS) attacks are an increasing threat for Multiprocessor System-on-Chip (MPSoC) architectures. By exploiting the shared resources on the chip, an attacker is able to prevent completion or degrade the performance of a task. This is extremely dangerous for MPSoCs used in critical applications. The Network-on-Chip (NoC), as a central MPSoC infrastructure, is exposed to this attack. In order to maintain communication availability, NoCs should be enhanced with an effective and precise attack detection mechanism that allows the triggering of effective attack mitigation mechanisms. Previous research works demonstrate DoS attacks on NoCs and propose detection methods being implemented in NoC routers. These countermeasures typically led to a significantly increased router complexity and to a high degradation of the MPSoC’s performance. To this end, we present two contributions. First, we provide an analysis of information that helps to narrow down the location of the attacker in the MPSoC, achieving up to a 69% search space reduction for locating the attacker. Second, we propose a low cost mechanism for detecting the location and direction of the interference, by enhancing the communication packet structure and placing communication degradation monitors in the NoC routers. Our experiments show that our NoC router architecture detects single-source DoS attacks and determines, with high precision, the location and direction of the collision, while incurring a low area and power overhead. Full article
(This article belongs to the Special Issue Emerging Interconnection Networks Across Scales)
Open AccessArticle High Level Current Modeling for Shaping Electromagnetic Emissions in Micropipeline Circuits
J. Low Power Electron. Appl. 2019, 9(1), 6; https://doi.org/10.3390/jlpea9010006
Received: 30 November 2018 / Revised: 23 January 2019 / Accepted: 25 January 2019 / Published: 29 January 2019
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Abstract
In order to fit circuit electromagnetic emissions within a spectral mask, a design flow based on high level current modeling for micropipeline circuits is proposed. The model produces a quick and rough estimation of the circuit current, thanks to a Timed Petri Net [...] Read more.
In order to fit circuit electromagnetic emissions within a spectral mask, a design flow based on high level current modeling for micropipeline circuits is proposed. The model produces a quick and rough estimation of the circuit current, thanks to a Timed Petri Net determining the activation instants of the different micropipeline stages and an asymmetric Laplace distribution modeling the current peaks of the activated stages. The design flow exploits this current estimation for shaping the electromagnetic emissions by setting the controller delays of the micropipeline circuits. The delay adjustment is performed by a genetic algorithm, which iterates until the electromagnetic emissions match the targeted spectral mask. In order to evaluate the technique, an Advanced Encryption Standard (AES) circuit has been designed. We first observed that the obtained current curve fits well with a gate simulation. Then, after shaping the electromagnetic emissions, the simulation shows that the spectrum fits within the spectral mask. Full article
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Open AccessArticle Power and Area Efficient Clock Stretching and Critical Path Reshaping for Error Resilience
J. Low Power Electron. Appl. 2019, 9(1), 5; https://doi.org/10.3390/jlpea9010005
Received: 28 December 2018 / Revised: 15 January 2019 / Accepted: 18 January 2019 / Published: 21 January 2019
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Abstract
Energy efficient semiconductor chips are in high demand to cater the needs of today’s smart products. Advanced technology nodes insert high design margins to deal with rising variations at the cost of power, area and performance. Existing run time resilience techniques are not [...] Read more.
Energy efficient semiconductor chips are in high demand to cater the needs of today’s smart products. Advanced technology nodes insert high design margins to deal with rising variations at the cost of power, area and performance. Existing run time resilience techniques are not cost effective due to the additional circuits involved. In this paper, we propose a design time resilience technique using a clock stretched flip-flop to redistribute the available slack in the processor pipeline to the critical paths. We use the opportunistic slack to redesign the critical fan in logic using logic reshaping, better than worst case sigma corner libraries and multi-bit flip-flops to achieve power and area savings. Experimental results prove that we can tune the logic and the library to get significant power and area savings of 69% and 15% in the execute pipeline stage of the processor compared to the traditional worst-case design. Whereas, existing run time resilience hardware results in 36% and 2% power and area overhead respectively. Full article
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Open AccessArticle Analog Architecture Complexity Theory Empowering Ultra-Low Power Configurable Analog and Mixed Mode SoC Systems
J. Low Power Electron. Appl. 2019, 9(1), 4; https://doi.org/10.3390/jlpea9010004
Received: 1 October 2018 / Revised: 21 November 2018 / Accepted: 7 December 2018 / Published: 21 January 2019
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Abstract
This discussion develops a theoretical analog architecture framework similar to the well developed digital architecture theory. Designing analog systems, whether small or large scale, must optimize their architectures for energy consumption. As in digital systems, a strong architecture theory, based on experimental results, [...] Read more.
This discussion develops a theoretical analog architecture framework similar to the well developed digital architecture theory. Designing analog systems, whether small or large scale, must optimize their architectures for energy consumption. As in digital systems, a strong architecture theory, based on experimental results, is essential for these opportunities. The recent availability of programmable and configurable analog technologies, as well as the start of analog numerical analysis, makes considering scaling of analog computation more than a purely theoretical interest. Although some aspects nicely parallel digital architecture concepts, analog architecture theory requires revisiting some of the foundations of parallel digital architectures, particularly revisiting structures where communication and memory access, instead of processor operations, that dominates complexity. This discussion shows multiple system examples from Analog-to-Digital Converters (ADC) to Vector-Matrix Multiplication (VMM), adaptive filters, image processing, sorting, and other computing directions. Full article
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Open AccessArticle A New Multi-Bit Flip-Flop Merging Mechanism for Power Consumption Reduction in the Physical Implementation Stage of ICs Conception
J. Low Power Electron. Appl. 2019, 9(1), 3; https://doi.org/10.3390/jlpea9010003
Received: 13 November 2018 / Revised: 3 January 2019 / Accepted: 4 January 2019 / Published: 21 January 2019
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Abstract
Recently, the multi-bit flip-flop (MBFF) technique was introduced as a method for reducing the power consumption and chip area of integrated circuits (ICs) during the physical implementation stage of their development process. From the perspective of the consumer, the main requirements for such [...] Read more.
Recently, the multi-bit flip-flop (MBFF) technique was introduced as a method for reducing the power consumption and chip area of integrated circuits (ICs) during the physical implementation stage of their development process. From the perspective of the consumer, the main requirements for such an optimization method are high performance, low power usage and small area (PPA). Therefore, any new optimization technique should improve at least one, if not all, of these requirements. This paper proposes a new low-power methodology, applying a MBFF merging solution during the physical implementation of an IC to achieve better power consumption and area reduction. The aim of this study is to prove the benefit of this methodology on the power saving capability of the system while demonstrating that the proposed methodology does not have a negative impact on the circuit performance and design routability. The experimental results show that MBFF merging of 76% can be achieved and preserved throughout the entire physical implementation process, from cell placement to the final interconnection routing, without impacting the system’s performance or routability. Moreover, the clock wirelength, nets and buffers needed to balance the clock network were reduced by 11.98%, 3.82% and 9.16%, respectively. The reduction of the clock tree elements led to a reduction of the power consumption of the clock nets, registers and cells by 22.11%, 20.84% and 12.38%, respectively. The total power consumption of the design was reduced by 2.67%. Full article
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Open AccessEditorial Acknowledgement to Reviewers of Journal of Low Power Electronics and Applications in 2018
J. Low Power Electron. Appl. 2019, 9(1), 2; https://doi.org/10.3390/jlpea9010002
Published: 16 January 2019
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Abstract
Rigorous peer-review is the corner-stone of high-quality academic publishing [...] Full article
Open AccessCommunication Modularity for Paralleling Different Rated Power Supplies Using Multi-Phase Switching Methods
J. Low Power Electron. Appl. 2019, 9(1), 1; https://doi.org/10.3390/jlpea9010001
Received: 1 November 2018 / Revised: 3 January 2019 / Accepted: 11 January 2019 / Published: 16 January 2019
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Abstract
This paper proposes a modularity for paralleling different rated power supplies without adding a circuit in the feedback loop by using direct and overlapped switching methods. Unlike an isolated output diode, the use of an isolated output switch composed of two Metal-Oxide-Semiconductor Field-Effect [...] Read more.
This paper proposes a modularity for paralleling different rated power supplies without adding a circuit in the feedback loop by using direct and overlapped switching methods. Unlike an isolated output diode, the use of an isolated output switch composed of two Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) can reduce power dissipation. The control module includes switches and a micro-programmed controlled unit that realizes the modularity by using multi-phase switching methods. The proposed module was studied, and experiments of two rated power supplies (60 and 45 W) were conducted to verify the studied results. Full article
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J. Low Power Electron. Appl. EISSN 2079-9268 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert
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