You are currently viewing a new version of our website. To view the old version click .

Journal of Low Power Electronics and Applications, Volume 9, Issue 1

March 2019 - 12 articles

  • Issues are regarded as officially published after their release is announced to the table of contents alert mailing list .
  • You may sign up for email alerts to receive table of contents of newly released issues.
  • PDF is the official format for papers published in both, html and pdf forms. To view the papers in pdf format, click on the "PDF Full-text" link, and use the free Adobe Reader to open them.

Articles (12)

  • Article
  • Open Access
2 Citations
8,163 Views
19 Pages

Experimental Evaluation of SAFEPOWER Architecture for Safe and Power-Efficient Mixed-Criticality Systems

  • Maher Fakih,
  • Kim Grüttner,
  • Sören Schreiner,
  • Razi Seyyedi,
  • Mikel Azkarate-Askasua,
  • Peio Onaindia,
  • Tomaso Poggi,
  • Nera González Romero,
  • Elena Quesada Gonzalez and
  • Timmy Sundström
  • + 9 authors

With the ever-increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as...

  • Article
  • Open Access
14 Citations
7,653 Views
18 Pages

Tolerating Permanent Faults in the Input Port of the Network on Chip Router

  • Hala J. Mohammed,
  • Wameedh N. Flayyih and
  • Fakhrul Z. Rokhani

Deep submicron technologies continue to develop according to Moore’s law allowing hundreds of processing elements and memory modules to be integrated on a single chip forming multi/many-processor systems-on-chip (MPSoCs). Network on chip (NoC)...

  • Article
  • Open Access
21 Citations
10,122 Views
20 Pages

In this research work, the threshold voltage and subthreshold swing of cylindrical surrounding double-gate (CSDG) MOSFET have been analyzed. These analyses are based on the analytical solution of 2D Poisson equation using evanescent-mode analysis (EM...

  • Article
  • Open Access
19 Citations
10,453 Views
19 Pages

The Internet-of-Things (IoT) revolution has shaped a new application domain where low-power RISC architectures constitute the standard computational backbone. The current de-facto design practice for such architectures is to extend the ISA and the co...

  • Article
  • Open Access
3 Citations
7,430 Views
8 Pages

A 50.5 ns Wake-Up-Latency 11.2 pJ/Inst Asynchronous Wake-Up Controller in FDSOI 28 nm

  • Jean-Frédéric Christmann,
  • Florent Berthier,
  • David Coriat,
  • Ivan Miro-Panades,
  • Eric Guthmuller,
  • Sébastien Thuries,
  • Yvain Thonnart,
  • Adam Makosiej,
  • Olivier Debicki and
  • Frédéric Heitzmann
  • + 3 authors

Due to low activity in Internet of Things (IoT) applications, systems tend to leverage low power modes in order to reduce their power consumption. Normally-off computing thus arose, consisting in having turned off most part of a system’s power...

  • Article
  • Open Access
15 Citations
8,369 Views
20 Pages

DoS Attack Detection and Path Collision Localization in NoC-Based MPSoC Architectures

  • Cesar Giovanni Chaves,
  • Siavoosh Payandeh Azad,
  • Thomas Hollstein and
  • Johanna Sepúlveda

Denial of Service (DoS) attacks are an increasing threat for Multiprocessor System-on-Chip (MPSoC) architectures. By exploiting the shared resources on the chip, an attacker is able to prevent completion or degrade the performance of a task. This is...

  • Article
  • Open Access
6,732 Views
15 Pages

In order to fit circuit electromagnetic emissions within a spectral mask, a design flow based on high level current modeling for micropipeline circuits is proposed. The model produces a quick and rough estimation of the circuit current, thanks to a T...

  • Article
  • Open Access
1 Citations
8,901 Views
9 Pages

A New Multi-Bit Flip-Flop Merging Mechanism for Power Consumption Reduction in the Physical Implementation Stage of ICs Conception

  • Lekbir Cherif,
  • Mohamed Chentouf,
  • Jalal Benallal,
  • Mohammed Darmi,
  • Rachid Elgouri and
  • Nabil Hmina

Recently, the multi-bit flip-flop (MBFF) technique was introduced as a method for reducing the power consumption and chip area of integrated circuits (ICs) during the physical implementation stage of their development process. From the perspective of...

  • Article
  • Open Access
23 Citations
10,461 Views
38 Pages

This discussion develops a theoretical analog architecture framework similar to the well developed digital architecture theory. Designing analog systems, whether small or large scale, must optimize their architectures for energy consumption. As in di...

  • Article
  • Open Access
1 Citations
7,232 Views
16 Pages

Energy efficient semiconductor chips are in high demand to cater the needs of today’s smart products. Advanced technology nodes insert high design margins to deal with rising variations at the cost of power, area and performance. Existing run t...

of 2

Get Alerted

Add your email address to receive forthcoming issues of this journal.

XFacebookLinkedIn
J. Low Power Electron. Appl. - ISSN 2079-9268