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Experimental Evaluation of SAFEPOWER Architecture for Safe and Power-Efficient Mixed-Criticality Systems

OFFIS e.V., 26121 Oldenburg, Germany
IK4-Ikerlan Technology Research Centre, 20500 Arrasate-Mondragón Gipuzkoa, Spain
CAF Signalling, 20018 San Sebastián, Gipuzkoa, Spain
Saab, 703 63 Stockholm, Sweden
FentISS, 46022 Valencia, Spain
Institute of Industrial Control Systems and Computing, Universitat Politecnica de Valencia, 46022 Valencia, Spain
School of Electrical Engineering and Computer Science, KTH Royal Institute of Technology, SE-100 44 Stockholm, Sweden
Department of Electrical Engineering and Computer Science, University of Siegen, 26121 Oldenburg, Germany
Imperas Software Ltd., North Weston, Thame OX9 2HA, UK
Authors to whom correspondence should be addressed.
J. Low Power Electron. Appl. 2019, 9(1), 12;
Received: 22 December 2018 / Revised: 27 February 2019 / Accepted: 6 March 2019 / Published: 11 March 2019
(This article belongs to the Special Issue Ultra-low Power Embedded Systems)
PDF [98081 KB, uploaded 12 March 2019]


With the ever-increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible. Even in safety-critical domains like railway and avionics, multicore processors are introduced, but under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such a System on Chip (SoC) is to enhance the way the SoC handles its power consumption. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC, which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power-saving methods in safety-critical domains yet. The EU project SAFEPOWER (Safe and secure mixed-criticality systems with low power requirements) targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality systems. This article provides an overview of the SAFEPOWER reference architecture for low-power mixed-criticality systems, which is the most important outcome of the project. Furthermore, the application of this reference architecture in novel railway interlocking and flight controller avionic systems was demonstrated, showing the capability to achieve power savings up to 37%, while still guaranteeing time-triggered task execution and time-triggered NoC-based communication. View Full-Text
Keywords: time-triggered; NoC-based communication; low-power; mixed-criticality; power-efficient time-triggered; NoC-based communication; low-power; mixed-criticality; power-efficient

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Fakih, M.; Grüttner, K.; Schreiner, S.; Seyyedi, R.; Azkarate-Askasua, M.; Onaindia, P.; Poggi, T.; Romero, N.G.; Quesada Gonzalez, E.; Sundström, T.; Peiró Frasquet, S.; Balbastre, P.; Mohammadat, T.; Öberg, J.; Bebawy, Y.; Obermaisser, R.; Maleki, A.; Lenz, A.; Graham, D. Experimental Evaluation of SAFEPOWER Architecture for Safe and Power-Efficient Mixed-Criticality Systems. J. Low Power Electron. Appl. 2019, 9, 12.

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J. Low Power Electron. Appl. EISSN 2079-9268 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert
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