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J. Low Power Electron. Appl. 2019, 9(1), 5; https://doi.org/10.3390/jlpea9010005

Power and Area Efficient Clock Stretching and Critical Path Reshaping for Error Resilience

1
VIRTUS, IC Design Centre of Excellence, School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798, Singapore
2
NXP Semiconductors Singapore Pte Ltd., 1 Fusionopolis Walk, #12-01/02 South Tower, Solaris, Singapore 138628, Singapore
*
Author to whom correspondence should be addressed.
Received: 28 December 2018 / Revised: 15 January 2019 / Accepted: 18 January 2019 / Published: 21 January 2019
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Abstract

Energy efficient semiconductor chips are in high demand to cater the needs of today’s smart products. Advanced technology nodes insert high design margins to deal with rising variations at the cost of power, area and performance. Existing run time resilience techniques are not cost effective due to the additional circuits involved. In this paper, we propose a design time resilience technique using a clock stretched flip-flop to redistribute the available slack in the processor pipeline to the critical paths. We use the opportunistic slack to redesign the critical fan in logic using logic reshaping, better than worst case sigma corner libraries and multi-bit flip-flops to achieve power and area savings. Experimental results prove that we can tune the logic and the library to get significant power and area savings of 69% and 15% in the execute pipeline stage of the processor compared to the traditional worst-case design. Whereas, existing run time resilience hardware results in 36% and 2% power and area overhead respectively. View Full-Text
Keywords: better than worst case design; error tolerance; slack re-distribution; time borrowing better than worst case design; error tolerance; slack re-distribution; time borrowing
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Jayakrishnan, M.; Chang, A.; Kim, T. .-H. Power and Area Efficient Clock Stretching and Critical Path Reshaping for Error Resilience. J. Low Power Electron. Appl. 2019, 9, 5.

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