Search Results (1,355)

Thermal management is an area of study in electronics focused on managing temperature to improve reliability and efficiency. When temperatures are too high, cooling systems are activated to prevent overheating, which can lead to reliability issues. To monitor the temperatures, sensors are often placed on-chip near hotspot locations. These sensors should be very small to allow them to be placed among compact, high-activity circuits. Often, they are connected to a central control circuit located far away from the hot spot locations where more area is available. This paper proposes sensing units for a novel temperature sensing architecture in the TSMC 180 nm process. This architecture functions by approximating the current through the sensing unit at a reference voltage, which is used to approximate the temperature in the digital back end using fitting functions. Sensing units are selected based on how well its temperature–current relationship can be modeled, sensing unit area, and power consumption. Many sensing units will be experimented with at different reference voltages. These temperature–current curves will be modeled with various fitting functions. The sensing unit selected is a diode-connected p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with a size of W = 400 nm, L = 180 nm. This sensing unit is exceptionally small compared to existing work because it does not rely on multiple devices at the sensing unit location to generate a PTAT or IPTAT signal like most work in this area. The temperature–current relationship of this device can also be modeled using a 2nd order polynomial, requiring a minimal number of trim temperatures. Its temperature error is small, and the power consumption is low. The range of currents for this sensing unit could be reasonably made on an IDAC. Full article

This paper presents the first hybrid supply modulator (HSM) designed for envelope tracking power amplifiers (ET-PAs) in base station applications. The focus is on a rail-to-rail Class-AB linear amplifier (LA) optimized for high-voltage and wide-bandwidth operation. The LA is designed using 130 nm BCD technology, utilizing Laterally Diffused Metal-Oxide Semiconductor (LDMOS) transistors for high-voltage operation and incorporating shielding MOSFETs to protect the low-voltage devices. The circuit utilizes dual power supply domains (5 V and 30 V) to improve power efficiency. The proposed LA achieves a bandwidth of 100 MHz and a slew rate of +1003/−852 V/$\mathsf{\mu }\mathrm{s}$, with a quiescent power consumption of 0.89 W. Transient simulations using a 50 MHz bandwidth 5G NR envelope input demonstrate that the proposed HSM achieves a power efficiency of 83%. Consequently, the proposed HSM supports high-output (100 W) wideband 5G NR transmission with enhanced efficiency. Full article

The development of an integrated circuit faces the challenge of the physical limit of Moore’s Law. One of the most important “Beyond Moore” challenges is the scaling down of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) versus their increasing static power consumption. This is because, at room temperature, the thermal emission transportation mechanism will cause a physical limitation on subthreshold swing (SS), which is fundamentally limited to a minimum value of 60 mV/decade for MOSFETs, and accompanied by an increase in off-state leakage current with the process of scaling down. Moreover, the impacts of short-channel effects on device performance also become an increasingly severe problem with channel length scaling down. Due to the band-to-band tunneling mechanism, Tunnel Field-Effect Transistors (TFETs) can reach a far lower SS than MOSFETs. Recent research works indicated that TFETs are already becoming some of the promising candidates of conventional MOSFETs for ultra-low-power applications. This paper provides a review of some advances in materials and structures along the evolutionary process of TFETs. An in-depth discussion of both experimental works and simulation works is conducted. Furthermore, the performance of TFETs with different structures and materials is explored in detail as well, covering Si, Ge, III-V compounds and 2D materials, alongside different innovative device structures. Additionally, this work provides an outlook on the prospects of TFETs in future ultra-low-power electronics and biosensor applications. Full article

AlGaN-based high-electron-mobility transistors are critical for next-generation power electronics and radio-frequency applications, yet achieving stable enhancement-mode operation with a high threshold voltage remains a key challenge. In this work, we designed p-AlGaN superlattices with different structures and performed energy band structure simulations using the device simulation software Silvaco. The results demonstrate that thin barrier structures lead to reduced acceptor incorporation, thereby decreasing the number of ionized acceptors, while facilitating vertical hole transport. Superlattice samples with varying periodic thicknesses were grown via metal-organic chemical vapor deposition, and their crystalline quality and electrical properties were characterized. The findings reveal that although gradient-thickness barriers contribute to enhancing hole concentration, the presence of thick barrier layers restricts hole tunneling and induces stronger scattering, ultimately increasing resistivity. In addition, we simulated the structure of the enhancement-mode HEMT with p-AlGaN as the under-gate material. Analysis of its energy band structure and channel carrier concentration indicates that adopting p-AlGaN superlattices as the under-gate material facilitates achieving a higher threshold voltage in enhancement-mode HEMT devices, which is crucial for improving device reliability and reducing power loss in practical applications such as electric vehicles. Full article

In advanced Complementary Metal-Oxide-Semiconductor (CMOS) technologies, where diminished feature sizes amplify radiation-induced soft errors, the optimization of fault-tolerant circuit designs requires detailed transistor-level analysis of reliability–performance trade-offs. As a fundamental building block in digital systems and critical data paths, the 2:1 multiplexer, widely used in data-path routing, clock networks, and reconfigurable systems, provides a critical benchmark for assessing radiation-hardened design methodologies. In this context, this work aims to analyze the power consumption, area overhead, and delay of 2:1 multiplexer designs under transient fault conditions, employing the CMOS and Differential Cascode Voltage Switch Logic (DCVSL) logic styles and mitigation strategies. Electrical simulations were conducted using 32 nm high-performance predictive technology, evaluating both the original circuit versions and modified variants incorporating three mitigation strategies: transistor sizing, D-Cells, and C-Elements. Key metrics, including power consumption, delay, area, and radiation robustness, were analyzed. The C-Element and transistor sizing techniques ensure satisfactory robustness for all the circuits analyzed, with a significant impact on delay, power consumption, and area. Although the D-Cell technique alone provides significant improvements, it is not enough to achieve adequate levels of robustness. Full article

With their superior switching speed, GaN high-electron-mobility transistors (HEMTs) enable high power density, reduce energy losses, and increase power efficiency in a wide range of applications, such as power electronics, due to their high breakdown voltage. GaN-HEMT devices are subject to long-term reliability due to the self-heating effect and lattice mismatch between the SiC substrate and the GaN. Depletion-mode GaN HEMTs are utilized for radio frequency applications, and this work investigates three wide-bandgap (WBG) GaN HEMT fixed-frequency oscillators with output buffers. The first GaN-on-SiC HEMT oscillator consists of an HEMT amplifier with an LC feedback network. With the supply voltage of 0.8 V, the single-ended GaN oscillator can generate a signal at 8.85 GHz, and it also supplies output power of 2.4 dBm with a buffer supply of 3.0 V. At 1 MHz frequency offset from the carrier, the phase noise is −124.8 dBc/Hz, and the figure of merit (FOM) of the oscillator is −199.8 dBc/Hz. After the previous study, the hot-carrier stressed RF performance of the GaN oscillator is studied, and the oscillator was subject to a drain supply of 8 V for a stressing step time equal to 30 min and measured at the supply voltage of 0.8 V after the step operation for performance benchmark. Stress study indicates the power oscillator with buffer is a good structure for a reliable structure by operating the oscillator core at low supply and the buffer at high supply. The second balanced oscillator can generate a differential signal. The feedback filter consists of a left-handed transmission-line LC network by cascading three unit cells. At a 1 MHz frequency offset from the carrier of 3.818 GHz, the phase noise is −131.73 dBc/Hz, and the FOM of the 2nd oscillator is −188.4 dBc/Hz. High supply voltage operation shows phase noise degradation. The third GaN cross-coupled VCO uses 8-shaped inductors. The VCO uses a pair of drain inductors to improve the Q-factor of the LC tank, and it uses 8-shaped inductors for magnetic coupling noise suppression. At the VCO-core supply of 1.3 V and high buffer supply, the FOM at 6.397 GHz is −190.09 dBc/Hz. This work enhances the design techniques for reliable GaN HEMT oscillators and knowledge to design high-performance circuits. Full article

A broadband, efficient monolithic microwave integrated circuit power amplifier (MMIC PA) in OMMIC’s 0.1 μm GaN-on-Si technology for 5G millimeter-wave communication is presented. This study concentrates on the output matching design, which has an important influence on the PA’s performance. A compact one-order synthesized transformer network (STN) is adopted to match the 50 Ω load to the extracted large-signal output model of the transistor. A dual-objective strategy is developed for parameter optimization, incorporating the impedance transformation trajectory inside the predefined optimal impedance domain (OID) that satisfies the required specifications, with approximation to selected optimal load impedances. By introducing a custom adjustment factor β into the error function, coupled with an automated iterative tuning process based on S-parameter simulations, desired broadband matching results can be rapidly achieved. The proposed two-stage PA occupies a small chip area of only 1.23 mm² and demonstrates good frequency consistency over the 24–31 GHz band. Continuous-wave characterization shows a flat small-signal gain of 19.7 ± 0.5 dB; both the output power (P_out) and the power-added efficiency (PAE) at the 4 dB compression point remain smooth, ranging from 32.3 to 32.7 dBm and 35.5% to 37.8%, respectively. The peak PAE reaches up to nearly 40% at the center frequency. Full article

As transistor dimensions continue to scale below 10 nm, traditional MOSFET architectures face increasing limitations from short-channel effects, gate leakage, and variability. FinFETs, especially junctionless FinFETs on silicon-on-insulator (SOI) substrates, offer improved electrostatic control and simplified fabrication, making them attractive for deeply scaled nodes. In this work, we propose a novel Stepped-Spacer Structured FinFET (S³-FinFET) that incorporates a three-layer HfO₂/Si₃N₄/HfO₂ spacer configuration designed to enhance electrostatics and suppress parasitic effects. Using 2D TCAD simulations, the S³-FinFET is evaluated in terms of key performance metrics, including transfer/output characteristics, ON/OFF current ratio, subthreshold swing (SS), drain-induced barrier lowering (DIBL), gate capacitance, and cut-off frequency. The results show significant improvements in leakage control and high-frequency behavior. These enhancements make the S³-FinFET particularly well-suited for Field-Programmable Gate Arrays (FPGAs), where power efficiency, speed, and signal integrity are critical to performance in reconfigurable logic environments. Full article

High-frequency (h. f.) harmonic distortion (HD) of advanced SiGe heterojunction bipolar transistor (HBT)-based power cells (PwCs), featuring optimized metallization interconnections between individual HBTs, was investigated. Single tone input power (P_in) excitations at 1, 2, 5, and 10 GHz frequencies were employed. The output power (P_out) of the fundamental tone and its harmonics were analyzed in both the frequency and time domains. A rapid increase in the third harmonic of P_out was observed at input powers exceeding −8 dBm for a fundamental frequency of 10 GHz in two different PwC technologies. This increase in the third harmonic was analyzed in terms of nonlinear current waveforms, the nonlinearity of the HBT p-n junction diffusion capacitances, substrate current behavior versus P_in, and avalanche multiplication current. To assess the RF power performance of the PwCs, scalar and vectorial load-pull (LP) measurements were conducted and analyzed. Under matched conditions, the SiGe PwCs demonstrated good linearity, particularly at high frequencies. The key power performance of the PwCs was measured and simulated as follows: input power 1 dB compression point (P_{in_1dB}) of −3 dBm, transducer power gain (G_T) of 15 dB, and power added efficiency (PAE) of 50% at 30 GHz. All measured data were corroborated with simulations using the compact model HiCuM L2. Full article

This study presents transistor-level simulation results for a novel memristor emulator circuit. The design incorporates an inverter and a current-mode-controlled operational transconductance amplifier to stabilize the output voltage. Transient performance is evaluated across a 20 MHz to 100 MHz frequency range. Simulations using 0.18 μm TSMC technology confirm the circuit’s functionality, demonstrating a power consumption of 0.1 mW at a 1.2 V supply. The memristor model’s reliability is verified through corner simulations, along with Monte Carlo and temperature variation tests. Furthermore, the emulator is applied in a Memristive Integrate-and-Fire neuron circuit, a CMOS-based system that replicates biological neuron behavior for spike generation, enabling ultra-low-power computing and advanced processing in retinal prosthesis applications. Full article

This paper presents a complete workflow for the evaluation of GaN transistors in voltage source inverters. With the associated high switching speed of transistors based on GaN, it is important to consider some critical points in the design phase as well as in the measurement setup in order to be able to utilise and verify the advantages of GaN properly. For this reason, the presented circuit board’s design focuses on a minimised power loop inductance. Simulation models, an analytical approach and measurement results with the aim of determining this inductance are compared with each other. A good compliance results between the presented methods. Additionally, the description of a test bench is given, which enables the performance of the opposition method. This setup allows the measurement of the designed H-bridge’s arising losses and the GaN-transistor’s switching behaviour. In comparison to the conventional double pulse method, this approach enables results that are more accurate for determining losses. Full article

Gallium nitride (GaN) enhancement-mode high-electron-mobility transistors ( E-HEMTs) deliver superior performance compared to traditional silicon (Si) and silicon carbide (SiC) counterparts. Their faster switching speeds, lower on-state resistances, and higher operating frequencies enable more efficient and compact power converters. However, their integration into high-power applications is limited by critical reliability concerns, particularly regarding their short-circuit (SC) withstand capability and overvoltage (OV) resilience. GaN devices typically exhibit SC withstand times of only a few hundred nanoseconds, needing ultrafast protection circuits, which conventional desaturation (DESAT) methods cannot adequately provide. Furthermore, their high switching transients increase the risk of false activation events. The lack of avalanche capability and the dynamic nature of GaN breakdown voltage exacerbate issues related to OV stress during fault conditions. Although SC-related behaviour in GaN devices has been previously studied, a focused and comprehensive review of protection strategies tailored to GaN technology remains lacking. This paper fills that gap by providing an in-depth analysis of SC and OV failure phenomena, coupled with a critical evaluation of current and next-generation protection schemes suitable for GaN-based high-power converters. Full article

Gallium nitride high-electron-mobility transistors (GaN HEMTs) are critical for high-power applications like AI power supplies and robotics but face reliability challenges due to increased dynamic ON-resistance (R_{DS_ON}) from electrical and thermomechanical stresses. This paper presents a novel self-calibrating temperature-sensitive electrical parameter (TSEP) model that uses gate leakage current (I_G) to estimate junction temperature with high accuracy, uniquely addressing aging effects overlooked in prior studies. By integrating I_G, aging-induced degradation, and failure-in-time (FIT) models, the approach achieves a junction temperature estimation error of less than 1%. Long-term hard-switching tests confirm its effectiveness, with calibrated R_{DS_ON} measurements enabling precise remaining useful life (RUL) predictions. This methodology significantly improves GaN HEMT reliability assessment, enhancing their performance in resilient power electronics systems. Full article

The advancement of Internet of Things (IoT) technology has enabled battery-powered devices to be deployed across a wide range of applications; however, it also introduces challenges such as high energy consumption and security vulnerabilities. To address these issues, adiabatic logic circuits offer a promising solution for achieving energy efficiency and enhancing the security of IoT devices. Adiabatic logic circuits are well suited for energy harvesting systems, especially in applications such as sensor nodes, RFID tags, and other IoT implementations. In these systems, the harvested bipolar sinusoidal RF power is directly used as the power supply for the adiabatic logic circuit. However, adiabatic circuits require a peak detector to provide bulk biasing for pMOS transistors. To meet this requirement, a diode-connected MOS transistor-based voltage doubler circuit is used to convert the sinusoidal input into a usable DC signal. In this paper, we propose a novel adiabatic logic design that maintains low power consumption while optimizing energy and current fluctuations across various input transitions. By ensuring uniform and complementary current flow in each transition within the logic circuit’s functional blocks, the design reduces energy variation and enhances resistance against power analysis attacks. Evaluation under different clock frequencies and load capacitances demonstrates that the proposed adiabatic logic circuit exhibits lower fluctuation and improved security, particularly at load capacitances of 50 fF and 100 fF. The results show that the proposed circuit achieves lower power dissipation compared to conventional designs. As an application example, we implemented an ultrasonic transmitter circuit within a LoRaWAN network at the end-node sensor level, which serves as both a communication protocol and system architecture for long-range communication systems. Full article

Dynamic on-resistance (R_ON) of commercial GaN on Si normally off high-electron-mobility transistor (HEMT) devices is a very important parameter because it is responsible for conduction losses that limit the power conversion efficiency of high-power switching converters. Due to charge trapping effects, dynamic R_ON is always higher than in DC, a behavior known as current collapse. To study how short-time dynamics of charge trapping and release affects R_ON we use rectangular 0–5 V gate voltage pulses with durations in the 1 μs to 100 μs range. Measurements are first carried out for single pulses of increasing duration, and it is found that R_ON depends on both pulse duration and drain current I_D, being higher at shorter pulse durations and lower I_D. For a train of five pulses, R_ON decreases with pulse number, reaching a steady state after a time interval of 100 μs. The response to a five pulses train is compared to that of a square-wave signal to study the time evolution of R_ON toward a dynamic steady state. The DC R_ON is also measured, and it is a factor of ten smaller than dynamic R_ON at the same I_D. This confirms that a reduction in trapped charges takes place in DC as compared to the square-wave switching operation. Additional off-state stress tests at V_DS = 55 V reveal the presence of residual surface traps in the drain access region, leading to four times increase in R_ON in comparison to pristine devices. Finally, the dynamic R_ON is also measured by the double-pulse test (DPT) technique with inductive load, giving a good agreement with results from single-pulse measurements. Full article