Design and Evaluation of Radiation-Tolerant 2:1 CMOS Multiplexers in 32 nm Technology Node: Transistor-Level Mitigation Strategies and Performance Trade-Offs

Abstract

In advanced Complementary Metal-Oxide-Semiconductor (CMOS) technologies, where diminished feature sizes amplify radiation-induced soft errors, the optimization of fault-tolerant circuit designs requires detailed transistor-level analysis of reliability–performance trade-offs. As a fundamental building block in digital systems and critical data paths, the 2:1 multiplexer, widely used in data-path routing, clock networks, and reconfigurable systems, provides a critical benchmark for assessing radiation-hardened design methodologies. In this context, this work aims to analyze the power consumption, area overhead, and delay of 2:1 multiplexer designs under transient fault conditions, employing the CMOS and Differential Cascode Voltage Switch Logic (DCVSL) logic styles and mitigation strategies. Electrical simulations were conducted using 32 nm high-performance predictive technology, evaluating both the original circuit versions and modified variants incorporating three mitigation strategies: transistor sizing, D-Cells, and C-Elements. Key metrics, including power consumption, delay, area, and radiation robustness, were analyzed. The C-Element and transistor sizing techniques ensure satisfactory robustness for all the circuits analyzed, with a significant impact on delay, power consumption, and area. Although the D-Cell technique alone provides significant improvements, it is not enough to achieve adequate levels of robustness.

1. Introduction

The continuous advancement of CMOS electronic devices has been made possible through transistor scaling, which has enabled remarkable improvements in computational density [1]. As technology nodes continue scaling down, the reliability of integrated circuits (ICs) in the radiation environment becomes more important [2]. Of particular concern is the necessary reduction in supply voltage that accompanies device scaling. While lower operating voltages successfully address power dissipation requirements, they inadvertently increase the circuit’s vulnerability to radiation-induced effects [3]. This occurs because the reduced voltage levels correspondingly decrease the energy required to maintain logic states, thereby making the circuits more susceptible to corruption caused by particle strikes, resulting in single-event effect (SEE) faults [4].

Single-event effects represent a critical reliability challenge in modern electronic systems, often manifesting as soft errors that can corrupt data or disrupt circuit operation without causing permanent damage. These effects occur when ionizing radiation generates charge carriers that interfere with normal device operation, with common manifestations including single-event upsets (SEUs) or single-event transients (SETs) [5]. Among these phenomena, SETs pose particularly significant threats to combinational logic circuits, as they induce transient variations in current or voltage that can be propagated, leading to errors. The growing vulnerability to SETs in advanced technology nodes primarily stems from the fact that rising clock frequencies and tighter timing constraints create greater opportunities for SET propagation through logic paths.

Single-event transients induced by ionizing radiation pose a critical threat to the reliability of nanoscale integrated circuits, particularly in harsh environments such as space, avionics, and high-altitude applications. While extensive research has focused on SET mitigation in memory elements (e.g., flip-flops and SRAM) [6,7], full adders [8], voters [9], and basic logic gates [10], circuits such as multiplexers (MUXs) remain understudied.

The 2:1 multiplexer serves as a fundamental building block in processors and communication systems, yet its inherent structure makes it particularly vulnerable to radiation effects. This vulnerability arises from the fact that a single-event transient occurring on the select line can corrupt the output, depending on the input logic state, potentially leading to silent data errors or system failures. While prior research has extensively evaluated multiplexer designs for power and delay characteristics, to the best of our knowledge, comprehensive assessments of radiation susceptibility remain limited. Although recent work has begun examining SET vulnerability across different 2:1 MUX topologies, including transmission gates, static CMOSs, pass transistors, and others [11], the literature still lacks systematic studies exploring radiation-tolerant designs that combine logic styles with hardening-by-design techniques.

This paper presents a comprehensive analysis of 2:1 multiplexer designs under single-event transient faults, evaluating the impact on power, delay, and area (PPA) characteristics, alongside susceptibility to radiation-induced faults. Based on the previously evaluation provided in [11], we selected the most promising multiplexer topologies, considering two logic styles, static CMOS and differential cascode voltage-switch logic (DCVSL). These multiplexers are then discussed in terms of three circuit-level mitigation strategies: transistor sizing (TS), Decoupling Cells (D-Cells), and C-Elements (CEs). The main contribution of this work is to quantify the trade-offs between performance metrics and SET robustness, providing guidelines for the design of radiation-hardened multiplexers in critical applications. Furthermore, the comparison with related work highlights the growing need for radiation impact analysis in multiplexer designs, particularly as technology nodes scale down, increasing susceptibility to radiation-induced faults. To the best of our knowledge, this is the first work to systematically apply radiation-hardening techniques—such as transistor sizing, Decoupling Cells, and C-Elements—to 2:1 multiplexers while rigorously analyzing their performance trade-offs. Our findings demonstrate that hardening the output node not only improves radiation resilience but also ensures robustness across internal nodes, offering a balanced solution for reliability-critical applications. By integrating radiation tolerance metrics with traditional PPA evaluation, this work bridges a critical gap in the field, providing designers with a comprehensive discussion for designing and optimizing multiplexers for harsh environments. The methodologies and results presented herein serve as a foundational step for future work in designing fault-tolerant combinational circuits for applications ranging from space electronics to medical devices.

The remainder of this paper is organized as follows: Section 2 provides background on multiplexer design techniques, single-event transient mechanisms in nanoscale technologies, and mitigation approaches, including transistor sizing, Decoupling Cells, and C-Elements. Section 3 describes the simulation methodology, covering SPICE models, SET injection techniques, and power–area–delay extraction. Section 4 presents the results, comparing the performance and SET resilience of each design variant. Section 5 discusses key trade-offs and practical implications for circuit designers. Finally, Section 6 concludes the work and outlines future research directions.

2. Background

The choice of logic style directly influences the characteristics of an integrated circuit, such as power, performance, and area. Considering design for reliable systems, robustness is also a relevant point to be characterized for the logic functions under evaluation to help designers to choose the most appropriated transistor arrangement for the application requirement [12,13]. This work considers the robustness to radiation effects, more specifically the single-event effects on combinational circuits that result into single-event transient faults. In this context, we present an overview about SET faults and also about the circuit-level fault mitigation techniques explored in this work. Among different approaches proposed in the literature, we focus on the impact of C-Elements [14], Decoupling Cells [15], and transistor sizing [16] applied to different logic styles of multiplexers.

2.1. Single-Event Effects

The study of radiation effects on microelectronics began in earnest after the 1962 failure of a U.S. telecommunications satellite during high-altitude nuclear testing [17]. Radiation interacts with integrated circuits through two fundamental mechanisms: (1) direct ionization by the incident particle and (2) indirect ionization through secondary particles generated when primary particles react with material [18].

The ongoing scaling of CMOS technology has increased radiation vulnerability despite performance improvements. Reduced operating voltages and critical charge levels have heightened SEE sensitivity, while higher clock frequencies diminish natural timing masking effects against soft errors. Single-event effects occur when energetic particles strike sensitive regions, generating charge pulses [19]. These are classified as destructive or non-destructive [20]. Destructive SEEs cause permanent damage on the circuits, while non-destructive cause temporary errors. In the case of non-destructive SEEs, there are single-event upsets, which are bit-flips in memory elements, and single-event transients, which are particle collisions in combinational logic. However, the effects caused by these non-destructive failures are considered temporary; i.e., they can be restored by re-performing the operation [2].

A sensitive node is typically a reversed-biased PN junction with a conductive path to the output [21]. As the particle passes through this sensitive node, it liberates electron–hole pairs, losing energy in the process. This generates a transient current, leading to the accumulation of charges at the affected node [22]. The particle’s trajectory is referred to as the particle range, and the energy lost along this path is known as Linear Energy Transfer (LET) [23].

In the context of combinational circuits, such particle interactions can result in a single-event transient (SET) fault. The transient pulse generated by the particle can vary in magnitude and polarity depending on the transistor affected. Figure 1 shows in a simplified way that a particle collision in a circuit can have different magnitudes. If the particle collides an NMOS transistor, the terminal will be discharged to GND, generating a “101” transient pulse, as illustrated in Figure 1a. Conversely, if the particle affects a PMOS transistor, the node will be charged by the charges present in the well, generating a “010” transient current, called a P-hit, as illustrated in Figure 1b.

2.2. Circuit-Level Fault Mitigation Techniques

The growing deployment of electronic systems in radiation-prone environments has significantly increased the demand for effective mitigation techniques against radiation faults. Radiation-hardening strategies vary from fabrication process modifications to circuit-level design implementations, typically named technological hardening or hardening-by-design approaches [24]. While technological hardening involves specialized manufacturing processes, hardening by design offers greater flexibility by implementing radiation tolerance during the circuit design phase. This design-centric approach can be applied across multiple abstraction levels, from individual transistor optimization to complete system architecture, enabling tailored solutions for different radiation environments. However, these hardening techniques invariably introduce trade-offs among area, power consumption, and delay overhead, which must be carefully balanced. At the transistor level, many techniques can be applied [24]; however, this paper focus on three gate hardening strategies, (1) transistor sizing, (2) D-Cell implementation, and (3) C-Element utilization, each offering distinct advantages and compromises in terms of radiation tolerance and circuit performance metrics.

2.2.1. C-Element

The C-Element strategy is a fault mitigation technique that compares the logic state of its inputs [14]. The idea of temporal filtering is to mitigate SET pulses that are faster than the delay. Thus, when the inputs are identical, the C-Element works as an inverter, changing the logic state of its output. Additionally, when its inputs differ, it retains the logic state, functioning as a memory element. The time it remains in this state is defined by the number of delay buffers. The logic behavior is shown in Figure 2.

However, this technique has two vulnerabilities: The first occurs when the C-Element is in the memory state, because if a particle hits the C-Element block, the energy necessary to cause an error is reduced and the SET pulse will propagate. The second is the scaling of the delay, because if the charge collection period at the node is very long, the delay needs to be longer.

2.2.2. Decoupling Cell

Decoupling Cells, also known as D-Cells, represent a promising approach to mitigate the effects of single-event transients in combinational logic gates. Originally used to filter noise in power supply and signals, these cells consist of transistors connected in cross-coupling mode, which increases the total capacitance at the output node of the logic gate [15]. This increase in capacitance increases the critical charge ($Q_{crit}$) required to induce a SET pulse, making the output node less sensitive to the impact of energetic particles. It is recommended to use two Decoupling Cells to ensure protection against P-hit and N-hit effects, connecting one between the output and the power supply and the other between the output and ground, as shown in Figure 3.

2.2.3. Transistor Sizing

Transistor resizing aims to increase the capacitance of the sensitive nodes, increasing the critical charge ($Q_{crit}$) needed to induce a SET [16]. However, this can increase the transistor’s drain area, which in turn increases the charge collected ($Q_{coll}$) during the particle’s impact. For low-LET particles, symmetrical resizing tends to reduce the transient pulse [25]. However, for higher LETs, the technique may not be effective and may even increase the amplitude and duration of the SET. The effectiveness of resizing is a compromise between the collected load and the critical load of the node. However, increasing the size of the transistors too much presents significant disadvantages in terms of area cost and power.

In this context, to manage the large elements in the design layout, it is common to apply the transistor folding technique [16,26]. Transistor folding divides a large transistor into multiple parallel segments in the layout, as shown in Figure 4. This makes it possible to reduce the area of the transistor drain affected by radiation without decreasing the node’s total capacitance or current capacity (since the transistors are added in parallel). This approach proves effective in reducing SETs induced by low- and high-energy particles [16]. Figure 4 shows the difference between these techniques at the circuit level and at the layout level.

2.3. Related Work

Multiplexers, also called MUXs, are essential components in digital electronics, particularly in communication systems and microprocessors, acting as data selectors that route multiple input signals to a single output line [27]. Their importance lies in their ability to increase data transmission efficiency, optimize memory space usage in computers, and convert data from parallel to serial formats in data communication. Multiplexers of the 2:1 type function as data selection switches, choosing between two input lines (A or B) based on the state of a selection line (S) and directing the selected signal to the output (Y). Figure 5 presents the logic gate block, truth table, and the logic function of a 2:1 multiplexer.

The literature features numerous works exploring different multiplexer designs while analyzing aspects such as power, performance, and area cost [11,27,28,29,30]. Since the 1990s, studies focused on multiplexer analysis have been produced in the literature, such as the work by [28], which presents an analysis of different logic styles examining power, area, and performance aspects for combinational circuits and full adders, using a 600 nm technology node.

In the 2000s, the topic was revisited, with the work in [27] presenting a power analysis for three different technology nodes: 45 nm, 32 nm, and 16 nm. The work in [31] presents an analysis of 2:1 multiplexers in various logic styles, using 180 nm technology. Currently, new demands for ultra-low-power circuits are emerging, and the work in [30] introduces new multiplexer proposals for (28 nm) technology nodes. Studies discussing radiation effects robustness analysis remain limited. More recently, the work in [11] addresses the most common logic styles in low-power and high-performance circuits, analyzing them only from a robustness perspective.

In this context, the main contribution of this work is to perform an analysis that encompasses the main metrics discussed in the literature—power consumption, performance, and area cost—and provide a robustness analysis against transient faults, employing circuit-level fault tolerance techniques. Several works use fault mitigation techniques to increase the robustness of combinational circuits and review the main techniques used [20,24,32,33,34,35].

Table 1. Comparative synthesis of the characteristics evaluated in this work and in the literature.

Characteristic	This Work	[11]	[31]	[30]	[28]	[29]
Technology Node	32 nm	32 nm	90 nm	28 nm	600 nm	180 nm
Impact on Area Overhead	yes	no	no	no	yes	yes
Impact on Power	yes	no	yes	yes	yes	yes
Impact on Delay	yes	no	yes	yes	yes	yes
Radiation-Hardening Evaluation	yes	yes	no	no	no	no
Design Style Evaluation	yes	yes	yes	yes	yes	yes

provides a comparative synthesis of the key characteristics addressed in the literature and the contributions proposed by this work. The evaluated aspects include the targeted technology node, the impact on power–performance–area parameters, a radiation-hardened design analysis, extracted LET threshold (LETth) values, and an assessment of different design approaches. The table reveals that while some related works evaluate 2:1 multiplexers, most focus primarily on PPA analysis without considering radiation effects. This comprehensive analysis addresses a research gap in the existing literature concerning 2:1 multiplexers’ robustness. Many works have been dedicated to optimizing these fundamental building blocks for traditional power, performance, and area metrics. However, the concurrent evaluation of radiation-induced transient faults has remained limited. Our work advances this field by integrating radiation-hardening techniques into the design flow and quantifying their impact on PPA parameters. This approach yields a more holistic understanding of the design trade-offs required for reliability-critical applications. By employing circuit-level fault tolerance methods such as transistor sizing, Decoupling Cells, and C-Elements, we demonstrate that a balanced PPA solution can be achieved without compromising robustness. The findings indicate that hardening the output node is a particularly effective strategy, as it not only improves radiation resilience at the final stage but also offers an inherent level of robustness across internal circuit nodes. This integration of radiation tolerance metrics with traditional PPA evaluation provides a robust and comprehensive panorama for circuit designers, enabling the optimization of multiplexers for operation in harsh environments where transient faults are a significant concern.

3. Methodology

This work systematically evaluates the robustness of 2:1 multiplexer designs against single-event transient faults while analyzing trade-offs between radiation-hardening effectiveness and power–performance–area characteristics. In order to analyze the robustness of each circuit, electrical simulations were carried out using the NGSPICE simulator, version 44 [36]. The simulation methodology is presented in the next paragraphs.

The experiments use the 32 nm high-performance predictive model from [37], with a nominal voltage of 0.9 V and minimal transistor sizing (i.e., L = 32 nm, Wn_$min$ = 70 nm, and Wp_$min$ = 105 nm), and a Cload capacitor of 1$fC$ is connected to the output node. In addition to minimum sizing, the logic effort rule is applied. The simulated scenario used is demonstrated in Figure 6. These characteristics are used to simulate and define the typical behavior of each circuit.

The first step involves selecting the best design candidates. For this, we rely on a prior evaluation of various multiplexer designs [11], where the top ten designs were chosen based on radiation robustness. Figure 7 illustrates the ten analyzed designs, all featuring data inputs A and B and a selector switch S. A detailed analysis of the different 2:1 multiplexer designs reveals poor distinctions in their implementations.

Circuits V1 to V4 are developed in single-stage CMOS, while circuits V5 and V6 are developed in multi-stage. All these circuits are designed in the static CMOS logic style. Circuit V1 has no parallel loop in any plane. V2 has parallel loops in both planes, and V3 has them only in the upper plane. V4 represents the equivalent circuit of the multiplexer equation when the Morgan’s equation is applied, resulting in the inverter being removed from the output and added to all inputs. MUX V5 is developed using NAND logic gates, and V6 uses both NAND and NOR logic gates.

The designs of V7 to V10 are developed in the DCVSL logic style. For designs V7 to V10, the differences lie in the NMOS transistor network. Design V7 has no parallel loops, V8 only in the left network, and V9 in both, and V10 has cross-coupling between the planes.

The second step of this work is to define a Linear Energy Transfer threshold (LETth) value within which the designs should be able to tolerate a SET. The value of 5 MeV was chosen considering the intensity of some of the most common radiation-causing elements reported in the literature [34]. It is important to note that this work consists exclusively of electrical simulations, without encompassing physical experimentation. We consider that different particle interactions may result in an energy deposition of approximately 5 MeV within the circuit and opted to adopt a moderate but significant intensity in the evaluation. Based on this representative energy value, we perform electrical simulations following established methodologies in the literature that employ TCAD tools to model radiation effects and evaluate circuit response [21,38,39]. By abstracting the analysis to a generic scenario in which any particle may cause this energy deposition, we define our protection parameters without the need to detail every possible particle type and interaction mechanism. This methodological choice effectively avoids the complexity and high computational cost associated with extensive simulations, such as Monte Carlo analyses, while maintaining a focus on the circuit’s electrical response under representative radiation conditions. This value is configurable and can be changed without modifying the methodological sequence of this work.

The third step is to evaluate the radiation robustness of each design, as the traditional form, i.e., without mitigation technique, and as radiation-hardened forms by applying three transient fault mitigation techniques, C-Elements, D-Cells, and transistor sizing, observing the impact of each on power consumption, delay, and area cost parameters. After evaluating the typical behavior and identifying that no design reached the desired LET threshold (i.e., 5 MeV), the three mitigation techniques were implemented separately.

The first technique implemented is the C-Element technique, whose transistors and buffers are dimensioned with the same specifications as the 2:1 multiplexers. The implementation in the designs illustrated in Figure 7 requires specific adaptations due to its inverting characteristic. When the original circuit has an inverter connected to the output, it must be removed to allow the correct connection of the delay block and the comparator; otherwise, if there is no inverter in the initial configuration, it is necessary to insert a new inverter stage before the delay. These modifications, represented schematically in Figure 8, ensure the proper integration of the C-Element into the system, preserving the operating logic and timing conditions of the design.

To determine the minimum number of buffers required to completely mitigate a SET fault, pairs of buffers are added sequentially, starting with one pair, until the charge collection period is shorter than the delay time [40]. Figure 9 presents the fault masking process graphed by the C-Element. In X, a fault is injected at the output of the combinational circuit; Y indicates the output of the delay block, and Q shows the output of the C-Element, representing the result after mitigation. It is noteworthy that even when the particle-induced disturbance reaches its maximum amplitude (0 V in this example), the C-Element output exhibits only a minimal perturbation. This demonstrates the effectiveness of the mitigation technique in suppressing transient faults at the circuit output.

Figure 9 illustrates the importance of properly dimensioning the delay block. The delay introduced by it ensures that only a minimum amount of energy is propagated to the comparator input. This energy is insufficient to sustain the error condition at the comparator output. In the context of this study, the delay was obtained by configuring 16 buffers.

The second technique implemented is the D-Cell. In this work, two D-Cells are implemented in the output node, as shown in Figure 3. Since the main idea of this technique is to be capacitive [15], the size of the PMOS and NMOS transistors is set to 800 nm; that is, each D-Cell has a total size of 1600 nm.

The last technique employed is transistor sizing. This work begins with minimum-sized transistors, optimized using logic effort. Subsequently, each transistor’s dimensions are scaled up by a factor of two while maintaining proportional relationships, as detailed in Figure 10.

To simulate the electrical effect of the SET fault, the macro-modeling method is used [41], which consists of inserting an independent current source of opposite magnitude to the state of the sensitive node [4], as shown in Figure 11 and mathematically modeled as described in Equation (1). A fault is considered when the pulse maximum exceeds 50% of $Vdd$, i.e., 0.45 V, at the circuit output. The pulse is modeled according to Equation (1). The $T\alpha$ is defined to $1.64\times {10}^{-10}$ s and $T\beta$ is defined to $5\times {10}^{-11}$ s [42]. These values represent the time constants for charge collection and the time constant for the initial establishment of the ion track, respectively.

$$I_{set}\left(t\right)={\displaystyle \frac{Qcoll}{T\alpha -T\beta }}(e^{{\displaystyle \frac{-t}{T\alpha }}}-e^{{\displaystyle \frac{-t}{T\beta }}})$$

(1)

From the current value $I_{set}\left(\mathit{t}\right)$ obtained from the simulation, it is possible to calculate the value of the collected charge ($Q_{coll}$) using Equation (2). As this work considers the minimum current value necessary to cause a fault, the collected charge is equivalent to the critical charge. To calculate the value of $LET$, Equation (3) is used. The parameter L refers to the depth of the charge collection channel and has a value of 1 $\mu$m. The constant 10.8 fC corresponds to the charge deposited by the particle for each 1 $\mu$m [43].

$$Qcoll=I\left(\mathit{t}\right)\times (T\alpha -T\beta )$$

(2)

$$LET={\displaystyle \frac{Q_{coll}}{10.8f.L}}$$

(3)

To perform the power consumption simulations, a specific test pattern was developed for each input, as illustrated in Figure 12. The sources “pa”, “pb”, and “ps” correspond to the waveforms applied to inputs A, B, and S, respectively. The pattern includes all 57 possible transitions, with the first 18 designed to represent the delays associated with each input individually, while the others correspond to the other transition combinations. After defining the test pattern, the power consumption was measured by the simulator using Equation (4).

$$Power=Vdd{\int }_{i=0ns}^{i=57ns}di$$

(4)

4. Results

This section presents the results of the impact of each technique on robustness. These results are presented in graphs organized by input vector and tables, summarizing the information of critical LETth, mean, and standard deviation, in addition to an overview of which techniques achieved the objective. The results for the nominal operation, without any mitigation technique applied, are labeled MUX. These results for nominal operation provide a relative comparison baseline for the impact of the mitigation approaches. Finally, the drawbacks of the mitigation techniques on the electrical characteristics of power consumption and delay are discussed for each 2:1 multiplexer design illustrated in Figure 7.

4.1. LET Impact

The evaluation of the mitigation techniques’ impact on the LET threshold reveals several critical findings. Notably, the C-Element technique demonstrated complete radiation robustness, proving to be fully effective against single-event transients in the multiplexer design. It is important to clarify that the C-Element technique was omitted from the LETth tables because its mitigation strategy relies on introducing a delay to filter out transient faults. This approach was specifically dimensioned to mitigate faults of up to 5 MeV, consistently ensuring 100% robustness across all designs where it was applied.

The electrical simulation results are organized in

Table 2. LETth analysis in each mitigation technique (values in MeV). The average values that reach 5 MeV are highlighted in green.

Design	MT	Input Vector								Achieved (%)
		000	001	010	011	100	101	110	111
V1, V2, V3 V6	MUX	1.21	1.21	1.11	1.11	1.21	1.11	1.21	1.11	0
	X2	2.49	2.49	2.28	2.28	2.49	2.28	2.49	2.28	0
	X4	5.05	5.05	4.61	4.61	5.05	4.61	5.05	4.61	50
	DC	1.40	1.40	1.30	1.30	1.40	1.30	1.40	1.30	0
	X2 + DC	2.64	2.64	2.43	2.43	2.64	2.43	2.64	2.43	0
	X4 + DC	5.18	5.18	4.74	4.74	5.18	4.74	5.18	4.74	50
V4	MUX	1.79	1.37	1.08	1.10	1.69	1.10	1.37	1.11	0
	X2	3.60	2.74	2.15	2.20	3.56	2.20	2.74	2.22	0
	X4	7.23	5.49	4.31	4.38	7.13	4.39	5.49	4.43	50
	DC	1.95	1.52	1.21	1.26	1.95	1.27	1.54	1.28	0
	X2 + DC	3.76	2.90	2.32	2.36	3.73	2.36	2.91	2.38	0
	X4 + DC	7.37	5.65	4.47	4.54	7.29	4.54	5.65	4.58	50
V5	MUX	1.35	1.35	1.12	1.12	1.35	1.13	1.35	1.13	0
	X2	2.71	2.71	2.29	2.29	2.71	2.31	2.71	2.31	0
	X4	5.43	5.43	4.63	4.63	5.42	4.70	5.43	4.69	50
	DC	1.51	1.51	1.28	1.28	1.50	1.29	1.51	1.29	0
	X2 + DC	2.86	2.86	2.44	2.36	2.87	2.47	2.87	2.45	0
	X4 + DC	5.54	5.57	4.75	4.76	5.57	4.80	5.58	4.80	50
V7	MUX	1.36	1.36	1.03	1.03	1.35	1.03	1.35	1.03	0
	X2	2.71	2.71	2.09	2.09	2.71	2.09	2.71	2.09	0
	X4	5.44	5.44	4.24	4.23	5.43	4.24	5.43	4.24	50
	DC	1.52	1.52	1.20	1.21	1.53	1.21	1.52	1.21	0
	X2 + DC	2.87	2.87	2.27	2.27	2.88	2.27	2.88	2.27	0
	X4 + DC	5.58	5.58	4.41	4.41	5.59	4.40	5.59	4.39	50
V8	MUX	1.78	1.36	1.03	1.03	1.75	1.03	1.35	1.03	0
	X2	3.59	2.71	2.08	2.08	3.54	2.09	2.71	2.09	0
	X4	7.20	5.44	4.19	4.19	7.08	4.24	5.44	4.24	50
	DC	1.94	1.52	1.52	1.20	1.94	1.20	1.53	1.21	0
	X2 + DC	3.74	2.87	2.25	2.25	3.71	2.26	2.88	2.27	0
	X4 + DC	7.34	5.59	4.36	4.38	7.25	4.43	5.59	4.39	50
V9	MUX	1.78	1.36	1.03	1.05	1.75	1.03	1.35	1.06	0
	X2	3.58	2.71	2.08	2.11	3.54	2.11	2.71	2.13	0
	X4	7.19	5.44	4.19	4.19	7.08	4.24	5.44	4.33	50
	DC	1.94	1.52	1.20	1.22	1.93	1.21	1.53	1.22	0
	X2 + DC	3.74	2.87	2.25	2.29	3.71	2.28	2.87	2.31	0
	X4 + DC	7.34	5.59	4.36	4.40	7.25	4.43	5.59	4.49	50
V10	MUX	1.38	1.36	1.03	1.03	1.38	1.03	1.36	1.02	0
	X2	2.76	2.71	2.10	2.08	2.76	2.10	2.71	2.10	0
	X4	5.52	5.44	4.24	4.24	5.52	4.24	5.44	4.22	50
	DC	1.52	1.52	1.20	1.21	1.55	1.21	1.53	1.20	0
	X2 + DC	2.91	2.87	2.27	2.26	2.91	2.27	2.88	2.26	0
	X4 + DC	5.67	5.59	4.40	4.37	5.69	4.43	5.61	4.38	50

. The first column indicates the multiplexer design, the second is the fault mitigation technique (MT) used, and the third is divided into the eight input vectors, with their respective LETth values. The last column is the percentage of vectors that presented a LETth value higher than our 5 MeV threshold. To calculate the percentage, the total number of vectors that reached 5 MeV is considered and divided by the total number of vectors, which, in the case of the 2:1 MUX, is eight. Values that meet the 5 MeV target in Table 2 are highlighted in green. It is important to note that designs V1, V2, V3, and V6 exhibit identical radiation response characteristics due to the presence of an inverter connected to the output of each circuit. As a result of their equivalent behavior under radiation, these designs were grouped into a single row in the table to simplify visualization and comparison.

The results demonstrate that the mitigation techniques consistently improve LETth values across all designs. The most significant enhancements come from transistor sizing approaches, as the X2 and X4 variants. While the standalone D-Cell technique provides modest improvements, with a LETth increase of approximately 10%, its combination with transistor sizing yields substantially better coverage, particularly in designs V4 and V8, which show the most pronounced benefits. When analyzing the input vectors in Table 2, it is clear that for input vectors 010, 011, 101, and 111, no mitigation technique was able to make a circuit robust to 5 MeV; that is, since these input vectors lead to an output logic “1”, these circuits are more sensitive to N-hit faults.

The techniques that stood out were X4 and X4 + DC, as they achieved the target in almost all designs. Design V4 was the only CMOS design that presented a LETth greater than 7 MeV in both mitigation techniques. In the circuits developed in DCVSL (V7 to V10), all designs achieved the target for four input vector combinations: 000, 001, 100, and 110. Circuits V8 and V9 stand out, as they presented a LETth greater than 7 MeV in two vectors, considering the X4 and X4 + DC mitigation techniques.

After organization, the lowest LETth value was identified, called critical LETth, and the arithmetic mean, standard deviation, and percentage of difference between the critical LETth and the circuit mean, called % Diff in

Table 3. LET statistics for each mitigation technique.The average values that reach 5 MeV are highlighted in green.

Design	MT	LET Min	Mean	Std Dev	% Diff
V1, V2, V3 V6	MUX	1.11	1.16	0.06	4.76
	X2	2.28	2.39	0.11	4.63
	X4	4.61	4.83	0.23	4.69
	DC	1.30	1.35	0.06	4.07
	X2 + DC	2.43	2.53	0.11	4.35
	X4 + DC	4.74	4.96	0.24	4.68
V4	MUX	1.08	1.33	0.29	23.16
	X2	2.15	2.68	0.61	24.26
	X4	4.31	5.22	1.27	21.29
	DC	1.21	1.50	0.31	23.37
	X2 + DC	2.32	2.84	0.61	22.33
	X4 + DC	4.47	5.51	1.23	23.40
V5	MUX	1.12	1.24	0.12	10.61
	X2	2.29	2.51	0.22	9.45
	X4	4.63	5.04	0.41	8.83
	DC	1.28	1.39	0.12	9.19
	X2 + DC	2.36	2.65	0.23	12.00
	X4 + DC	4.75	5.17	0.42	8.92
V7	MUX	1.03	1.20	0.17	15.56
	X2	2.09	2.40	0.33	14.90
	X4	4.23	4.84	0.64	14.25
	DC	1.20	1.37	0.17	13.60
	X2 + DC	2.27	2.57	0.32	13.37
	X4 + DC	4.39	5.00	0.63	13.79
V8	MUX	1.03	1.30	0.32	25.51
	X2	2.08	2.61	0.65	25.57
	X4	4.19	5.25	1.28	25.35
	DC	1.20	1.51	0.30	25.44
	X2 + DC	2.25	2.78	0.64	23.53
	X4 + DC	4.36	5.42	1.27	24.27
V9	MUX	1.03	1.30	0.32	25.89
	X2	2.08	2.62	0.64	26.08
	X4	4.19	5.26	1.27	25.57
	DC	1.20	1.47	0.32	22.48
	X2 + DC	2.25	2.79	0.63	24.06
	X4 + DC	4.36	5.43	1.26	24.61
V10	MUX	1.02	1.20	0.18	17.40
	X2	2.08	2.41	0.34	16.12
	X4	4.22	4.86	0.66	15.06
	DC	1.20	1.37	0.17	13.82
	X2 + DC	2.26	2.58	0.34	14.19
	X4 + DC	4.37	5.02	0.67	14.82

, were calculated. The average values that reach 5 MeV are highlighted in green.

To complement the presented data in Table 2, the statistics in Table 3 confirm that the mitigation techniques as effective as the C-Element are X4 and X4 + DC. This conclusion is drawn not only from an analysis of their average values but also from the critical LETth values of these techniques, which closely approach the objective.

The output inverter designs (V1, V2, V3, and V6) demonstrated consistent performance. This performance was accompanied by low standard deviation and percentage difference between the critical value and the overall average. When analyzing the X4 technique alone, a difference of only 4.69% was observed between the critical LETth and the average, a particularly positive result, since this configuration achieved the target in 50% of the input vectors.

In contrast, the designs implemented in DCVSL (V8 and V9), although exceeding the established threshold, presented a significant discrepancy between the critical LETth and the overall circuit average, over 20%, as evidenced by the high standard deviation values.

Figure 13 presents the normalization ratio in the traditional scenario for the LETth of each input vector. The LETth values are normalized relative to those of the designs with an inverter at the output (V1, V2, V3, and V6), as these designs exhibited the lowest standard deviation. The normalization was performed by dividing the LETth value of each design operating under normal conditions by the corresponding LETth value from design V1, V2, V3, or V6 with the same mitigation technique and input vector. For example, as shown in Table 2, the LETth value for the MUX configuration in V4, input vector 000, is 1.79 MeV, while for V1–V3 and V6, it is 1.11 MeV, resulting in a normalization ratio of 1.48. This approach highlights the relative robustness among designs, allowing for the identification and analysis of critical behavior in specific input vectors under standard operation. It is important to highlight that this pattern of robustness observed under the standard condition persists even when mitigation techniques are applied.

4.2. Power Consumption Impact

The energy consumption data for each project in each scenario are presented in

Table 4. Power consumption for nominal (MUX) circuits and with the evaluated mitigation approaches.

Design	Power Consumption ($\mathit{fW}$)
	MUX	CE	DC	X2	X4	X2 + DC	X4 + DC
V1	49	271	113	85	156	149	221
V2	49	272	113	86	159	150	223
V3	48	271	112	84	162	148	219
V4	62	297	126	112	211	176	275
V5	49	284	113	86	159	150	224
V6	68	290	132	125	239	189	303
V7	99	321	207	174	323	286	438
V8	101	325	206	180	336	288	446
V9	101	325	206	180	337	288	447
V10	93	322	200	163	301	272	413

. The “MUX” column represents the traditional consumption of the respective project without the application of techniques, while the others present the results for each mitigation approach individually. In Figure 14 the power consumption results normalized by the traditional power consumption are presented. A value of 1.00 indicates that the technique has the same consumption as the traditional configuration, and higher values indicate a proportional increase in consumption. It compares the impact of each technique relative to the traditional behavior of each multiplexer design in Figure 7.

As demonstrated in Table 4, the technique that least influenced power consumption for all designs is X2 sizing, followed by D-Cells, especially in designs V4 and V6. These results are confirmed by the graph in Figure 14. In contrast, the combined X4 + DC technique had a more significant impact on power consumption in all designs, especially those developed in CMOS, presenting an increase approximately 4.5x greater than traditional consumption, as shown in Figure 14. The C-Element also had a significant impact, but only the CMOS logic style was more affected, reaching 5.76x greater power consumption in design V5.

The designs projected in DCVSL (V7 to V10) presented high consumption in their traditional configurations and were also strongly impacted by the X4 + DC technique, with values close to 450 $fW$ in designs V8 and V9. Design V7 presented similar consumption between the C-Element and X4 sizing techniques. Designs V8 and V9 presented virtually identical behavior across all techniques. Finally, design V10 was the only DCVSL design in which consumption with the C-Element technique was higher than that with X4.

4.3. Delay Impact

Table 5. Delay results for each design.

Design	Delay (ps)
	MUX	CE	X2	X4	DC	X2 + DC	X4 + DC
V1	21.99	156.84	18.20	16.30	40.84	27.92	21.36
V2	21.57	156.61	17.77	15.88	40.63	27.62	20.93
V3	21.51	156.47	18.01	15.82	40.63	27.62	20.93
V4	19.13	165.10	15.98	14.49	38.83	25.58	18.92
V5	18.12	162.44	15.43	13.89	36.31	23.84	18.21
V6	28.36	163.76	25.26	23.57	47.16	34.05	28.14
V7	26.56	169.82	22.01	19.51	60.20	39.10	27.90
V8	28.45	171.81	22.06	19.73	61.41	40.21	27.50
V9	27.18	171.05	21.36	19.04	58.91	38.27	26.76
V10	26.86	169.36	22.70	20.15	60.03	38.35	28.84

presents the average propagation delay values for each design for all fault mitigation techniques. Figure 15 presents a comparative bar chart illustrating the average propagation delay for each circuit under different techniques, normalized to the propagation delays of each traditional multiplexer design. The first column corresponds to the baseline implementation without any mitigation, serving as a reference point. The subsequent columns display the delay introduced by each individual hardening technique.

The C-Element is the technique that most negatively impacts performance, due to the intrinsic need for a delay block in its structure. However, its impact is even greater in static CMOS circuits, especially in designs V4 and V5, where the impact was over 850%. In contrast, design V6 suffered the least in terms of its traditional performance of all the circuits. One reason for design V6’s behavior is that it is a multi-stage multiplexer and has an inverter at the output. In other words, it gains performance by removing the inverter, and the delays relative to each input are less affected.

The techniques that use only transistor scaling, X2 and X4, were the most beneficial, improving the performance of all the multiplexers. This is an expected result considering their structure. The D-Cells had a significant impact on all the projects, especially those developed in DCVSL, increasing the propagation delay by more than 220%. Furthermore, it is relevant to note that the X4 + DC technique, combining techniques with complementary characteristics, had practically zero impact on performance.

4.4. Area Impact

Table 6. Area impact for nominal (MUX) circuits and with the evaluated mitigation approaches.

Designs	Area ($\mu$m)
	MUX	CE	DC	X2	X4	X2 + DC	X4 + DC
V1	1750	4725	4950	3500	7000	6700	10,200
V2	1750	4725	4950	3500	7000	6700	10,200
V3	1750	4725	4950	3500	7000	6700	10,200
V4	1925	5250	5125	3850	7700	7050	10,900
V5	1645	4970	4845	3290	6580	6490	9780
V6	2240	5215	5440	4480	8960	7680	12,160
V7	1855	5180	5055	3710	7420	6910	10,620
V8	1855	5180	5055	3710	7420	6910	10,620
V9	1855	5180	5055	3710	7420	6910	10,620
V10	1575	4900	4775	3150	6300	6350	9500

presents the estimated area values for each design and mitigation technique. Figure 16 complements this information by providing a bar chart normalized by the initial area of each design, highlighting the area impact of each mitigation technique. As described in the methodology, the area values are estimates, obtained by summing the W parameters of the transistors present in each design. It is possible to observe that the C-Element and D-Cell presented a very similar area cost; that is, the area cost of the buffers was practically equivalent to the area cost of adding the D-Cell transistors. The technique that had the least impact on the circuits was X2 sizing, only doubling the cost, as expected. The X4 and X4 + DC transistor sizing techniques had the greatest impact on the area of all the circuits; increasing the size of all the transistors combined with a capacitive technique will have a very high area cost.

Design V6, despite being the largest because it had the most transistors, was the one with the smallest impact in terms of area. In contrast, design V10 had the smallest area and was the one most impacted by the X4 + DC technique.

In contrast, the X2 sizing technique had the smallest impact on area for all designs. However, when this approach was combined with the DC technique, X2 + DC, it was observed that it presented an area cost comparable to X4 sizing alone. This correspondence is particularly evident in design V10, where both techniques showed almost identical values of area.

The insertion of the C-Element had a fixed cost in area, as the same number of buffers and the same comparator block were used, varying only with the insertion or removal of an inverter. The circuits developed in DCVSL presented a similar area impact for the C-Element and D-Cell techniques compared with the static CMOS circuits.

5. Overall Trade-Off Discussion

The tolerance of certain design features depends on the objectives of each application. This section discusses the optimal combination of designs and fault mitigation strategies, considering scenarios in which power, delay, and area can be tolerated. The comprehensive evaluation of these fault mitigation techniques for 2:1 multiplexers reveals a complex design challenge to observe the trade-offs among radiation robustness, power consumption, propagation delay, and area overhead. The selection of a design strategy is inherently a trade-off, dictated by the specific requirements of the target application.

The C-Element technique demonstrates the highest level of radiation robustness across all evaluated designs. This resilience to the adopted intensity of simulated transient faults (5 MeV) comes at a significant cost. Its implementation degrades the propagation delay by over 850% and power consumption by up to 5.76 times compared with the nominal circuits. Area overhead is also notable, though less critical than the performance and power penalties. Therefore, the C-Element is ideally suited for ultra-critical applications where uninterrupted operation in harsh radiation environments is paramount and the system architecture can inherently tolerate considerable power and performance degradation. Examples include deep-space exploration systems or life-support critical medical devices, where reliability supersedes all other metrics.

Conversely, the standalone Decoupling Cell (D-Cell) technique offers only marginal improvements in LETth, approximately 10%. While it exhibits a low impact on propagation delay, its limited effectiveness in fault mitigation makes it an unsuitable primary hardening solution for radiation-sensitive applications.

Transistor sizing presents a more nuanced set of trade-offs. The X2 sizing variant provides beneficial effects on performance, making circuits faster, and has the least impact on power consumption and area among the evaluated techniques. However, its robustness enhancement is insufficient to meet the 5 MeV threshold, rendering it inadequate for applications demanding high radiation tolerance. This approach might be considered for performance-driven application where only a minor, non-critical improvement in inherent robustness is enough.

The X4 sizing technique offers a more substantial increase in LETth, achieving the 5 MeV target for a significant portion of input vectors in several designs. While it also contributes to improved propagation delay, this enhancement is accompanied by an increase in both power consumption and area overhead. This technique is a viable option for applications requiring a moderate level of radiation hardening with a focus on performance, provided that the power and area budgets are flexible enough to accommodate the increased resource utilization.

The combined mitigation strategies reveal compelling solutions. The X2 + DC combination, despite integrating two techniques, fails to achieve the robustness target. Furthermore, it introduces significant penalties, nearly doubling the power consumption of the X2-only approach and increasing the area while also making circuits slower. Consequently, this combination is generally not recommended due to its unfavorable trade-off balance.

In contrast, the X4 + DC technique emerges as the most balanced and effective solution for a wide range of radiation-sensitive applications. This combination consistently achieves the LETth target across designs. The synergistic interaction between X4 sizing and the D-Cell ensures that high performance can be maintained alongside robust radiation tolerance. The primary trade-offs for X4 + DC are its increased power consumption and area. Therefore, this approach is recommended for high-performance, radiation-hardened applications where a strong emphasis is placed on maintaining speed and functionality in harsh environments and the system can accommodate the increased power and area footprints. Examples include high-speed data processing units in aerospace systems or critical control logic in nuclear facilities.

6. Conclusions

This article presents a discussion about approaches to increasing the robustness of the 2:1 multiplexer designs up to a threshold of 5 MeV. During the analysis, we consider the application of three faults mitigation techniques at the circuit level, C-Element, D-Cell, and transistor sizing, observing the robustness to SET and also the drawbacks, i.e., the impacts on power consumption, delay, and area cost parameters. For this purpose, ten 2:1 multiplexer designs were chosen from [11,30], covering the static CMOS and DCVSL logic styles, which are recognized for their low power consumption characteristics.

Regarding robustness, the C-Element stands out as the most effective technique for mitigating transient faults, as long as these faults are restricted to the temporal pre-filtering block. However, its implementation has a considerable negative impact on propagation delay and power consumption. Although the impact on the area is not critical, it is still strongly related to the delay block.

The D-Cell technique shows a low impact on propagation delay. However, it is not effective in mitigating transient faults, presenting only an improvement of 10% compared with the traditional circuit robustness, at a moderate area cost.

The transistor sizing technique presents more interesting results. For X2 sizing, the impacts on power and delay are 1.77x and 0.8x respectively, making the circuits faster. However, like the D-Cell, it is not efficient in mitigating failures, either in the average behavior or in the input vector analysis. By combining X2 + DC, the behavior changes. The addition of the D-Cell almost doubles the power consumption, makes the circuits slower, and increases the area, without any circuit reaching the 5 MeV target.

Our analysis demonstrates that X4 and X4 + DC transistor sizing impact power and area characteristics across all multiplexer designs while emerging as the only viable solutions, besides the C-Element, capable of meeting the stringent 5 MeV threshold. However, it is important to highlight that for the X4 + DC technique, the impact on the delay is nullified, due to the characteristics of each technique. These findings confirm X4 + DC as the most balanced hardening approach for radiation-sensitive applications where performance cannot be compromised.

Notably, while the LETth response is uniform among inverter-based designs (V1, V2, V3, V6), their area, power, and delay vary substantially, emphasizing the importance of considering all design parameters in optimization. The standout performer is design V5, which consistently achieves superior robustness, setting it apart as the reference implementation for robust multiplexer design under radiation constraints. These findings suggest that particularly when using X4 + DC, designers can reach the required tolerance levels while balancing power and area costs. Designs V4, V8, and V9 exhibit a considerably higher standard deviation in LETth values across the different input vectors, as highlighted in Table 3. This large variability indicates that the radiation robustness of these circuits is highly dependent on the specific input vector being applied. As a result, these designs are not suitable alternatives in scenarios where the input vector probability distribution deviates from the typical assumption of uniform (50%) probability. In practical applications where certain input vectors may occur more frequently or are more critical, choosing designs with more consistent LETth behavior—such as V5—ensures more reliable and predictable radiation tolerance.

While designs V1–V3 and V6 failed to meet radiation targets, they revealed crucial insights about inverter vulnerability that will guide future work. Our ongoing research focuses on two key advancements: (1) developing asymmetric sizing approaches specifically for output inverter structures and (2) evaluating layout-level optimization including Enclosed Layout Transistors (ELTs) for enhanced radiation tolerance. These developments will address the current limitations while advancing toward radiation-hardened multiplexers capable of meeting the extreme demands of next-generation space electronics. The foundational results presented here establish critical benchmarks for these forthcoming innovations in radiation-hardened IC design.