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Micromachines
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III–V Compound Semiconductors and Devices, 2nd Edition
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III–V Compound Semiconductors and Devices, 2nd Edition

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "D1: Semiconductor Devices".

Deadline for manuscript submissions: 28 February 2026 | Viewed by 4913

Special Issue Editors

Prof. Dr. Yeong-Her Wang

E-Mail Website
Guest Editor
Institute of Microelectronics, National Cheng Kung University, Tainan 70101, Taiwan
Interests: semiconductor devices and physics
Special Issues, Collections and Topics in MDPI journals
Prof. Dr. Kuan-Wei Lee

E-Mail Website
Guest Editor
Department of Electronic Engineering, I-Shou University, Kaohsiung 84001, Taiwan
Interests: metal-oxide-semiconductor technology; high-speed semiconductor devices; semiconductor manufacturing technology
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Compared to silicon technology, III-V compound semiconductors and their applications have attracted considerable attention for use in many different circuits such as power amplifiers, low-noise amplifiers, mixers, frequency converters, phase shifters, and optoelectronics.

This Special Issue of Micromachines aims to present recent advantages in the fabrication, characterization, and modeling of electron devices based on III-V compound semiconductors and devices. The scope of this Special Issue includes, but is not limited to:

  • Characterization techniques for defects in high-k dielectrics/III-V semiconductors.
  • Novel methods or concepts for III-V devices (e.g., HBT, field-effect transistors, nanowires, or gate-all-around).
  • Electronic or optoelectronic applications for III-V devices (including physical, chemical, and electronic properties).
  • Advanced fabrication processes for III-V on insulator (e.g., GaN on silicon or III-V on silicon).
  • Advanced simulation or modeling of III-V devices.

Prof. Dr. Yeong-Her Wang
Prof. Dr. Kuan-Wei Lee
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Micromachines is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2100 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • compound semiconductor
  • high-k dielectric
  • insulator
  • frequency
  • optoelectronic

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Related Special Issue

Published Papers (4 papers)

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Research

13 pages, 2826 KiB  
Article
Design and Application of p-AlGaN Short Period Superlattice
by Yang Liu, Changhao Chen, Xiaowei Zhou, Peixian Li, Bo Yang, Yongfeng Zhang and Junchun Bai
Micromachines 2025, 16(8), 877; https://doi.org/10.3390/mi16080877 - 29 Jul 2025
Viewed by 329
Abstract
AlGaN-based high-electron-mobility transistors are critical for next-generation power electronics and radio-frequency applications, yet achieving stable enhancement-mode operation with a high threshold voltage remains a key challenge. In this work, we designed p-AlGaN superlattices with different structures and performed energy band structure simulations using [...] Read more.
AlGaN-based high-electron-mobility transistors are critical for next-generation power electronics and radio-frequency applications, yet achieving stable enhancement-mode operation with a high threshold voltage remains a key challenge. In this work, we designed p-AlGaN superlattices with different structures and performed energy band structure simulations using the device simulation software Silvaco. The results demonstrate that thin barrier structures lead to reduced acceptor incorporation, thereby decreasing the number of ionized acceptors, while facilitating vertical hole transport. Superlattice samples with varying periodic thicknesses were grown via metal-organic chemical vapor deposition, and their crystalline quality and electrical properties were characterized. The findings reveal that although gradient-thickness barriers contribute to enhancing hole concentration, the presence of thick barrier layers restricts hole tunneling and induces stronger scattering, ultimately increasing resistivity. In addition, we simulated the structure of the enhancement-mode HEMT with p-AlGaN as the under-gate material. Analysis of its energy band structure and channel carrier concentration indicates that adopting p-AlGaN superlattices as the under-gate material facilitates achieving a higher threshold voltage in enhancement-mode HEMT devices, which is crucial for improving device reliability and reducing power loss in practical applications such as electric vehicles. Full article
(This article belongs to the Special Issue III–V Compound Semiconductors and Devices, 2nd Edition)
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12 pages, 3788 KiB  
Article
On-Wafer Gate Screening Test for Improved Pre-Reliability in p-GaN HEMTs
by Giovanni Giorgino, Cristina Miccoli, Marcello Cioni, Santo Reina, Tariq Wakrim, Virgil Guillon, Nossikpendou Yves Sama, Pauline Gaillard, Mohammed Zeghouane, Hyon-Ju Chauveau, Maria Eloisa Castagna, Aurore Constant, Ferdinando Iucolano and Alessandro Chini
Micromachines 2025, 16(8), 873; https://doi.org/10.3390/mi16080873 - 29 Jul 2025
Viewed by 491
Abstract
In this paper, preliminary gate reliability of p-GaN HEMTs under high positive gate bias is studied. Gate robustness is of great interest both from an academic and industrial point of view; in fact, different tests and models can be explored to estimate the [...] Read more.
In this paper, preliminary gate reliability of p-GaN HEMTs under high positive gate bias is studied. Gate robustness is of great interest both from an academic and industrial point of view; in fact, different tests and models can be explored to estimate the device lifetime, which must meet some minimum product requirements, as specified by international standards (AEC Q101, JESD47, etc.). However, reliability characterizations are usually time-consuming and are performed in parallel on multiple packaged devices. Therefore, it would be useful to have a faster method to screen out weaker gate trials, already on-wafer, before reaching the packaging step. For this purpose, a room-temperature stress procedure is presented and described in detail. Then, this screening test is applied to devices with a reference gate process, and, as a result, high gate leakage degradation is observed. Afterwards, a different process implementing a dielectric layer between p-GaN and gate metal is evaluated, highlighting the improved behavior during the stress test. However, it is also observed that devices with this process suffer from very high drain leakage, and this effect is then studied and understood through TCAD (technology computer-aided design) simulations. Finally, the effect of a surface treatment performed on the p-GaN is analyzed, showing improved gate pre-reliability while maintaining low drain leakage. Full article
(This article belongs to the Special Issue III–V Compound Semiconductors and Devices, 2nd Edition)
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13 pages, 2510 KiB  
Article
A High-Performance InGaAs Vertical Electron–Hole Bilayer Tunnel Field Effect Transistor with P+-Pocket and InAlAs-Block
by Hu Liu, Peifeng Li, Xiaoyu Zhou, Pengyu Wang, Yubin Li, Lei Pan, Wenting Zhang and Yao Li
Micromachines 2023, 14(11), 2049; https://doi.org/10.3390/mi14112049 - 31 Oct 2023
Cited by 3 | Viewed by 1518
Abstract
To give consideration to both chip density and device performance, an In0.53Ga0.47As vertical electron–hole bilayer tunnel field effect transistor (EHBTFET) with a P+-pocket and an In0.52Al0.48As-block (VPB-EHBTFET) is introduced and systematically studied by [...] Read more.
To give consideration to both chip density and device performance, an In0.53Ga0.47As vertical electron–hole bilayer tunnel field effect transistor (EHBTFET) with a P+-pocket and an In0.52Al0.48As-block (VPB-EHBTFET) is introduced and systematically studied by TCAD simulation. The introduction of the P+-pocket can reduce the line tunneling distance, thereby enhancing the on-state current. This can also effectively address the challenge of forming a hole inversion layer in an undoped InGaAs channel during device fabrication. Moreover, the point tunneling can be significantly suppressed by the In0.52Al0.48As-block, resulting in a substantial decrease in the off-state current. By optimizing the width and doping concentration of the P+-pocket as well as the length and width of the In0.52Al0.48As-block, VPB-EHBTFET can obtain an off-state current of 1.83 × 10−19 A/μm, on-state current of 1.04 × 10−4 A/μm, and an average subthreshold swing of 5.5 mV/dec. Compared with traditional InGaAs vertical EHBTFET, the proposed VPB-EHBTFET has a three orders of magnitude decrease in the off-state current, about six times increase in the on-state current, 81.8% reduction in the average subthreshold swing, and stronger inhibitory ability on the drain-induced barrier-lowering effect (7.5 mV/V); these benefits enhance the practical application of EHBTFETs. Full article
(This article belongs to the Special Issue III–V Compound Semiconductors and Devices, 2nd Edition)
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16 pages, 4084 KiB  
Article
An Aging Small-Signal Model for Degradation Prediction of Microwave Heterojunction Bipolar Transistor S-Parameters Based on Prior Knowledge Neural Network
by Lin Cheng, Hongliang Lu, Silu Yan, Chen Liu, Jiantao Qiao, Junjun Qi, Wei Cheng, Yimen Zhang and Yuming Zhang
Micromachines 2023, 14(11), 2023; https://doi.org/10.3390/mi14112023 - 30 Oct 2023
Viewed by 1704
Abstract
In this paper, an aging small-signal model for degradation prediction of microwave heterojunction bipolar transistor (HBT) S-parameters based on prior knowledge neural networks (PKNNs) is explored. A dual-extreme learning machine (D-ELM) structure with an adaptive genetic algorithm (AGA) optimization process is used [...] Read more.
In this paper, an aging small-signal model for degradation prediction of microwave heterojunction bipolar transistor (HBT) S-parameters based on prior knowledge neural networks (PKNNs) is explored. A dual-extreme learning machine (D-ELM) structure with an adaptive genetic algorithm (AGA) optimization process is used to simulate the fresh S-parameters of InP HBT devices and the degradation of S-parameters after accelerated aging, respectively. In addition to the reliability parametric inputs of the original aging problem, the S-parameter degradation trend obtained from the aging small-signal equivalent circuit is used as additional information to inject into the D-ELM structure. Good agreement was achieved between measured and predicted results of the degradation of S-parameters within a frequency range of 0.1 to 40 GHz. Full article
(This article belongs to the Special Issue III–V Compound Semiconductors and Devices, 2nd Edition)
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