Single-Event Effects: Modeling, Prediction, Testing and Radiation Hardening

A special issue of Electronics (ISSN 2079-9292).

Deadline for manuscript submissions: 16 June 2025 | Viewed by 1161

Special Issue Editors


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Guest Editor
CERN, CH-1211 Genève, Switzerland
Interests: soft errors; radiation-hardening-by-design (RHBD) techniques; prediction methods; Monte Carlo; dosimetry

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Guest Editor
Advanced Power Semiconductor Laboratory (APS), ETH Zurich, Physikstrasse 3, 8092 Zürich, Switzerland
Interests: wide-bandgap power devices; basic mechanisms; single-event effects; total ionizing dose; displacement damage

Special Issue Information

Dear Colleagues,

Single-event effects (SEEs), caused by high-energy particles, pose significant challenges to the reliability and safety of electronic systems in both space and terrestrial environments. Traditionally, research in SEEs has focused on soft errors such as single-event upsets (SEUs), single-event transients (SETs), and single-event functional interrupts (SEFIs). However, with the scaling of semiconductor technologies, the use of wide-bandgap semiconductors, and the increasing complexity of applications—from space exploration to autonomous cars—other critical effects, such as single-event latch-up (SEL), single-event burnout (SEB), single-event gate rupture (SEGR), and single-event leakage current (SELC), are becoming equally significant and require novel approaches in modeling, prediction, testing, and mitigation.

This Special Issue aims to gather high-quality submissions that address both fundamental and advanced topics in SEE research, with a focus on comprehensive methodologies for modeling, prediction, testing, and hardening. SEEs will be explored across a wide range of applications and technology platforms, from traditional space systems to emerging ground-level environments, like autonomous vehicles, high-performance computing, medical devices, and particle accelerators. Additionally, this Special Issue will highlight new approaches in alternative SEE testing methodologies—using tools like lasers and high-energy heavy ions—and discuss the challenges in the radiation monitoring and dosimetry needs involved in ensuring accurate SEE characterization and rate prediction. The topics of interest include, but are not limited to, the following:

  • Modeling and prediction of single-event effects:
    • Mechanisms of soft errors (SEUs, SETs, and SEFIs);
    • Mechanisms of destructive effects (SEL, SEB, SEGR, and SELC);
    • Simulation and prediction tools.
  • Experimental characterization of single-event effects in the following:
    • Advanced technologies (FinFETs, GAA, etc.);
    • Mixed-signal, RF, power, and digital circuits (such as radar circuits, RISC-V processors, and custom SoC designs).
  • Testing methodologies:
    • Alternative SEE testing methods, such as laser testing, mixed-field, and high-energy heavy-ion irradiation;
    • Innovations in SEE test facilities, including the calibration of ion beams and the related radiation monitoring as well as dosimetry.
  • Radiation-hardening-by-design (RHBD) techniques:
    • Novel layout-level hardening techniques;
    • Novel circuit-level hardening techniques;
    • Novel system-level hardening techniques;
    • Design automation tools for integrating radiation-hardened techniques into advanced ICs and system-on-chip designs.
  • Radiation-hardening-by-process (RHBP) techniques:
    • Innovations in device-level hardening by using materials and novel architectures that exhibit natural SEE resilience.
  • Single-event effects in disruptive technologies like quantum computing, silicon photonics, and AI-driven applications.

Dr. Ygor Aguiar
Dr. Corinna Martinella
Guest Editors

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Keywords

  • single-event effects
  • soft errors
  • SEE modeling and prediction
  • wide-bandgap semiconductors
  • radiation testing
  • hardening techniques

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Published Papers (3 papers)

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Research

16 pages, 4344 KiB  
Article
Ion-Induced Charge and Single-Event Burnout in Silicon Power UMOSFETs
by Saulo G. Alberton, Vitor A. P. Aguiar, Nemitala Added, Alexis C. Vilas-Bôas, Marcilei A. Guazzelli, Jeffery Wyss, Luca Silvestrin, Serena Mattiazzo, Matheus S. Pereira, Saulo Finco, Alessandro Paccagnella and Nilberto H. Medina
Electronics 2025, 14(11), 2288; https://doi.org/10.3390/electronics14112288 - 4 Jun 2025
Viewed by 7
Abstract
The U-shaped Metal-Oxide-Semiconductor Field-Effect Transistor (UMOS or trench FET) is one of the most widely used semiconductor power devices worldwide, increasingly replacing the traditional vertical double-diffused MOSFET (DMOSFET) in various applications due to its superior electrical performance. However, a detailed experimental comparison of [...] Read more.
The U-shaped Metal-Oxide-Semiconductor Field-Effect Transistor (UMOS or trench FET) is one of the most widely used semiconductor power devices worldwide, increasingly replacing the traditional vertical double-diffused MOSFET (DMOSFET) in various applications due to its superior electrical performance. However, a detailed experimental comparison of ion-induced Single-Event Burnout (SEB) in similarly rated silicon (Si) UMOS and DMOS devices remains lacking. This study presents a comprehensive experimental comparison of ion-induced charge collection mechanisms and SEB susceptibility in similarly rated Si UMOS and DMOS devices. Charge collection mechanisms due to alpha particles from 241Am radiation source are analyzed, and SEB cross sections induced by heavy ions from particle accelerators are directly compared. The implications of the unique gate structure of Si UMOSFETs on their reliability in harsh radiation environments are discussed based on technology computer-aided design (TCAD) simulations. Full article
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19 pages, 4988 KiB  
Article
Analysis of the SEU Tolerance of an FPGA-Based Time-to-Digital Converter Using Emulation-Based Fault Injection
by Roza Teklehaimanot Siecha, Getachew Alemu, Jeffrey Prinzie and Paul Leroux
Electronics 2025, 14(11), 2176; https://doi.org/10.3390/electronics14112176 - 27 May 2025
Viewed by 146
Abstract
In application domains where severe environmental conditions are unavoidable, including high-energy physics and nuclear power plants, accurate and dependable time-to-digital converters (TDCs) are essential components. Single-event upsets (SEUs) associated with the configuration memory of field-programmable gate array (FPGA)-based implementations are becoming common sources [...] Read more.
In application domains where severe environmental conditions are unavoidable, including high-energy physics and nuclear power plants, accurate and dependable time-to-digital converters (TDCs) are essential components. Single-event upsets (SEUs) associated with the configuration memory of field-programmable gate array (FPGA)-based implementations are becoming common sources of performance degradation even in terrestrial areas. Hence, the need to test and mitigate the effects of SEUs on FPGA-based TDCs is crucial to ensure that the design achieves reliable performance under critical conditions. The TMR SEM IP provides real-time fault injection, and dynamic SEU monitoring and correction in safety critical conditions without intervening with the functionality of the system, unlike traditional fault injection methods. This paper presents a scalable and fast fault emulation framework that tests the effects of SEUs on the configuration memory of a 5.7 ps-resolution TDC implemented on ZedBoard. The experimental results demonstrate that the standard deviation in mean bin width is 2.4964 ps for the golden TDC, but a 0.8% degradation in the deviation is observed when 3 million SEUs are injected, which corresponds to a 0.02 ps increment. Moreover, as the number of SEUs increases, the degradation in the RMS integral non-linearity (INL) of the TDC also increases, which shows 0.04 LSB (6.8%) and 0.05 LSB (8.8%) increments for 1 million and 3 million SEUs injected, respectively. The RMS differential non-linearity (DNL) of the faulty TDC with 3 million SEUs injected shows a 0.035 LSB (0.8%) increase compared to the golden TDC. Full article
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11 pages, 11863 KiB  
Article
Single-Event Upset Characterization of a Shift Register in 16 nm FinFET Technology
by Federico D’Aniello, Marcello Tettamanti, Syed Adeel Ali Shah, Serena Mattiazzo, Stefano Bonaldo, Valeria Vadalà and Andrea Baschirotto
Electronics 2025, 14(7), 1421; https://doi.org/10.3390/electronics14071421 - 31 Mar 2025
Viewed by 486
Abstract
Today, many electronic circuits are required to be able to work effectively, even in environments exposed to ionizing radiation. This work examines the effects of ionizing radiation on shift registers realized in a bulk 16 nm FinFET technology, focusing on Single-Event Upset (SEU). [...] Read more.
Today, many electronic circuits are required to be able to work effectively, even in environments exposed to ionizing radiation. This work examines the effects of ionizing radiation on shift registers realized in a bulk 16 nm FinFET technology, focusing on Single-Event Upset (SEU). An SEU occurs when a charged particle ionizes a sensitive node in the circuit, causing a stored bit to flip from one logical state to its opposite. This study estimates the saturation cross-section for the 16 nm FinFET technology and compares it with results from a 28 nm planar CMOS technology. The experiments were conducted at the SIRAD facility of INFN Legnaro Laboratories (Italy). The device under test was irradiated with the ion sources 58Ni and 28Si, both with different tilt angles, to assess the number of SEUs with different LET and range values. Additionally, the study evaluates the effectiveness of the radiation-hardened by design technique, specifically the Triple Modular Redundancy (TMR), which is a technique commonly employed in planar technologies. However, in this particular case study, TMR proved to be ineffective, and the reasons behind this limitation are analyzed along with potential improvements for future designs. Full article
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