GaN HEMT Oscillators with Buffers

Abstract

With their superior switching speed, GaN high-electron-mobility transistors (HEMTs) enable high power density, reduce energy losses, and increase power efficiency in a wide range of applications, such as power electronics, due to their high breakdown voltage. GaN-HEMT devices are subject to long-term reliability due to the self-heating effect and lattice mismatch between the SiC substrate and the GaN. Depletion-mode GaN HEMTs are utilized for radio frequency applications, and this work investigates three wide-bandgap (WBG) GaN HEMT fixed-frequency oscillators with output buffers. The first GaN-on-SiC HEMT oscillator consists of an HEMT amplifier with an LC feedback network. With the supply voltage of 0.8 V, the single-ended GaN oscillator can generate a signal at 8.85 GHz, and it also supplies output power of 2.4 dBm with a buffer supply of 3.0 V. At 1 MHz frequency offset from the carrier, the phase noise is −124.8 dBc/Hz, and the figure of merit (FOM) of the oscillator is −199.8 dBc/Hz. After the previous study, the hot-carrier stressed RF performance of the GaN oscillator is studied, and the oscillator was subject to a drain supply of 8 V for a stressing step time equal to 30 min and measured at the supply voltage of 0.8 V after the step operation for performance benchmark. Stress study indicates the power oscillator with buffer is a good structure for a reliable structure by operating the oscillator core at low supply and the buffer at high supply. The second balanced oscillator can generate a differential signal. The feedback filter consists of a left-handed transmission-line LC network by cascading three unit cells. At a 1 MHz frequency offset from the carrier of 3.818 GHz, the phase noise is −131.73 dBc/Hz, and the FOM of the 2nd oscillator is −188.4 dBc/Hz. High supply voltage operation shows phase noise degradation. The third GaN cross-coupled VCO uses 8-shaped inductors. The VCO uses a pair of drain inductors to improve the Q-factor of the LC tank, and it uses 8-shaped inductors for magnetic coupling noise suppression. At the VCO-core supply of 1.3 V and high buffer supply, the FOM at 6.397 GHz is −190.09 dBc/Hz. This work enhances the design techniques for reliable GaN HEMT oscillators and knowledge to design high-performance circuits.

1. Introduction

A Gallium Nitride (GaN) High Electron-Mobility Transistor (HEMT) has emerged as a potential high-power and high-speed transistor for commercial and military applications due to its superior material performance, such as a large bandgap, high saturation and peak velocity, and good thermal conductivity. GaN HEMTs offer comparable noise levels to conventional GaAs HEMT devices [1] and better noise figure compared to bipolar SiGe HBT and InGaP HBT [2]. A low-phase-noise oscillator is a key component of many radio-frequency communication systems, and the reliability of the oscillator helps the design of GaN HEMT circuits for high-power applications.

GaN HEMT oscillators can be designed with a GaN HEMT amplifier with a feedback network [3,4]. With the feedback method, the power amplifier and the oscillator are combined in one for low power consumption, and no buffer is used. But the output matching network may degrade the oscillator’s performance. On the other hand, an oscillator and a buffer form a composite high-power oscillator. The role of the buffer is to duplicate the low-phase signal from the core oscillator and provide large output power. The oscillator can use different supply voltages for the VCO core and the buffer for performance optimization. This paper studies three GaN HEMT oscillators with HEMT buffers. The first 0.25 μm GaN HEMT oscillator consists of a split core and a buffer, demonstrating the advantage of this design from the reliability point of view. The core oscillator is used to improve the phase noise at low supply voltage with high reliability.

Balanced oscillators [5,6] based on Colpitts oscillator topology have good phase noise performance. Secondly, this paper describes a balanced 0.25 μm GaN [7] oscillator with a left-handed transmission-line LC network as the high-pass feedback filter, which provides impedance matching and delay phase control. Cross-coupled GaN HEMT oscillators [8,9,10] are made of two HEMTs; the differential topology suppresses the substrate coupling effect. This third cross-coupled 0.12 μm GaN oscillator, embedded with an implicit harmonic LC network, improves the phase noise, and it uses 8-shaped inductors to suppress the magnetic coupling noise.

2. X-Band Feedback GaN HEMT Oscillator with Split Core and Buffer

2.1. Circuit Design of the First Oscillator

Figure 1a shows a feedback oscillator generating a periodic output Y without input X = 0. The feedback network circuit β is used to select the operation frequency. The circuit can oscillate if Barkhausen’s criteria |βH(jω_o)| = 1 and ∠βH(jω_o) = 0° hold. Figure 1b shows the schematic of the designed single-ended GaN HEMT oscillator. It consists of an oscillator and a buffer. The inductor L₃ and HEMT M₁ form an amplifier, and R₁ is a gate-biasing resistor, and V_G1 is the gate voltage. Inductors L₁ and L₂, capacitors C₁ and C_2, and the parasitic gate-source capacitor of M₁ form the feedback filter. V_DD is the supply voltage and is connected to the output node of L₃. The oscillator is used to drive the following buffer amplifier M₂. HEMT M₂ forms a buffer amplifier with gate bias at V_G2 through the gate-bias resistor R₂. V_B is the buffer drain bias through an external bias inductor L. With different V_DD and V_B, the oscillator can be optimized for low phase noise performance, and the buffer is used to output high power. M₁ and M₂ share the same substrate stray inductance; the current of M₂ affects the property of M₁. Figure 1c is the simplified small-signal equivalent circuit of the designed HEMT oscillator. C_gsb is the parasitic gate-source capacitor of buffer M₂. C_gs, C_ds, and C_gd are, respectively, the gate-source, drain-source, and gate-drain capacitors of M₁. These capacitors are bias-dependent. g_m is the transconductance of M₁, and g_d is the output conductance due to the effect of M₁ output conductance and other resistive losses. C₃ is ignored for simplicity. Minimum transconductance gain is given by

$${\mathrm{g}}_{\mathrm{m}}={\displaystyle \frac{{\omega }^2{L}_{21}{\mathrm{C}}_{x-1}}{{\mathrm{C}}_x/{\mathrm{C}}_{gs}}}{\mathrm{g}}_{\mathrm{d}}$$

(1)

$${\displaystyle \frac{1}{{\mathrm{C}}_x}}={\displaystyle \frac{1}{{\mathrm{C}}_{gs}}}+{\displaystyle \frac{1}{{\mathrm{C}}_1}}+{\displaystyle \frac{1}{{\mathrm{C}}_2}}, L_{21}=L_2+L_1$$

(2)

The small-signal model for the oscillator is used to derive the resonant frequency given by

$${\omega }^2={\displaystyle \frac{{\mathrm{C}}_x{\mathrm{L}}_3+{\mathrm{L}}_3{\mathrm{C}}_{gsb}+L_{21}{\mathrm{C}}_x}{{2\mathrm{L}}_3{\mathrm{C}}_{gsb}{L}_{21}{\mathrm{C}}_x}}+{\displaystyle \frac{\sqrt{{({\mathrm{C}}_x{\mathrm{L}}_3+{\mathrm{L}}_3{\mathrm{C}}_{gsb}+L_{21}{\mathrm{C}}_x)}^2-4{\mathrm{L}}_3{\mathrm{C}}_{gsb}{L}_{21}{\mathrm{C}}_x}}{{2\mathrm{L}}_3{\mathrm{C}}_{gsb}{L}_{21}{\mathrm{C}}_x}}$$

(3)

As V_DD increases, the voltage swing of V_o increases, and the average capacitance over an oscillation cycle changes. DC bias also changes the capacitance. The oscillation frequency is tunable by tuning V_DD. If L₃ is large, (3) simplifies to

$$\omega =\sqrt{{\displaystyle \frac{1}{L_{21}}}{\displaystyle \frac{{\mathrm{C}}_x+{\mathrm{C}}_{gsb}}{{\mathrm{C}}_{gsb}{\mathrm{C}}_x}}}$$

(4)

2.2. Measurement and Discussion

The first oscillators were designed and fabricated in the WIN 0.25 μm GaN/SiC HEMT process. Figure 2 shows the micrograph of the oscillator with a chip area of 2 × 1 mm², including all test pads and dummy metal. Foundry-supplied inductors are planar circular inductors featuring a high-Q factor. Figure 3 shows the measured output characteristics of the buffer HEMT. Figure 4a shows the measured expanded output spectrum. Figure 4b shows the measured full-span output spectrum of the fundamental signal at 8.86 GHz with an output power of 3.75 dBm. At V_DD = 0.8 V, the power consumption is 2.45 mW. The 2nd harmonic power is lower than the fundamental by 30.3 dB.

Figure 5 shows the measured phase noise performance of the oscillator. The phase noise of the oscillator is about −124.8 dBc/Hz at 1 MHz offset frequency from 8.86 GHz oscillation frequency and has a slope of −30 dB/dec in the low frequency offset. The phase noise is mainly due to the upconversion of device flicker current noise. Figure 6 shows the measured oscillator frequency and output power. As V_DD increases, the output power increases, the capacitance decreases, and the oscillation frequency f_osc increases.

The figure of merit (FoM) defined in Equation (5) is used to benchmark the performance of oscillators:

$$\mathrm{FOM}=\mathrm{L}({\omega }_o,\Delta \omega )+10\cdot \log \left(P_{DC}\right)-20\cdot \log \left({\displaystyle \frac{{\omega }_o}{\Delta \omega }}\right)$$

(5)

where ω_o is the fundamental frequency, ∆ω is the offset frequency, L {∆ω} is the phase noise at ∆ω, and P_DC is the DC power consumption of the oscillator in mW. By the calculation, the FoM of the first oscillator is −199.8 dBc/Hz.

Figure 7 shows the effect of buffer bias V_B on oscillator performance. As V_B increases, output power from the buffer increases, and power dissipation in the oscillator core decreases. Oscillation frequency is insensitive to V_B, and minimum phase noise is measured at V_B = 1.4 V. Considering the effect of buffer power consumption, a new FOM is defined by

$${\mathrm{FOM}}_{\mathrm{p}}=\mathrm{L}(\Delta \omega )+10\cdot \log \left({\displaystyle \frac{P_{core}+P_{buffer}}{P_{out}}}\right)-20\cdot \log \left({\displaystyle \frac{{\omega }_o}{\Delta \omega }}\right)$$

(6)

P_OUT is the output power of the buffer, and P_Buffer is the buffer power consumption. Figure 8 shows a comparison of FOM and FOMp versus V_DD. FOM decreases with V_DD, and FOM_P is relatively insensitive to V_DD because P_Core is smaller than P_Buffer. The phase noise of the oscillator is due to the AM-PM up-conversion caused by the device’s current noise and voltage-dependent capacitance.

Table 1. Performance comparison of GaN oscillators.

Ref	Proc (um)	Topol	Vdd (V)/ Pdis (mW)	fo GHz	PN dBc/Hz	FOM dBc/Hz	8-Shaped Inductor
[7]	0.25	Hartley	28/1456	7.9	−112 *	−178	no
[10]	0.25	Balanced Colpitts	6/180	9.92	−136	−193	no
[14]	-	Push-push	15/600	9.1	−130	−181	no
[15]	0.25	Common source	10/600	9.9	−135	−187	no
[16]	0.25	Common gate	30/10625	9.55	−115.0	−154.0	no
[17]	0.25	Cross-coup	0.4/2.669	4.746	−121.77	−191.03	no
[18]	0.25	Bal Colpitts Osc	15/600	8.6	−102	−172.9	no
[19]	0.25	Cross-Coupled VCO	-/747	23.9–24.4	−109.4	−168.3	no
[20]	-	Osc (on-board)	28/4.9	2.44	−123.1	−164.03	no
This 1	0.25	feedback	0.8/2.45	8.86	−124.8	−199.8	no
This 2	0.25	LH feedback	1.6/31.36	3.818	−131.73	−188.4	no
This 3	0.12	Cross-Coupled Osc	1.3/9.373	6.397	−123.688	−190.09	yes

* @100 KHz. ¹ chip in Figure 2. ² chip in Figure 18. ³ chip in Figure 32.

shows the performance comparison. A GaN HEMT has deep-level defects located on the surface, barrier, or buffer layer of the device; the presence of deep-level defects could contribute to low-frequency current noise. It was found that the low-frequency current noise of GaN HEMT [11,12] is dominated by the flicker noise. The low-frequency current noise of M₁ flows into C_gs, C_ds, and C_gd, changes the capacitor voltage, and causes the fluctuation of average capacitance and oscillation frequency [13].

2.3. Drift of GaN HEMT Oscillator Performance with High Operating Bias

High-power GaN HEMT oscillators operate the HEMTs in the high field with the hot-carrier stress causing the electron trapping and the creation of interface states, which increase the phase noise of the oscillator. In this subsection, the degradation of the oscillator with HEMTs subjected to hot-carrier injection is discussed. The stressed oscillator is subject to higher drain voltage operation: V_DD = 8 V, V_G1 = −2.4 V, V_G2 = 0 V, V_B = 0 V for 90 min, which is divided into three time steps classified at t = 0, 30, 60, and 90 min for measuring the time-dependent oscillator performance at low supply voltage while the buffer is on. Figure 9 shows the measured oscillation frequency versus V_DD, and the oscillation frequency increases with V_DD. The stress increases the oscillation frequency. The oscillation frequency is related to the tank capacitance; the stress increases the oscillation frequency, and a high supply voltage bias reduces the capacitance.

Figure 10a shows the measured oscillator output power versus V_DD, where the V_DD increases the output power. Figure 10b shows measured power consumption versus V_DD. The stress reduces the oscillator’s output power and power consumption. Figure 11a, Figure 11b, and Figure 11c show, respectively, the measured phase noise versus stress step at V_DD = 0.8, 1, and 3 V, indicating that the fresh phase noise is the smallest at low and high offset frequencies. Figure 12 shows measured phase noise at 1 MHz offset frequency versus V_DD. At V_DD = 0.8 V, V_G1 = −2.4 V, V_B = 3 V, V_G2 = −2 V, the measured fresh phase noise of the oscillator is about −124.8 dBc/Hz at 1 MHz offset frequency from the carrier frequency 8.86 GHz. Figure 13 shows the FOM versus V_DD. The high drain bias increases phase noise and degrades the FOM at V_DD < 2 V.

For the next stress experiment, the buffer is subjected to higher drain voltage operation: V_G1 = 0 V, V_DD = 0 V, V_G2 = −2.2 V, and V_B = 8 V for 30 min, and the VCO-core is under low supply voltage. Figure 14a shows the measured output characteristics of buffer HEMT before and after the high buffer bias. Figure 14b shows measured oscillation frequency versus V_B, and Figure 14c shows measured phase noises versus step stress. The buffer stress alone does not change the oscillation frequency and phase noise of the oscillator under low supply bias. This indicates that biasing the oscillator core at low supply and the buffer at high supply voltage is a good operation condition for large output power because high FOM is maintained. To gain high output power, the buffer supply voltage is increased.

3. Balanced GaN HEMT Oscillator with Left-Handed Transmission Line Filter

3.1. Circuit Design of the Balanced Oscillator

The previous oscillator is a single-ended circuit, and this section discusses a balanced oscillator using two identical single-ended oscillators configured in a balanced structure. In the balanced oscillator, the feedback network can be a lossless transmission line (TL) such as a right-handed TL (RH-TL) consisting of a series inductor L₁ and parallel capacitor C, as shown in Figure 15a, or a left-handed TL (LH-TL) consisting of a shunt inductor L₁ and series capacitor C, as shown in Figure 15b; the composite right/left-handed TL (CRLH-TL) is a general TL with a combination of the RH-TL and LH-TL. The LH-TL [14] and CRLH-TL [15,16] have been used to design CMOS cross-coupled oscillators. The present GaN HEMT balanced oscillator employs the LH-TL as the feedback network by cascading three LH-TL unit cells.

Figure 16a shows the schematic of the designed fixed-frequency GaN HEMT oscillator. It consists of two single-ended sub-oscillators sharing the same virtual ground. The first sub-oscillator consists of a feedback filter and an amplifier formed with inductor L₁ and HEMT M₁. R₁ is a gate-biasing resistor, and V_G1 is the gate voltage for M₁. Inductors L₁, L₂, and L₃, capacitors C₁, C₂, and C₃ form a left-handed filter for feedback from the output at the I-node to the input of the amplifier at the O-node. The circuit of a standing wave oscillator (SWO) uses an open-ended TL. The filter acts as an impedance transformer between the input and output of the amplifier, and it also provides a phase response to set the oscillation frequency. V_DD is the supply voltage. The second sub-oscillator consists of the same components as the first sub-oscillator. The common node of L₂ and R₅ is a virtual ground for the differential mode signals, and the common mode signal will develop a voltage at this node. R₅ is the resistor used to diminish the common-mode oscillation. HEMT M₃ and M₄ forms buffer amplifiers with gate bias at V_G2 through the gate-bias resistors R₃ and R₄. V_B is the buffer drain bias through an external bias inductor L. The I-port shows the largest voltage swing, and the O-port shows the smallest voltage swing; both ports show opposite voltage phases. C₁ and L₂ cause a phase shift and decrease the voltage swing.

In Figure 16b, a single-ended equivalent small-signal circuit for the designed oscillator is shown. C_gs, C_ds, and C_gd are, respectively, the gate-source, drain-source, and gate-drain capacitors of M₂. C_gsb is the capacitor owing to C₈ in series with the gate-source capacitor of M₄. These parasitic capacitors are bias-dependent. Device flicker noise and thermal noise are up-converted to oscillator phase noise through these capacitors via the AM-PM modulation. g_m is the transconductance of M₂, and g_d is the output conductance due to the effect of M₂ output conductance and other resistive losses. The input impedance Y_in shows the effect of a high-pass 6th–order resonator. If C_gd is ignored, then Y_in is given by

$${\mathrm{Y}}_{in}={\displaystyle \frac{den}{{\mathrm{sL}}_{1\mathrm{h}}num}}$$

(7)

$$num=s{\mathrm{C}}_{4x}{\mathrm{sL}}_{2\mathrm{h}}\{1+s^2{\mathrm{L}}_{3\mathrm{h}}{[\mathrm{C}}_{6x}+{\mathrm{C}}_{5x}]\}+1+s^2{[\mathrm{L}}_{3\mathrm{h}}{\mathrm{C}}_{6x}+{\mathrm{L}}_{3\mathrm{h}}{\mathrm{C}}_{5x}+{\mathrm{L}}_{2\mathrm{h}}{\mathrm{C}}_{5x}]+s^4{\mathrm{L}}_{2\mathrm{h}}{\mathrm{C}}_{5x}{\mathrm{L}}_{3\mathrm{h}}{\mathrm{C}}_{6x}]$$

(8)

$$\begin{array}{l}den=1+s^6{\mathrm{L}}_{1\mathrm{h}}{\mathrm{C}}_{4x}{\mathrm{L}}_{2\mathrm{h}}{\mathrm{C}}_{5x}{\mathrm{L}}_{3\mathrm{h}}{\mathrm{C}}_{6x}+s^2{[\mathrm{L}}_{3\mathrm{h}}{\mathrm{C}}_{6x}+{\mathrm{L}}_{3\mathrm{h}}{\mathrm{C}}_{5x}+{\mathrm{L}}_{2\mathrm{h}}{\mathrm{C}}_{5x}+{\mathrm{C}}_{4x}{\mathrm{L}}_{2\mathrm{h}}+{\mathrm{L}}_{1\mathrm{h}}{\mathrm{C}}_{4x}]\\ +s^4{\{\mathrm{L}}_{2\mathrm{h}}{\mathrm{C}}_{5x}{\mathrm{L}}_{3\mathrm{h}}{\mathrm{C}}_{6x}+{\mathrm{C}}_{4x}{\mathrm{L}}_{2\mathrm{h}}{\mathrm{L}}_{3\mathrm{h}}{[\mathrm{C}}_{6x}+{\mathrm{C}}_{5x}]+{\mathrm{L}}_{1\mathrm{h}}{\mathrm{C}}_{4x}{[\mathrm{L}}_{3\mathrm{h}}{\mathrm{C}}_{6x}+{\mathrm{L}}_{3\mathrm{h}}{\mathrm{C}}_{5x}+{\mathrm{L}}_{2\mathrm{h}}{\mathrm{C}}_{5x}]\}\end{array}$$

(9)

If C₅ and L_2h are removed, the input admittance of the 4th-order resonator becomes

$${\mathrm{Y}}_{in}={\displaystyle \frac{1+s^2{[\mathrm{L}}_{3\mathrm{h}}{\mathrm{C}}_{6x}+{\mathrm{L}}_{3\mathrm{h}}{\mathrm{C}}_{4x}+{\mathrm{L}}_{1\mathrm{h}}{\mathrm{C}}_{4x}]+s^4{\mathrm{L}}_{1\mathrm{h}}{\mathrm{C}}_{4x}{\mathrm{L}}_{3\mathrm{h}}{\mathrm{C}}_{6x}}{{\mathrm{sL}}_{1\mathrm{h}}\{1+s^2{\mathrm{L}}_{3\mathrm{h}}{[\mathrm{C}}_{6x}+{\mathrm{C}}_{4x}]\}}}$$

(10)

The resonant frequency is obtained by setting Y_in = 0.

$${\omega }^2={\displaystyle \frac{{\mathrm{L}}_{3\mathrm{h}}{\mathrm{C}}_{6x}+{\mathrm{L}}_{3\mathrm{h}}{\mathrm{C}}_{4x}+{\mathrm{L}}_{1\mathrm{h}}{\mathrm{C}}_{4x}}{2{\mathrm{L}}_{1\mathrm{h}}{\mathrm{C}}_{4x}{\mathrm{L}}_{3\mathrm{h}}{\mathrm{C}}_{6x}}}\pm {\displaystyle \frac{\sqrt{{{[\mathrm{L}}_{3\mathrm{h}}{\mathrm{C}}_{6x}+{\mathrm{L}}_{3\mathrm{h}}{\mathrm{C}}_{4x}+{\mathrm{L}}_{1\mathrm{h}}{\mathrm{C}}_{4x}]}^2-4{\mathrm{L}}_{1\mathrm{h}}{\mathrm{C}}_{4x}{\mathrm{L}}_{3\mathrm{h}}{\mathrm{C}}_{6x}}}{2{\mathrm{L}}_{1\mathrm{h}}{\mathrm{C}}_{4x}{\mathrm{L}}_{3\mathrm{h}}{\mathrm{C}}_{6x}}}$$

(11)

The oscillation frequency should obey the Barkhausen criteria. Figure 17a shows the simulated input impedance at the drain of M₁, with a peak resonant frequency of 4.56 GHz. The second resonant frequency is 2.9 GHz, and the third resonant frequency is out of the x-axis plot. Figure 17b shows the simulated inductance and Q-factor of the inductor L₁. The inductance is 0.316 nH, and the Q-factor is 9.643 at 4.56 GHz.

3.2. Measurement and Discussion

The oscillators were designed and fabricated in the WIN 0.25 μm GaN/SiC HEMT process. Figure 18 shows the micrograph of the second oscillator with a chip area of 2 × 1 mm², including all test pads and dummy metal. Two center-tapped and one symmetric inductor are used. The die was attached to the PCB using epoxy for characterization. Figure 19 shows measured output voltages; differential signals are measured for the balanced oscillator. Figure 20 shows the measured output spectrum of the fundamental signal at 3.81 GHz with an output power of −0.706 dBm.

To investigate the effect of varying supply bias on the phase noise of the balanced oscillator, the gate bias is fixed at −2.2 V and the supply bias is changed from 0.6 V to 2 V. Figure 21 shows the phase noise performance of VCO biased at V_DD = 0.6 V~2 V. At V_DD = 1.6 V, the power consumption is 31.36 mW, the measured phase noise of oscillator is about −131.73 dBc/Hz at 1 MHz offset frequency from 3.818 GHz oscillation frequency and has a slope of −20 dB/dec in the high frequency offset. The corner frequency increases as V_DD increases. By the calculation, the FOM is −188.4 dBc/Hz. Figure 22 shows measured frequency, phase noise at 1 MHz offset, output power, and current consumption versus V_DD. As versus V_DD increases, the phase noise decreases, the oscillation frequency slightly increases, and the output power increases. Figure 23 shows the measured power consumption and output power of the buffer versus V_B. Power consumption and output power of the buffer increase with increasing V_B because of enhanced channel conductance. The thermal noise-related phase noise is more sensitive to the supply variation than the flicker noise-related phase noise. Increasing the supply voltage is an effective way to reduce phase noise at high offset frequencies at the cost of power. The phase noise associated with thermal noise reduces as V_DD increases, while the phase noise at low offset frequency is not sensitive to supply bias; the latter is owing to device flicker noise. Table 1 is the performance comparison.

3.3. High-Supply Voltage Effect

The 2nd experiment was carried out by biasing the buffer at low supply and biasing the oscillator-core at V_DD = 15 V for 30 min; the output power and consumption decrease versus bias time, t_bias, as shown in Figure 24. Measured data shows the effect of the VCO-core subject to the high V_DD bias. The hot-carrier stress causes degradation in oscillator parameters. Figure 25a shows measured phase noise after the stress time for t_bias= 0, 30, and 60 min. At 1 MHz offset frequency, the phase noise increases with bias time. Figure 25b shows measured phase noise at a 1 MHz offset frequency; the degradation occurs at low supply voltage.

4. GaN HEMT Oscillator with Implicit-Resonator

Depending on the RF applications, the GaN oscillator can be classified as either a voltage-controlled oscillator (VCO) or a fixed-frequency oscillator (FFO) [20]. This section designs a third GaN HEMT cross-coupled FFO using a two-turn 8-shaped inductor to reduce the magnetic coupling noise and a degenerated-drain inductor to reduce the phase noise. The 8-shaped inductors are configured with 1-turn [21], 2-turn [22], 3-turn, and 4-turn structures and have not been used in GaN circuits.

4.1. Circuit Design

Figure 26 shows the FFO schematic. The FFO is designed using the WIN 0.12 μm RF GaN on SiC technology. Two 1-turn 8-shaped inductors (L₂, L₃) could improve the tank Q-factor, while (M₁, M₂) show channel resistance operating in the linear regime. Two-turn eight-shaped L₁, capacitor C₁, and parasitic capacitors (C_v1, C_v2) of HEMTs (M₁, M₂) resonate at the fundamental carrier. V_DD is the supply, and V_Bias is the gate bias. The three-and-a-half-turn spiral inductors (L₄, L₅) are buffer loads using a bias circuit (C₄, R₃). The pair (M₁, M₂) provides the negative differential resistance, compensating for the loss of the LC tank.

Figure 27 shows the equivalent circuit of Figure 26 with the dual resonant network by replacing M₁ with the drain-source capacitor C_ds and channel resistor R_ds. L₂ in series with C_ds forms the harmonic resonator. Neglecting R_ds, C₁, and C_gs for simplicity, the two resonant frequencies are

$${\omega }^2={\displaystyle \frac{C_5{L}_1+L_2{C}_{ds}+0.5L_1{C}_{ds}}{2C_5{L}_1{L}_2{C}_{ds}}}\pm {\displaystyle \frac{\sqrt{{[C_5{L}_1+L_2{C}_{ds}+0.5L_1{C}_{ds}]}^2-4C_5{L}_1{L}_2{C}_{ds}}}{2C_5{L}_1{L}_2{C}_{ds}}}$$

(12)

From the nodes A and B, C₅ and (L₂, L₃) form the filter effect. C_ds, C_ds, and (L₂, L₃) form the harmonic resonance. The impedance peak seen between the nodes A and B is larger than the impedance peak seen between the nodes C and D. This is caused by (L₂, L₃).

Figure 28a shows the simulated phase noise. Inductors (L₂, L₃) reduce the phase noise. The simulated phase noise is −119.3 dBc/Hz (−121.5 dBc/Hz) without (with) drain inductor. Figure 28b shows the three simulated tank impedances. The differential-mode (DM) impedance in purple color is from a reference VCO shown in Figure 26 without (L₂, L₃). It has one peak impedance. For the designed circuit, the DM impedance seen from the A and B nodes has two peaks, indicated in red color. The fundamental DM peak impedance occurs at 7.3 GHz, and the 3rd harmonic DM impedance can reduce the phase noise by reducing the Groszkowski frequency shift [23]. It also shows an impedance dip at the second harmonic. The dip filters out the second harmonic, and it reduces the phase noise. The first peak is caused by (L₁, L₂, L₃) in shunt with (C_ds, C_ds). The impedance dip is caused by (L₂, L₃) in series with C₅. The high-frequency impedance peak is caused by (L₂, L₃) in shunt with (C_ds, C_ds). For the designed circuit, the DM impedance seen between the C and D nodes has one peak, indicated in blue color. It is smaller than the reference one, except for the peak. This will reduce the harmonics. Inductors (L₂, L₃) shift the peak impedance to a lower frequency.

Using the circuit schematic depicted in Figure 26, simulation analyses were performed at nodes A and B to obtain the waveforms shown in Figure 29. As illustrated in Figure 29a, the drain voltage (V_D1) exhibits rapid transitions between on and off states. Figure 29b shows that the drain current I_D1 contains harmonics. Figure 29c compares the impedance magnitude between nodes A and B with the DFT results of V_D1 and I_D1. It demonstrates higher impedance magnitudes at the fundamental and third harmonic frequencies compared to the second harmonic. The dip reduces the second harmonic.

Figure 30 shows the simulated time-domain drain voltage V_out1 waveform and DFT. The carrier is at 6.971 GHz and has an output power of −1.81 dBm. The second harmonic has an output power of −24.492 dBm. Figure 31a shows the layout of a one-turn series twisted eight-shaped inductor, and Figure 31b shows a two-turn eight-shaped inductor consisting of two 2-turn O-shaped inductors in a twisted series. Figure 31c shows the simulated inductance and Q-factor of the 8-shaped inductor. At 6.4 GHz, the inductance of L₂ is 0.758 nH, and the Q-factor is 13.568. The inductance of L₁ is 1.947 nH, and the Q-factor is 15.043.

4.2. Measurement and Discussion

The 3rd FFO has been designed and fabricated in the WIN 0.12 μm GaN technology. The FFO was measured on the PC board. The measurements of oscillation frequency were conducted with the Keysight Spectrum Analyzer, while the phase noise was measured using the Keysight signal source analyzer. As shown in Figure 32, the die micrograph occupies an area of 0.8 × 0.8 mm², including all test pads and dummy metal. Figure 33 shows the measured spectrum of the GaN FFO at 6.49 GHz. The carrier output power is −2.154 dBm. The second harmonic output power is −17.64 dBm, and the 3rd harmonic output power is −23.27 dBm. Figure 34a shows the measured phase noise of the FFO at V_DD = 1 V. The phase noise at 1 MHz offset from the carrier at 6.397 GHz is −120.9 dBc/Hz. The corner frequency is 800 KHz. The FOM is −188.81 dBc/Hz. Figure 34b shows the measured phase noise of the FFO at V_DD = 1.3 V. The phase noise at 1 MHz offset from the carrier at 6.397 GHz is −123.688 dBc/Hz. The corner frequency is 1 MHz. At 6.3971 GHz, the calculated FOM is −190.09 dBc/Hz. Similar to Figure 30a, Figure 35 shows the measured output voltages of the GaN FFO. Figure 33a resembles Figure 30b; the M₁ and M₂ cause the harmonic. Table 1 is the performance comparison of GaN oscillators.

5. Conclusions

This paper designs three GaN HEMT oscillators with a buffer. The oscillators include a single-ended oscillator, a balanced oscillator, and a cross-coupled oscillator. Two biases, oscillator supply and buffer supply, are used to optimize the oscillator performance and reliability of the circuit design. The first 8.86 GHz oscillator consists of an oscillator core biased at a supply voltage of 0.8 V and a buffer biased at 3 V. It can supply large output power because of a buffer biased at a high supply voltage, and it achieves low phase noise by operating the reliable oscillator core at a low supply voltage. The FoM of this oscillator is −199.8 dBc/Hz. We also study the hot-carrier stress effect on the 8.9 GHz GaN oscillator. When the core oscillator is subject to a supply voltage of 8 V, the post-bias oscillator phase noise measured at low supply voltage degrades. High FFO-core supply bias degrades the FOM. Biasing the oscillator core at low supply and the buffer at high supply is a good operation condition because high-oscillator FOM is maintained. The second 3.8 GHz balanced oscillator consists of two feedback sub-oscillators in a balanced configuration by suppressing the common mode oscillation, and the oscillator feedback uses a differential left-handed transmission line LC network for the first time in GaN HEMT oscillators. The balanced oscillator provides a differential signal, as verified by the time domain waveform. The output power increases and the phase noise improves with the supply voltage. For the present design, the output power can be controlled by buffer bias for higher output power. The oscillator phase noise degrades with high oscillator-core stress supply operation. The third 6.39 GHz C-band LC-tank oscillator with a buffer biased at high supply and the FFO-core biased at low supply is based on 0.12 μm WIN GaN-on-SiC technology. The oscillator uses 8-shaped inductors for suppressing magnetic coupling noise. At the supply of 1.3 V, the phase noise of the oscillator consists of 1/f² and 1/f³ noise; the FFO FOM is −190.09 dBc/Hz. The FFO using two 1-turn 8-shaped inductors improves the oscillator phase noise by forming an intrinsic LC resonator to null the effect of the 2nd harmonic current on the phase noise.