Special Issue "System-on-Chip (SoC) Design and Its Applications"

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: 31 January 2021.

Special Issue Editor

Prof. Dr. Yunho Jung
Website
Guest Editor
School of Electronics and Information Engineering, Korea Aerospace University, Gyeonggi-do, 10540, Korea
Interests: system-on-chip (SoC) design; VLSI signal processing; HW accelerator for AI learing and inference; HW/SW co-design

Special Issue Information

Dear Colleagues:

In recent decades, innovative system-on-chip (SoC) design has been a very important issue, due to the market requirements for small-size and low-power products. In particular, SoC design has rapidly evolved from simple uni-core systems to complex systems with many heterogeneous cores communicating and cooperating via complex on-chip networks and shared resources. In addition, artificial intelligence is essential for various SoC applications, such as autonomous vehicle, internet of things, medical/healthcare, and consumer electronics.

The main aim of this Special Issue is to attract submissions of recent high-quality research as well as review articles on the recent progress for “SoC and Its Applications.” Topics in this Special Issue include (but are not limited to):

  • Circuits for SoC: RF, analog, digital, mixed-signal circuit IP for SoC
  • Signal processing for SoC: analog/digital VLSI signal processing for SoC design
  • Low-power design: low-power design methodology, power/energy management, energy harvesting
  • MPSoC architecture: on-chip interconnect, network-on-chip, memory architecture for multicore computing, platform architectures
  • SoC for AI applications: machine learning, deep neural network, neuromorphic computing
  • SoC for intelligent systems: automotive, IoT, medical/healthcare, wired/wireless communications, consumer electronics, etc.

Prof. Dr. Yunho Jung
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All papers will be peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1500 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Published Papers (2 papers)

Order results
Result details
Select all
Export citation of selected articles as:

Research

Open AccessArticle
High Efficiency Ring-LWE Cryptoprocessor Using Shared Arithmetic Components
Electronics 2020, 9(7), 1075; https://doi.org/10.3390/electronics9071075 - 30 Jun 2020
Abstract
A high efficiency architecture for ring learning with errors (ring-LWE) cryptoprocessor using shared arithmetic components is presented in this paper. By applying a novel approach for sharing number theoretic transform (NTT) polynomial multiplier and polynomial adder in encryption and decryption operations, the total [...] Read more.
A high efficiency architecture for ring learning with errors (ring-LWE) cryptoprocessor using shared arithmetic components is presented in this paper. By applying a novel approach for sharing number theoretic transform (NTT) polynomial multiplier and polynomial adder in encryption and decryption operations, the total number of polynomial multipliers and polynomial adders used in the proposed ring-LWE cryptoprocessor are reduced. In addition, the processing time of NTT polynomial multiplier is speeded up by employing multiple-path delay feedback (MDF) architecture and deploying pipelined technique between all stages of NTT processes. As a result, the proposed architecture offers a great reduction in terms of the hardware complexity and computation latency compared with existing works. The implementation result for the proposed ring-LWE cryptoprocessor on Virtex-7 FPGA board using Xilinx VIVADO shows a significant decrease in the number of slices and LUTs compared with previous works. Moreover, the proposed ring-LWE cryptoprocessor offers higher throughput and efficiency than its predecessors. Full article
(This article belongs to the Special Issue System-on-Chip (SoC) Design and Its Applications)
Show Figures

Figure 1

Open AccessArticle
Design and Analysis of an Approximate Adder with Hybrid Error Reduction
Electronics 2020, 9(3), 471; https://doi.org/10.3390/electronics9030471 - 11 Mar 2020
Abstract
This paper presents an energy-efficient approximate adder with a novel hybrid error reduction scheme to significantly improve the computation accuracy at the cost of extremely low additional power and area overheads. The proposed hybrid error reduction scheme utilizes only two input bits and [...] Read more.
This paper presents an energy-efficient approximate adder with a novel hybrid error reduction scheme to significantly improve the computation accuracy at the cost of extremely low additional power and area overheads. The proposed hybrid error reduction scheme utilizes only two input bits and adjusts the approximate outputs to reduce the error distance, which leads to an overall improvement in accuracy. The proposed design, when implemented in 65-nm CMOS technology, has 3, 2, and 2 times greater energy, power, and area efficiencies, respectively, than conventional accurate adders. In terms of the accuracy, the proposed hybrid error reduction scheme allows that the error rate of the proposed adder decreases to 50% whereas those of the lower-part OR adder and optimized lower-part OR constant adder reach 68% and 85%, respectively. Furthermore, the proposed adder has up to 2.24, 2.24, and 1.16 times better performance with respect to the mean error distance, normalized mean error distance (NMED), and mean relative error distance, respectively, than the other approximate adder considered in this paper. Importantly, because of an excellent design tradeoff among delay, power, energy, and accuracy, the proposed adder is found to be the most competitive approximate adder when jointly analyzed in terms of the hardware cost and computation accuracy. Specifically, our proposed adder achieves 51%, 49%, and 47% reductions of the power-, energy-, and error-delay-product-NMED products, respectively, compared to the other considered approximate adders. Full article
(This article belongs to the Special Issue System-on-Chip (SoC) Design and Its Applications)
Show Figures

Figure 1

Back to TopTop