Special Issue "FPGA and SoC Devices Applied to New Trends in Image/Video and Signal Processing Fields"

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Microelectronics and Optoelectronics".

Deadline for manuscript submissions: closed (31 March 2016).

Special Issue Editors

Guest Editor
Dr. Ignacio Bravo-Muñoz

Department of Electronics, Polytechnic School Office O-217, University of Alcalá, Campus Universitario, 28871 – Alcalá, Madrid, Spain
Website | E-Mail
Fax: +34 91 885 659
Interests: embedded systems; electronic design; intelligent sensors; HDL; industrial automation; architectures based on FPGAs; image and signal processing in embedded systems
Guest Editor
Dr. Alfredo Gardel-Vicente

Department of Electronics, Polytechnic School Office O-322, University of Alcalá, Campus Universitario, 28871 – Alcalá, Madrid, Spain
Website | E-Mail
Fax: +34 91 885 659
Interests: omputer vision; parallel computing; image and IR sensors; motion planning and robot positioning; embedded electronic design; reconfigurable hardware
Guest Editor
Prof. Dr. José L. Lázaro-Galilea

Department of Electronics, Polytechnic School Office O-334, University of Alcalá, Campus Universitario, 28871 – Alcalá, Madrid, Spain
Website | E-Mail
Interests: intelligent sensors; optoelectronic sensors; sensor image fusion; sensorial systems for robotic by laser, optical fibers, and infrared vision; motion planning and electronic design

Special Issue Information

Dear Colleagues,

Field programmable gate arrays (FPGAs) and recently System on Chip (SoC) devices have been applied in different areas and fields for the past 20 years. The initial planned roadmaps to deploy them in electronics devices/applications have been widely exceeded due to the high performance that they can achieve. Other improvements such as scalability, reconfigurability or affordability have been responsible to broaden the different type of designers using these devices. Nowadays, embedded processors are available in FPGA/SOC, ready to be used in signal processing applications, video analysis algorithms, etc. Specific modules can be developed using the reconfigurable hardware and combine them into a standard processor system all in one die/circuit. Currently, many applications/algorithms executed in conventional computing architectures are being redefined to fully exploit the parallelization of hardware systems co-designed with pieces of software executed on one or more standard processors. This special issue is intended to show current proposals, applications or architectures based on FPGA/SOC devices applied to image and signal processing areas. Different topics in which they could be used (but are not limited to) are listed below.

We invite scientists and researchers from all fields related to electronics to submit papers for this special issue of Electronics.

Dr. Ignacio Bravo-Muñoz
Dr. Alfredo Gardel-Vicente
Prof. Dr. José L. Lázaro-Galilea
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All papers will be peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • embedded smart video systems
  • network on chip (noc) oriented to signal/image processing
  • new trends in image‐video processing area based on fpga/soc
  • new signal modulation/codification techniques based on fpga/soc
  • industrial applications based on fpga/soc to speed up the execution time
  • smart sensors based on fpga/soc to collect, process and send processed data
  • new high level language / novel tools to improve algorithm processing performance

Published Papers (7 papers)

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Editorial

Jump to: Research

Open AccessEditorial
FPGA and SoC Devices Applied to New Trends in Image/Video and Signal Processing Fields
Electronics 2017, 6(2), 25; https://doi.org/10.3390/electronics6020025
Received: 17 March 2017 / Accepted: 20 March 2017 / Published: 23 March 2017
Cited by 3 | PDF Full-text (182 KB) | HTML Full-text | XML Full-text
Abstract
Field-programmable gate arrays (FPGAs) and, recently, System on Chip (SoC) devices have been applied in different areas and fields for the past 20 years. [...]
Full article

Research

Jump to: Editorial

Open AccessArticle
FPGA-Based Real-Time Motion Detection for Automated Video Surveillance Systems
Electronics 2016, 5(1), 10; https://doi.org/10.3390/electronics5010010
Received: 21 December 2015 / Revised: 23 February 2016 / Accepted: 4 March 2016 / Published: 11 March 2016
Cited by 12 | PDF Full-text (5631 KB) | HTML Full-text | XML Full-text
Abstract
Design of automated video surveillance systems is one of the exigent missions in computer vision community because of their ability to automatically select frames of interest in incoming video streams based on motion detection. This research paper focuses on the real-time hardware implementation [...] Read more.
Design of automated video surveillance systems is one of the exigent missions in computer vision community because of their ability to automatically select frames of interest in incoming video streams based on motion detection. This research paper focuses on the real-time hardware implementation of a motion detection algorithm for such vision based automated surveillance systems. A dedicated VLSI architecture has been proposed and designed for clustering-based motion detection scheme. The working prototype of a complete standalone automated video surveillance system, including input camera interface, designed motion detection VLSI architecture, and output display interface, with real-time relevant motion detection capabilities, has been implemented on Xilinx ML510 (Virtex-5 FX130T) FPGA platform. The prototyped system robustly detects the relevant motion in real-time in live PAL (720 × 576) resolution video streams directly coming from the camera. Full article
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Open AccessArticle
FPGA Implementation of Blue Whale Calls Classifier Using High-Level Programming Tool
Received: 10 November 2015 / Revised: 17 January 2016 / Accepted: 26 January 2016 / Published: 4 February 2016
Cited by 8 | PDF Full-text (3963 KB) | HTML Full-text | XML Full-text
Abstract
In this paper, we propose a hardware-based architecture for automatic blue whale calls classification based on short-time Fourier transform and multilayer perceptron neural network. The proposed architecture is implemented on field programmable gate array (FPGA) using Xilinx System Generator (XSG) and the Nexys-4 [...] Read more.
In this paper, we propose a hardware-based architecture for automatic blue whale calls classification based on short-time Fourier transform and multilayer perceptron neural network. The proposed architecture is implemented on field programmable gate array (FPGA) using Xilinx System Generator (XSG) and the Nexys-4 Artix-7 FPGA board. This high-level programming tool allows us to design, simulate and execute the compiled design in Matlab/Simulink environment quickly and easily. Intermediate signals obtained at various steps of the proposed system are presented for typical blue whale calls. Classification performances based on the fixed-point XSG/FPGA implementation are compared to those obtained by the floating-point Matlab simulation, using a representative database of the blue whale calls. Full article
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Open AccessArticle
Hardware/Software Co-Design of a Traffic Sign Recognition System Using Zynq FPGAs
Electronics 2015, 4(4), 1062-1089; https://doi.org/10.3390/electronics4041062
Received: 31 August 2015 / Revised: 23 November 2015 / Accepted: 26 November 2015 / Published: 4 December 2015
Cited by 7 | PDF Full-text (2550 KB) | HTML Full-text | XML Full-text
Abstract
Traffic sign recognition (TSR), taken as an important component of an intelligent vehicle system, has been an emerging research topic in recent years. In this paper, a traffic sign detection system based on color segmentation, speeded-up robust features (SURF) detection and the k [...] Read more.
Traffic sign recognition (TSR), taken as an important component of an intelligent vehicle system, has been an emerging research topic in recent years. In this paper, a traffic sign detection system based on color segmentation, speeded-up robust features (SURF) detection and the k-nearest neighbor classifier is introduced. The proposed system benefits from the SURF detection algorithm, which achieves invariance to rotated, skewed and occluded signs. In addition to the accuracy and robustness issues, a TSR system should target a real-time implementation on an embedded system. Therefore, a hardware/software co-design architecture for a Zynq-7000 FPGA is presented as a major objective of this work. The sign detection operations are accelerated by programmable hardware logic that searches the potential candidates for sign classification. Sign recognition and classification uses a feature extraction and matching algorithm, which is implemented as a software component that runs on the embedded ARM CPU. Full article
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Open AccessArticle
CDL, a Precise, Low-Cost Coincidence Detector Latch
Electronics 2015, 4(4), 1018-1032; https://doi.org/10.3390/electronics4041018
Received: 26 August 2015 / Revised: 10 November 2015 / Accepted: 17 November 2015 / Published: 3 December 2015
Cited by 2 | PDF Full-text (582 KB) | HTML Full-text | XML Full-text
Abstract
The electronic detection of the coincidence of two events is still a key ingredient for high-performance applications, such as Positron Emission Tomography and Quantum Optics. Such applications are demanding, since the precision of their calculations and thus their conclusions directly depend on the [...] Read more.
The electronic detection of the coincidence of two events is still a key ingredient for high-performance applications, such as Positron Emission Tomography and Quantum Optics. Such applications are demanding, since the precision of their calculations and thus their conclusions directly depend on the duration of the interval in which two events are considered coincidental. This paper proposes a new circuitry, called coincidence detector latch (CDL), which is derived from standard RS latches. The CDL has the following advantages: low complexity, fully synthesizable, and high scalability. Even in its simple implementation, it achieves a coincidence window width as short as 115 ps, which is more than 10 times better than that reported by recent research. Full article
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Open AccessArticle
A FPGA-Based Broadband EIT System for Complex Bioimpedance Measurements—Design and Performance Estimation
Electronics 2015, 4(3), 507-525; https://doi.org/10.3390/electronics4030507
Received: 5 May 2015 / Revised: 19 July 2015 / Accepted: 22 July 2015 / Published: 29 July 2015
Cited by 13 | PDF Full-text (3298 KB) | HTML Full-text | XML Full-text
Abstract
Electrical impedance tomography (EIT) is an imaging method that is able to estimate the electrical conductivity distribution of living tissue. This work presents a field programmable gate array (FPGA)-based multi-frequency EIT system for complex, time-resolved bioimpedance measurements. The system has the capability to [...] Read more.
Electrical impedance tomography (EIT) is an imaging method that is able to estimate the electrical conductivity distribution of living tissue. This work presents a field programmable gate array (FPGA)-based multi-frequency EIT system for complex, time-resolved bioimpedance measurements. The system has the capability to work with measurement setups with up to 16 current electrodes and 16 voltage electrodes. The excitation current has a range of about 10 µA to 5 mA, whereas the sinusoidal signal used for excitation can have a frequency of up to 500 kHz. Additionally, the usage of a chirp or rectangular signal excitation is possible. Furthermore, the described system has a sample rate of up to 3480 impedance spectra per second (ISPS). The performance of the EIT system is demonstrated with a resistor-based phantom and tank phantoms. Additionally, first measurements taken from the human thorax during a breathing cycle are presented. Full article
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Open AccessArticle
A Geometric Algebra Co-Processor for Color Edge Detection
Electronics 2015, 4(1), 94-117; https://doi.org/10.3390/electronics4010094
Received: 19 November 2014 / Revised: 16 December 2014 / Accepted: 7 January 2015 / Published: 26 January 2015
Cited by 6 | PDF Full-text (1799 KB) | HTML Full-text | XML Full-text
Abstract
This paper describes advancement in color edge detection, using a dedicated Geometric Algebra (GA) co-processor implemented on an Application Specific Integrated Circuit (ASIC). GA provides a rich set of geometric operations, giving the advantage that many signal and image processing operations become straightforward [...] Read more.
This paper describes advancement in color edge detection, using a dedicated Geometric Algebra (GA) co-processor implemented on an Application Specific Integrated Circuit (ASIC). GA provides a rich set of geometric operations, giving the advantage that many signal and image processing operations become straightforward and the algorithms intuitive to design. The use of GA allows images to be represented with the three R, G, B color channels defined as a single entity, rather than separate quantities. A novel custom ASIC is proposed and fabricated that directly targets GA operations and results in significant performance improvement for color edge detection. Use of the hardware described in this paper also shows that the convolution operation with the rotor masks within GA belongs to a class of linear vector filters and can be applied to image or speech signals. The contribution of the proposed approach has been demonstrated by implementing three different types of edge detection schemes on the proposed hardware. The overall performance gains using the proposed GA Co-Processor over existing software approaches are more than 3.2× faster than GAIGEN and more than 2800× faster than GABLE. The performance of the fabricated GA co-processor is approximately an order of magnitude faster than previously published results for hardware implementations. Full article
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