Special Issue "Radiation Tolerant Electronics, Volume II"

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Microelectronics".

Deadline for manuscript submissions: closed (30 June 2022) | Viewed by 8940

Special Issue Editor

Prof. Dr. Paul Leroux
E-Mail Website
Guest Editor
Department of Electrical Engineering (ESAT), KU Leuven, Kleinhoefstraat 4, 2440 Geel, Belgium
Interests: analog and mixed-signal IC design; RF; radiation effects; radiation hardening by design
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Research on radiation tolerant electronics has increased rapidly over the last few years, resulting in many interesting approaches to model radiation effects and design radiation hardened integrated circuits and embedded systems. This research is strongly driven by the growing need for radiation hardened electronics for space applications, high-energy physics experiments such as those on the large hadron collider at CERN, and many terrestrial nuclear applications, including nuclear energy and safety management. With the progressive scaling of integrated circuit technologies and the growing complexity of electronic systems, their ionizing radiation susceptibility has raised many exciting challenges which are expected to drive research in the coming decade. Even though total ionizing dose effects in bulk CMOS is well known, still little is known on the radiation performance of advanced (FD-)SOI and FinFET technologies. Regarding single-event effects, the continued scaling has drastically increased the number of multiple-transistor or multiple-cell upsets which requires new solutions to reduce the error rate in digital and mixed-signal ASICs but also for FPGAs. Radiation hardness assurance of complex systems with multiple components in mixed technologies also necessitates new testing paradigms and verification methodologies to limit the time and cost for evaluation.

The main aim of this Special Issue is to seek high-quality submissions that highlight emerging applications, address recent breakthroughs in modeling radiation effects in advanced electronic devices and circuits, the design of radiation hardened analog, mixed-signal, RF and digital integrated circuits and radiation hardness testing methodologies. The topics of interest include, but are not limited to:

  • Basic mechanisms of radiation effects in electronic devices
  • Compact modeling of radiation effects and circuit/layout level optimization (TID and SEE)
  • Radiation effects in power devices/circuits
  • Design of radiation hardened integrated circuits (analog/RF/mixed-signal/digital)
  • Radiation hardening and fault tolerance in FPGAs
  • Radiation hardness assurance testing

Prof. Dr. Paul Leroux
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2000 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Published Papers (14 papers)

Order results
Result details
Select all
Export citation of selected articles as:

Research

Article
A Fully Polarity-Aware Double-Node-Upset-Resilient Latch Design
Electronics 2022, 11(15), 2465; https://doi.org/10.3390/electronics11152465 - 08 Aug 2022
Viewed by 167
Abstract
Due to aggressive scaling down, multiple-node-upset hardened design has become a major concern regarding radiation hardening. The proposed latch overcomes the architecture and performance limitations of state-of-the-art double-node-upset (DNU)-resilient latches. A novel stacked latch element is developed with multiple thresholds, regular architecture, increased [...] Read more.
Due to aggressive scaling down, multiple-node-upset hardened design has become a major concern regarding radiation hardening. The proposed latch overcomes the architecture and performance limitations of state-of-the-art double-node-upset (DNU)-resilient latches. A novel stacked latch element is developed with multiple thresholds, regular architecture, increased number of single-event upset (SEU)-insensitive nodes, low power dissipation, and high robustness. The radiation-aware layout considering layout-level issues is also proposed. Compared with state-of-the-art DNU-resilient latches, simulation results show that the proposed latch exhibits up to 92% delay and 80% power reduction in data activity ratio (DAR) of 100%. The radiation simulation using the dual-double exponential current source model shows that the proposed latch has the strongest radiation-hardening capability among the other DNU-resilient latches. Full article
(This article belongs to the Special Issue Radiation Tolerant Electronics, Volume II)
Show Figures

Figure 1

Article
Quantitative Research on Generalized Linear Modeling of SEU and Test Programs Based on Small Sample Data
Electronics 2022, 11(14), 2242; https://doi.org/10.3390/electronics11142242 - 18 Jul 2022
Viewed by 223
Abstract
Complex integrated circuits (ICs) have complex functions and various working modes, which have many factors affecting the performance of a single event effect. The single event effect performance of complex ICs is highly program-dependent and the single event sensitivity of a typical operating [...] Read more.
Complex integrated circuits (ICs) have complex functions and various working modes, which have many factors affecting the performance of a single event effect. The single event effect performance of complex ICs is highly program-dependent and the single event sensitivity of a typical operating mode is generally used to represent the single event performance of the circuits. Traditional evaluation methods fail to consider the cross effects of multiple factors and the comprehensive effects of each factor on the single event soft error cross section. In order to solve this problem, a new quantitative study method of single event error cross section based on a generalized linear model for different test programs is proposed. The laser test data is divided into two groups: a training set and a validation set. The former is used for model construction and parameter estimation based on five methods, such as the generalized linear model and Ensemble, while the latter is used for quantitative evaluation and validation of a single event soft error cross section of the model. In terms of percentage error, the minimum mean estimation error on the validation set is 13.93%. Therefore, it has a high accuracy to evaluate the single event soft error cross section of circuits under different testing programs based on the generalized linear model, which provides a new idea for the evaluation of a single event effect on complex ICs. Full article
(This article belongs to the Special Issue Radiation Tolerant Electronics, Volume II)
Show Figures

Figure 1

Article
TAISAM: A Transistor Array-Based Test Method for Characterizing Heavy Ion-Induced Sensitive Areas in Semiconductor Materials
Electronics 2022, 11(13), 2043; https://doi.org/10.3390/electronics11132043 - 29 Jun 2022
Viewed by 263
Abstract
The heavy ion-induced sensitive area is an essential parameter for space application integrated circuits. Circuit Designers need it to evaluate and mitigate heavy ion-induced soft errors. However, it is hard to measure this parameter due to the lack of test structures and methods. [...] Read more.
The heavy ion-induced sensitive area is an essential parameter for space application integrated circuits. Circuit Designers need it to evaluate and mitigate heavy ion-induced soft errors. However, it is hard to measure this parameter due to the lack of test structures and methods. In this paper, a test method called TAISAM was proposed to measure the heavy ion-induced sensitive area. TAISAM circuits were irradiated under the heavy ions. The measured sensitive areas are 1.75 μm2 and 1.00 μm2 with different LET values. TAISAM circuits are also used to investigate the layout structures that can affect the sensitive area. When the source region of the target transistor is floating, the heavy ion-induced sensitive area decreases by 28.5% for the target PMOS transistor while it increases by more than 28% for the target NMOS transistor. When the well contacts are added, the heavy ion-induced sensitive area decreases by more than 25% for the target PMOS transistor while it remains unchanged for the target NMOS transistor. Experimental results directly validate that the two structures significantly affect the heavy ion-induced sensitive area. Full article
(This article belongs to the Special Issue Radiation Tolerant Electronics, Volume II)
Show Figures

Figure 1

Article
Comparison of Total Ionizing Dose Effects in 22-nm and 28-nm FD SOI Technologies
Electronics 2022, 11(11), 1757; https://doi.org/10.3390/electronics11111757 - 01 Jun 2022
Viewed by 642
Abstract
Total ionizing dose (TID) effects from Co-60 gamma ray and heavy ion irradiation were studied at the 22-nm FD SOI technology node and compared with the testing results from the 28-nm FD SOI technology. Ring oscillators (RO) designed with inverters, NAND2, and NOR2 [...] Read more.
Total ionizing dose (TID) effects from Co-60 gamma ray and heavy ion irradiation were studied at the 22-nm FD SOI technology node and compared with the testing results from the 28-nm FD SOI technology. Ring oscillators (RO) designed with inverters, NAND2, and NOR2 gates were used to observe the output frequency drift and current draw. Experimental results show a noticeable increased device current draw and decreases in RO frequencies where NOR2 ROs have the most degradation. As well, the functionality of a 256 kb SRAM block and shift-register chains were evaluated during C0-60 irradiation. SRAM functionality deteriorated at 325 krad(Si) of the total dosage, while the FF chains remained functional up to 1 Mrad(Si). Overall, the 22-nm FD SOI results show better resilience to TID effects compared to the 28-nm FD SOI technology node. Full article
(This article belongs to the Special Issue Radiation Tolerant Electronics, Volume II)
Show Figures

Figure 1

Article
TID Sensitivity Assessment of Quadrature LC-Tank VCOs Implemented in 65-nm CMOS Technology
Electronics 2022, 11(9), 1399; https://doi.org/10.3390/electronics11091399 - 27 Apr 2022
Viewed by 453
Abstract
This article presents a comprehensive assessment of the ionizing radiation induced effects on the performance of quadrature phase LC-tank based voltage-controlled-oscillators (VCOs). Two different quadrature VCOs (QVCOs) that are capable of generating frequencies in the range of 2.5 GHz to 2.9 GHz are [...] Read more.
This article presents a comprehensive assessment of the ionizing radiation induced effects on the performance of quadrature phase LC-tank based voltage-controlled-oscillators (VCOs). Two different quadrature VCOs (QVCOs) that are capable of generating frequencies in the range of 2.5 GHz to 2.9 GHz are implemented in a commercial 65 nm bulk CMOS technology to target for harsh radiation environments like space applications and high-energy physics (HEP) experiments. Each of the QVCOs consumes 13 mW power from a 1.2 V supply. The architectures are based on the popular implementation of two different types of QVCOs: parallel-coupled QVCO (PQVCO) and super-harmonic coupled QVCO (SQVCO). The various performance metrics (oscillation frequency, quadrature phase, phase noise, frequency tuning range, and power consumption) of the two different QVCOs are evaluated with respect to a Total ionizing Dose (TID) up to a level of approximately 100 Mrad (SiO2) through X-ray irradiation. During irradiation, the electrical characterization of the samples of the prototype are performed under biased condition at room temperature. Before irradiation, the QVCOs (PQVCO and SQVCO) achieve phase noise equal to −115 dBc/Hz and −119 dBc/Hz at 1 MHz offset, resulting in figure-of-merit (FoM) of −172.2 dBc/Hz and −176.4 dBc/Hz respectively. The test-setup of the TID experiment is discussed and the results obtained are statistically analyzed in this article to perform a comparative study of the performance of the two different QVCOs and evaluate the effectiveness of the radiation hardened by design techniques (RHBDs) employed in the implementations. Post-irradiation, the overall variations of the frequencies of the oscillators are less than 1% and the change in tuning range (TR) is less than 5% as observed from the tested samples. Full article
(This article belongs to the Special Issue Radiation Tolerant Electronics, Volume II)
Show Figures

Graphical abstract

Article
Novel Radiation-Hardened High-Speed DFF Design Based on Redundant Filter and Typical Application Analysis
Electronics 2022, 11(9), 1302; https://doi.org/10.3390/electronics11091302 - 20 Apr 2022
Cited by 1 | Viewed by 321
Abstract
A cell-level radiation hardening by design (RHBD) method based on commercial processes of single event transient (SET) and single event upset (SEU) is proposed in this paper, in which new radiation-hardened D-type flip-flops (DFFs) are designed. An application-specific integrated circuit (ASIC) of a [...] Read more.
A cell-level radiation hardening by design (RHBD) method based on commercial processes of single event transient (SET) and single event upset (SEU) is proposed in this paper, in which new radiation-hardened D-type flip-flops (DFFs) are designed. An application-specific integrated circuit (ASIC) of a million gates level is developed based on DFFs, and SEU and single event functional interruption (SEFI) heavy-ion radiation tests are carried out. The experimental results show that the new DFF SEU ability is increased by 63 times compared with the DICE-designed DFF, and is three orders of magnitude higher than the redundantly designed DFF. The SEFI ability of the ASIC designed by the new DFF is 2.6 times higher than the circuit hardened by the TMR design. Full article
(This article belongs to the Special Issue Radiation Tolerant Electronics, Volume II)
Show Figures

Figure 1

Article
SEU Tolerance Efficiency of Multiple Layout-Hardened 28 nm DICE D Flip-Flops
Electronics 2022, 11(7), 972; https://doi.org/10.3390/electronics11070972 - 22 Mar 2022
Cited by 2 | Viewed by 485
Abstract
Three layout-hardened Dual Interlocked Storage Cell (DICE) D Flip-Flops (DFFs) were designed and manufactured based on an advanced 28 nm planar technology. The systematic vertical and tilt heavy ion irradiations demonstrated that the DICE structure contributes to radiation tolerance. However, it is hard [...] Read more.
Three layout-hardened Dual Interlocked Storage Cell (DICE) D Flip-Flops (DFFs) were designed and manufactured based on an advanced 28 nm planar technology. The systematic vertical and tilt heavy ion irradiations demonstrated that the DICE structure contributes to radiation tolerance. However, it is hard to achieve immunity from a Single Event Upset (SEU), even when a ~3-µm well isolation is utilized. The SEU mitigation of the hardened DFFs was affected by the data patterns and clock signals due to the imbalance in the number of upset nodes. When the clock signal equalled 0, no error was observed in 181Ta irradiation, indicating that the DICE DFFs are SEU tolerant in vertical irradiation owing to their reasonable isolation of sensitive volumes. The divergences of SEU cross-sections were enlarged by our specially designed joint change of tilt incidences for both the along-cell and cross-cell irradiation of heavy ions. The evaluations of SEU for both the vertical and tilt irradiations assist with eliminating the overestimation of SEU tolerance and guarantee the in-orbit safety of spacecraft in harsh radiation environments. Full article
(This article belongs to the Special Issue Radiation Tolerant Electronics, Volume II)
Show Figures

Figure 1

Article
Radiation Qualification by Means of the System-Level Testing: Opportunities and Limitations
Electronics 2022, 11(3), 378; https://doi.org/10.3390/electronics11030378 - 27 Jan 2022
Viewed by 665
Abstract
System-level radiation testing of electronics is evaluated, based on test examples of the System-in-Package (SiP) module irradiations. Total ionizing dose and single event effects tests are analyzed to better understand the opportunities and limitations of the system-level approach in the context of the [...] Read more.
System-level radiation testing of electronics is evaluated, based on test examples of the System-in-Package (SiP) module irradiations. Total ionizing dose and single event effects tests are analyzed to better understand the opportunities and limitations of the system-level approach in the context of the radiation qualification of electronics. Impact on the SiP product development is discussed. Full article
(This article belongs to the Special Issue Radiation Tolerant Electronics, Volume II)
Show Figures

Figure 1

Article
Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS
Electronics 2021, 10(22), 2741; https://doi.org/10.3390/electronics10222741 - 10 Nov 2021
Viewed by 678
Abstract
This paper presents the first fully integrated radiation-tolerant All-Digital Phase-Locked Loop (PLL) and Clock and Data Recovery (CDR) circuit for wireline communication applications. Several radiation hardening techniques are proposed to achieve state-of-the-art immunity to Single-Event Effects (SEEs) up to 62.5 MeV cm2 [...] Read more.
This paper presents the first fully integrated radiation-tolerant All-Digital Phase-Locked Loop (PLL) and Clock and Data Recovery (CDR) circuit for wireline communication applications. Several radiation hardening techniques are proposed to achieve state-of-the-art immunity to Single-Event Effects (SEEs) up to 62.5 MeV cm2 mg−1 as well as tolerance to the Total Ionizing Dose (TID) exceeding 1.5 Grad. The LC Digitally Controlled Oscillator (DCO) is implemented without MOS varactors, avoiding the use of a highly SEE sensitive circuit element. The circuit is designed to operate at reference clock frequencies from 40 MHz to 320 MHz or at data rates from 40 Mbps to 320 Mbps and displays a jitter performance of 520 fs with a power dissipation of only 11 mW and an FOM of 235 dB. Full article
(This article belongs to the Special Issue Radiation Tolerant Electronics, Volume II)
Show Figures

Figure 1

Article
Comparison of the Total Ionizing Dose Sensitivity of a System in Package Point of Load Converter Using Both Component- and System-Level Test Approaches
Electronics 2021, 10(11), 1235; https://doi.org/10.3390/electronics10111235 - 22 May 2021
Cited by 2 | Viewed by 660
Abstract
Testing at system level is evaluated by measuring the sensitivity of point-of-load (PoL) converter parameters, submitted to total ionizing dose (TID) irradiations, at both system and component levels. Testing at system level shows that the complete system can be fully functional at the [...] Read more.
Testing at system level is evaluated by measuring the sensitivity of point-of-load (PoL) converter parameters, submitted to total ionizing dose (TID) irradiations, at both system and component levels. Testing at system level shows that the complete system can be fully functional at the TID level more than two times higher than the qualification level obtained using a standard-based component-level approach. Analysis of the failure processes shows that the TID tolerance during testing at system level is increased due to internal compensation in the system. Finally, advantages and shortcomings of the testing at system level are discussed. Full article
(This article belongs to the Special Issue Radiation Tolerant Electronics, Volume II)
Show Figures

Figure 1

Article
A Quad-Band RF Circuit for Enhancement of Energy Harvesting
Electronics 2021, 10(10), 1160; https://doi.org/10.3390/electronics10101160 - 13 May 2021
Cited by 2 | Viewed by 940
Abstract
Radio frequency energy harvesting is one of the new renewable sources that faces some technical challenges, which limit its performance. This study presents two scenarios to enhance the harvested power. The first scenario introduces a quad-band voltage multiplier circuit with a single receiving [...] Read more.
Radio frequency energy harvesting is one of the new renewable sources that faces some technical challenges, which limit its performance. This study presents two scenarios to enhance the harvested power. The first scenario introduces a quad-band voltage multiplier circuit with a single receiving antenna and four band-pass filters of elliptic type. In this scenario, four frequencies of the Global System for Mobile communications, Universal Mobile Telecommunications System, and Wireless Fidelity frequency bands have been considered for the study. The second scenario proposes a quad-band voltage multiplier circuit with four receiving antennas at the same frequency bands as the first scenario. High conversion efficiencies were achieved for the two scenarios. The proposed quad-band system developed a harvested power level, sufficient for powering up low power micro-devices with no need for an external power supply. Full article
(This article belongs to the Special Issue Radiation Tolerant Electronics, Volume II)
Show Figures

Figure 1

Article
A High-Reliability Redundancy Scheme for Design of Radiation-Tolerant Half-Duty Limited DC-DC Converters
Electronics 2021, 10(10), 1146; https://doi.org/10.3390/electronics10101146 - 12 May 2021
Viewed by 642
Abstract
Redundancy techniques are commonly used to design radiation- and fault-tolerant circuits for space applications, to ensure high reliability. However, higher reliability often comes at a cost of increased usage of hardware resources. Triple Modular Redundancy (TMR) ensures full single fault masking, with a [...] Read more.
Redundancy techniques are commonly used to design radiation- and fault-tolerant circuits for space applications, to ensure high reliability. However, higher reliability often comes at a cost of increased usage of hardware resources. Triple Modular Redundancy (TMR) ensures full single fault masking, with a >200% power and area overhead cost. TMR/Simplex ensures full single fault masking with a slightly more complicated circuitry, inefficient use of resource and a >200% power and area overhead cost, but with higher reliability than that of TMR. In this work, a high-reliability Spatial and Time Redundancy (TR) hybrid technique, which does not abandon a working module and is applicable for radiation hardening of half-duty limited DC-DC converters, is proposed and applied to the design of a radiation-tolerant digital controller for a Dual-Switch Forward Converter. The technique has the potential of double fault masking with a <2% increase in resource overhead cost compared to TMR. Moreover, for a Simplex module failure rate, λ, of 5%, the Reliability Improvement Factor (RIF) over the Simplex system is 20.8 and 500 for the proposed technique’s two- and three-module implementations, respectively, compared to a RIF over the Simplex system of only 7.25 for TMR and 14.3 for the regular TMR/Simplex scheme. Full article
(This article belongs to the Special Issue Radiation Tolerant Electronics, Volume II)
Show Figures

Figure 1

Article
A Virtual Device for Simulation-Based Fault Injection
Electronics 2020, 9(12), 1989; https://doi.org/10.3390/electronics9121989 - 24 Nov 2020
Cited by 2 | Viewed by 921
Abstract
This paper describes the design and implementation of a virtual device to perform simulation-based fault injection campaigns. The virtual device is fully compatible with the same user software that is already being used to perform fault injection campaigns in existing FPGA (Field Programmable [...] Read more.
This paper describes the design and implementation of a virtual device to perform simulation-based fault injection campaigns. The virtual device is fully compatible with the same user software that is already being used to perform fault injection campaigns in existing FPGA (Field Programmable Gate Array)-based hardware devices. Multiple instances of the virtual device can be launched in parallel in order to speed-up the fault injection campaigns, without any preexisting limitations on number, such as available license seats, since the virtual device can be compiled with the open-source simulator GHDL. This virtual device also allows one to find bugs in both software and firmware, and to reproduce in simulation, with total visibility of the internal states, corner cases that may have occurred in the real hardware. Full article
(This article belongs to the Special Issue Radiation Tolerant Electronics, Volume II)
Show Figures

Figure 1

Article
Novel Full TMR Placement Techniques for High-Speed Radiation Tolerant Digital Integrated Circuits
Electronics 2020, 9(11), 1936; https://doi.org/10.3390/electronics9111936 - 17 Nov 2020
Viewed by 657
Abstract
This paper presents a novel physical implementation methodology for high-speed Triple Modular Redundant (TMR) digital integrated circuits for harsh radiation environment applications. An improved distributed approach is presented to constrain redundant branches of Triple Modular Redundant (TMR) digital logic cells using repetitive, interleaved [...] Read more.
This paper presents a novel physical implementation methodology for high-speed Triple Modular Redundant (TMR) digital integrated circuits for harsh radiation environment applications. An improved distributed approach is presented to constrain redundant branches of Triple Modular Redundant (TMR) digital logic cells using repetitive, interleaved micro-floorplans. To optimally constrain the placement of both sequential and combinational cells, the TMR netlist is used to segment the the logic into unrelated groups allowing sharing without compromising reliability. The technique was evaluated in a 65 nm bulk CMOS technology and a comparison is made to conventional methods. Full article
(This article belongs to the Special Issue Radiation Tolerant Electronics, Volume II)
Show Figures

Figure 1

Back to TopTop