Special Issue "Microelectronics Reliability"

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Microelectronics".

Deadline for manuscript submissions: 30 November 2021.

Special Issue Editors

Prof. Dr. Sanghyeon Baeg
E-Mail Website
Guest Editor
Electronics Engineering, Hanyang University, Ansan, Korea
Interests: semiconductor reliability; DRAM test and reliability; radiation effects
Dr. Shi-Jie Wen
E-Mail Website
Guest Editor
Cisco System Inc., USA
Interests: silicon reliability on silicon technology, circuits, components, and network products; resilience in systems, networks, and the cloud; AI/MI in networks with high availability; HW prediction; health monitoring

Special Issue Information

Dear Colleagues,

With the advent of life-critical technologies such as autonomous vehicles, microelectronics’ reliability and requirements have increased in modern electronics. Recent research in reliability areas has rapidly expanded from low-level devices such as diodes and transistors to the reliabilities of various aspects of products: components, systems, and manufacturing processes. Microelectronics’ reliability should not be handled as a standalone issue that mainly deals with device degradation due to structural changes in materials (i.e., fundamental mechanism-oriented reliability). In order to overcome the challenges from emerging technologies that deal with life and security data, reliability topics should be perceived and researched as problems in combinations of associated devices, circuits, systems, and even system software. Such a multilevel approach of integrating devices into systems is essential. The goal of this Special Issue of Electronics is to present state-of-the-art investigations on various reliability technologies and cover all levels of integrated systems and manufacturing:

  • materials and processes;
  • technologies (CMOS, BiCMOS, etc.);
  • transistors;
  • components (SRAM, DRAM, sensors, power electronics, etc.);
  • integrated circuits (processors, controllers, etc.);
  • integrated systems (communication, graphic module, etc.); and
  • packages.

Topics of interest on reliability include, but are not limited to:

  • traditional reliability topics (TDDB, HCT, EM, etc.);
  • life testing;
  • accelerated testing;
  • maintainability;
  • failure mechanisms;
  • case studies of physical failures;
  • mitigation (proactive and passive);
  • reliability models;
  • stress mechanisms;
  • interconnection issues;
  • reliability due to radiation effects;
  • telemetry, on-die sensors, and instant health monitoring for fast reliability loops.

Prof. Dr. Sanghyeon Baeg
Dr. Shi-Jie Wen
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All papers will be peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1800 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • semiconductor reliability
  • failure mechanisms
  • reliability models
  • physical failure
  • stress mechanisms
  • mitigation
  • radiation effects
  • telemetry on-die sensors, instant health monitoring for fast reliability loops

Published Papers (4 papers)

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Research

Article
DDR4 BER Degradation Due to Crack in FBGA Package Solder Ball
Electronics 2021, 10(12), 1445; https://doi.org/10.3390/electronics10121445 - 16 Jun 2021
Viewed by 377
Abstract
This paper measures bit error rate degradation in DDR4 due to crack in fine pitch ball grid array (FBGA) package solder ball. Thermal coefficient mismatch between the package and printed circuit board material causes cracks to occur in solder balls. These cracks change [...] Read more.
This paper measures bit error rate degradation in DDR4 due to crack in fine pitch ball grid array (FBGA) package solder ball. Thermal coefficient mismatch between the package and printed circuit board material causes cracks to occur in solder balls. These cracks change the electrical model of the solder ball and introduce parallel capacitance in the electrical model. The capacitance causes higher frequency attenuation and closes the data eye. As the data rate of the DDR4 increases there are more data eye closures. The data eye closure causes bit error rate (BER) degradation as the timing margin and voltage margin decreases. This degradation reduces the reliability of the system and causes more intermittent errors. DDR4 data line is loaded with a parallel capacitive element to mimic a crack in solder ball. The measured data eye shows a decrease in eye width. Bathtub plots are created for comparison of cracked solder ball and intact solder ball. The bathtub plots show the BER degradation due to crack in solder ball. Full article
(This article belongs to the Special Issue Microelectronics Reliability)
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Article
Low-Cost Soft Error Robust Hardened D-Latch for CMOS Technology Circuit
Electronics 2021, 10(11), 1256; https://doi.org/10.3390/electronics10111256 - 25 May 2021
Cited by 1 | Viewed by 480
Abstract
In this paper, a Soft Error Hardened D-latch with improved performance is proposed, also featuring Single Event Upset (SEU) and Single Event Transient (SET) immunity. This novel D-latch can tolerate particles as charge injection in different internal nodes, as well as the input [...] Read more.
In this paper, a Soft Error Hardened D-latch with improved performance is proposed, also featuring Single Event Upset (SEU) and Single Event Transient (SET) immunity. This novel D-latch can tolerate particles as charge injection in different internal nodes, as well as the input and output nodes. The performance of the new circuit has been assessed through different key parameters, such as power consumption, delay, Power-Delay Product (PDP) at various frequencies, voltage, temperature, and process variations. A set of simulations has been set up to benchmark the new proposed D-latch in comparison to previous D-latches, such as the Static D-latch, TPDICE-based D-latch, LSEH-1 and DICE D-latches. A comparison between these simulations proves that the proposed D-latch not only has a better immunity, but also features lower power consumption, delay, PDP, and area footprint. Moreover, the impact of temperature and process variations, such as aspect ratio (W/L) and threshold voltage transistor variability, on the proposed D-latch with regard to previous D-latches is investigated. Specifically, the delay and PDP of the proposed D-latch improves by 60.3% and 3.67%, respectively, when compared to the reference Static D-latch. Furthermore, the standard deviation of the threshold voltage transistor variability impact on the delay improved by 3.2%, while its impact on the power consumption improves by 9.1%. Finally, it is shown that the standard deviation of the (W/L) transistor variability on the power consumption is improved by 56.2%. Full article
(This article belongs to the Special Issue Microelectronics Reliability)
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Article
Experimental Study of Thermal Management Characteristics of Mass via Arrays
Electronics 2021, 10(9), 1027; https://doi.org/10.3390/electronics10091027 - 26 Apr 2021
Viewed by 367
Abstract
Mass via arrays (MVAs) are intersubstrate thermal management structures that utilize thermal meta-material design principles to target localized hot spots and extreme variation in the temperature profile of electronic systems. MVAs have shown promise for integration into electronic systems as passive thermal management [...] Read more.
Mass via arrays (MVAs) are intersubstrate thermal management structures that utilize thermal meta-material design principles to target localized hot spots and extreme variation in the temperature profile of electronic systems. MVAs have shown promise for integration into electronic systems as passive thermal management techniques. Theoretical analysis has shown that, when properly designed, MVAs and MVA-like structures provide control over how the heat is transferred in an electronic substrate. While the theoretical confirmation of this behavior is promising, experimental results are important to prove and strengthen MVA design principles. In this work, MVAs are implemented using an industry-standard printed circuit board (PCB) fabrication technique with Rogers 4350B (RO4350) material. The design structures are first theoretically modeled using a multilayer RO4350 stack-up in which equivalent thermal properties are studied for a variety of MVA designs. Uncertainty metrics are integrated into this model, and an iterative, Monte Carlo process is used to simulate variability in MVA performance. Next, these theoretical structures are implemented in conventional PCBs. Sample devices are chosen at random, and the heat spreading characteristics of the devices are measured using a thermal imaging camera. The results of these measurements confirm the theoretical baseline that an MVA structure provides improved thermal management characteristics relative to conventional thermal via array (TVA) structures. Full article
(This article belongs to the Special Issue Microelectronics Reliability)
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Article
Comparative Study on the “Soft Errors” Induced by Single-Event Effect and Space Electrostatic Discharge
Electronics 2021, 10(7), 802; https://doi.org/10.3390/electronics10070802 - 28 Mar 2021
Cited by 1 | Viewed by 436
Abstract
Single event effect (SEE) and space electrostatic discharge (SESD) are two important types of effects causing spacecraft anomalies. However, it is difficult to differentiate them to identify the root cause of on-orbit anomalies. This paper pioneers the comparative study of the “soft errors” [...] Read more.
Single event effect (SEE) and space electrostatic discharge (SESD) are two important types of effects causing spacecraft anomalies. However, it is difficult to differentiate them to identify the root cause of on-orbit anomalies. This paper pioneers the comparative study of the “soft errors” induced by the SEE and SESD with a well-known static random-access memory (SRAM). The similarity and difference of the physical mechanisms between the “soft errors” induced by SEE and SESD are studied with the technology computer-aided design (TCAD) simulations. Meanwhile, the characteristics of the “soft errors” and the relation with external stimulus between SEE and SESD are further investigated with the pulsed laser SEE facility and SESD test system. The results showed that the similar appearances of “soft errors” can be generated by both SEE and SESD, while multiple-bit upset (MBU) has been observed only in SESD testing. In addition, in comparison to the random distribution of SEE sensitivity areas, the SESD sensitivity areas are in closer proximity to the power supply regions. The different symptoms in upsets can be used to identify the root causes of the spacecraft anomalies. Full article
(This article belongs to the Special Issue Microelectronics Reliability)
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