Hardware Accelerated Algorithms and Architectures for Various DSP Applications
A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".
Deadline for manuscript submissions: closed (30 June 2023) | Viewed by 10126
Special Issue Editor
Interests: digital signal processing; VLSI for signal processing algorithms; system-on-chip design; HW-SW co-design; machine learning; digital communication
Special Issue Information
Dear Colleagues,
Achieving high performance even with low power consumption has become a major issue when designing embedded systems with limited resources. To this end, there is a growing demand for accelerated computing that speeds up processing by allocating some processing to subsystems such as GPGPU, FPGA, ASIC, and DSP. Even if a new algorithm meets the design goals, the usefulness of the algorithm inevitably decreases if it is not hardware friendly. The rapid evolution of high-level synthesis tools that automatically convert algorithm level to register-transfer level is also based on the growing demand for accelerated computing and shorter time-to-market. Therefore, in the algorithm development stage, not only should the ease of hardware implementation be considered but also the optimized hardware architecture. In addition, appropriate software–hardware partitioning along with their co-optimization is essential to maximize performance with limited resources.
The main purpose of this Special Issue is to attract submissions on the development of high-performance signal processing algorithms and optimized hardware architectures required for various signal processing applications, such as artificial intelligence, 5G, autonomous vehicles, cybersecurity, biomedical systems, video analytics, etc. Optimization at all levels of abstraction falls within the field of interest of this Special Issue, e.g., at the algorithm, register-transfer, and circuit levels.
The topics of interest include, but are not limited to:
• Models, methods, and architectures for accelerated computing
• Hardware architecture for digital signal processing algorithm
• Hardware design in edge/IoT computing
• Low power and high-performance design
• Hardware/software co-design
• High level synthesis
• Reconfigurable system design
• Interaction of CPU and FPGA components
• System on chip design
• High-speed algorithm and architecture
• Optimized design of digital communication systems
• Digital system design with reduced memory bandwidth
Prof. Dr. Sang Yoon Park
Guest Editor
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