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Hardware in the Loop for Electrical Systems: Techniques, Algorithm and...
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Hardware in the Loop for Electrical Systems: Techniques, Algorithm and Circuits

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Power Electronics".

Deadline for manuscript submissions: closed (31 October 2020) | Viewed by 44785

Special Issue Editor

Dr. Giambattista Gruosso

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Guest Editor
Department of Electronics, Information and BioEngineering, Politecnico di Milano, Piazza Leonardo da Vinci, 32, 20133 Milano, MI, Italy
Interests: simulation and modelling of electrical systems; hardware in the loop simulation; electrical vehicle simulation and modelling; smart grid simulation; Industry 4.0
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

The hardware in the loop simulation of electrical and electronic systems still has unexplored potential. The aim of this Special Issue is to collect the best contributions on both simulation methods and on architectures to be used, including the necessary interfacing circuits. For the latter aspect, the theme of power hardware in the loop is perfectly in line with the purpose of the Issue.

This Special Issue aims to collect methodological works, reviews, or innovative applications of hardware in the loop techniques applied to different fields of engineering, such as automotive, smart grids, avionics, and biomedical electronics. However, any application of hardware in the loop to the simulation of electrical and electronic systems is to be considered in the scope of this Special Issue.

Topics of interest include, but are not limited to:

  • Hardware in the loop simulation of grid-connected renewable energy;
  • Hardware in the loop simulation of automotive components integration;
  • Hardware in the loop simulation and testing of electronic control units;
  • Hardware in the loop simulation of electronics and systems for biomedical devices;
  • Hardware in the loop simulation for testing.

Dr. Giambattista Gruosso
Guest Editor

Manuscript Submission Information

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Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • hardware in the loop
  • control in the loop
  • power hardware in the loop
  • biomedical electronics and devices
  • smart grids
  • electrical vehicles
  • energy storage systems
  • real-time simulation
  • testing

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Published Papers (11 papers)

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Research

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14 pages, 6232 KiB  
Article
Emulator of a Boost Converter for Educational Purposes
by Paula Lamo, Ángel de Castro, Christian Brañas and Francisco J. Azcondo
Electronics 2020, 9(11), 1883; https://doi.org/10.3390/electronics9111883 - 9 Nov 2020
Cited by 9 | Viewed by 3138
Abstract
Project-based learning (PBL) is proposed for the development of a Hardware-in-the-Loop (HIL) platform and the design of its digital controller for an undergraduate course on Digital Electronic Systems. The objective for students is the design of a digitally controlled HIL Boost converter, a [...] Read more.
Project-based learning (PBL) is proposed for the development of a Hardware-in-the-Loop (HIL) platform and the design of its digital controller for an undergraduate course on Digital Electronic Systems. The objective for students is the design of a digitally controlled HIL Boost converter, a digital pulse-width modulator (DPWM) and a current mode controller, implemented in field-programmable gate array (FPGA) devices. To this end, the different parts of the project are developed and evaluated, maximizing the use of FPGA resources in the design of the HIL and DPWM blocks, and applying design techniques that minimize the use of the digital resources used in the design of the controller. Students are equipped with a new individualized educational experience, allowing them to test their technical competence and knowledge in an environment close to the reality of the industry. Full article
(This article belongs to the Special Issue Hardware in the Loop for Electrical Systems: Techniques, Algorithm and Circuits)
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21 pages, 1518 KiB  
Article
A Latency-Insensitive Design Approach to Programmable FPGA-Based Real-Time Simulators
by Federico Montaño, Tarek Ould-Bachir and Jean Pierre David
Electronics 2020, 9(11), 1838; https://doi.org/10.3390/electronics9111838 - 3 Nov 2020
Cited by 5 | Viewed by 3335
Abstract
This paper presents a methodology for the design of field-programmable gate array (FPGA)-based real-time simulators (RTSs) for power electronic circuits (PECs). The programmability of the simulator results from the use of an efficient and scalable overlay architecture (OA). The proposed OA relies on [...] Read more.
This paper presents a methodology for the design of field-programmable gate array (FPGA)-based real-time simulators (RTSs) for power electronic circuits (PECs). The programmability of the simulator results from the use of an efficient and scalable overlay architecture (OA). The proposed OA relies on a latency-insensitive design (LID) paradigm. LID consists of connecting small processing units that automatically synchronize and exchange data when appropriate. The use of such data-driven architecture aims to ease the design process while achieving a higher computational efficiency. The benefits of the proposed approach is evaluated by assessing the performance of the proposed solver in the simulation of a two-stage AC–AC power converter. The minimum achievable time-step and FPGA resource consumption for a wide range of power converter sizes is also evaluated. The proposed overlays are parametrizable in size, they are cost-effective, they provide sub-microsecond time-steps, and they offer a high computational performance with a reported peak performance of 300 GFLOPS. Full article
(This article belongs to the Special Issue Hardware in the Loop for Electrical Systems: Techniques, Algorithm and Circuits)
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24 pages, 8104 KiB  
Article
HIL-Assessed Fast and Accurate Single-Phase Power Calculation Algorithm for Voltage Source Inverters Supplying to High Total Demand Distortion Nonlinear Loads
by Jorge El Mariachet, Yajuan Guan, Jose Matas, Helena Martín, Mingshen Li and Josep M. Guerrero
Electronics 2020, 9(10), 1643; https://doi.org/10.3390/electronics9101643 - 7 Oct 2020
Cited by 10 | Viewed by 3906
Abstract
The dynamic performance of the local control of single-phase voltage source inverters (VSIs) can be degraded when supplying to nonlinear loads (NLLs) in microgrids. When this control is based on the droop principles, a proper calculation of the active and reactive averaged powers [...] Read more.
The dynamic performance of the local control of single-phase voltage source inverters (VSIs) can be degraded when supplying to nonlinear loads (NLLs) in microgrids. When this control is based on the droop principles, a proper calculation of the active and reactive averaged powers (P–Q) is essential for a proficient dynamic response against abrupt NLL changes. In this work, a VSI supplying to an NLL was studied, focusing the attention on the P–Q calculation stage. This stage first generated the direct and in-quadrature signals from the measured load current through a second-order generalized integrator (SOGI). Then, the instantaneous power quantities were obtained by multiplying each filtered current by the output voltage, and filtered later by utilizing a SOGI to acquire the averaged P–Q parameters. The proposed algorithm was compared with previous proposals, while keeping the active power steady-state ripple constant, which resulted in a faster calculation of the averaged active power. In this case, the steady-state averaged reactive power presented less ripple than the best proposal to which it was compared. When reducing the velocity of the proposed algorithm for the active power, it also showed a reduction in its steady-state ripple. Simulations, hardware-in-the-loop, and experimental tests were carried out to verify the effectiveness of the proposal. Full article
(This article belongs to the Special Issue Hardware in the Loop for Electrical Systems: Techniques, Algorithm and Circuits)
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22 pages, 18985 KiB  
Article
Wide Frequency Band Single-Phase Amplitude and Phase Angle Detection Based on Integral and Derivative Actions
by Luccas M. Kunzler and Luiz A. C. Lopes
Electronics 2020, 9(10), 1578; https://doi.org/10.3390/electronics9101578 - 26 Sep 2020
Cited by 1 | Viewed by 3219
Abstract
Numerous applications, such as the synchronization of distributed energy resources to an existing AC grid, the operation of active power filters or the amplification of signals for Power-Hardware-In-The-Loop (PHIL) systems require a few tasks in common. Amplitude, phase angle and frequency detection are [...] Read more.
Numerous applications, such as the synchronization of distributed energy resources to an existing AC grid, the operation of active power filters or the amplification of signals for Power-Hardware-In-The-Loop (PHIL) systems require a few tasks in common. Amplitude, phase angle and frequency detection are crucial for all these applications and many more. Various techniques are presented for three-phase and single-phase applications but only a few of them are able to identify the signals’ attributes for a wide range of frequencies and amplitudes. Single-phase systems are typically burdensome, considering the challenge to create an internal signal, orthogonal with the input, in order to perform the phase angle detection. This matter is even more critical when the amplitude and frequency of the input signal varies in a wide range. This paper presents an Orthogonal Signal Generator (OSG) based on integral and derivative actions. It includes a detailed design procedure and a design example. The performance of a single-phase wide range amplitude and frequency detector based on the discussed OSG is experimentally validated under steady state and dynamic conditions. Full article
(This article belongs to the Special Issue Hardware in the Loop for Electrical Systems: Techniques, Algorithm and Circuits)
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20 pages, 1701 KiB  
Article
Hardware in the Loop Implementation of the Oscillator-based Heart Model: A Framework for Testing Medical Devices
by Chiara Di Mascio and Giambattista Gruosso
Electronics 2020, 9(4), 571; https://doi.org/10.3390/electronics9040571 - 28 Mar 2020
Cited by 3 | Viewed by 4798
Abstract
The hardware in the loop technologies allow to simulate physical models in combination with real devices in order to validate the behavior of the latter under different conditions, not easily reproducible in the real world. They are widely used in various industrial applications. [...] Read more.
The hardware in the loop technologies allow to simulate physical models in combination with real devices in order to validate the behavior of the latter under different conditions, not easily reproducible in the real world. They are widely used in various industrial applications. In this work we want to extend the methodology to medical devices. These must interact with the patient to obtain the desired clinical result, however, during the development and validation phase of medical devices, the patient cannot be involved in the testing process. In this article the hardware in the loop methodology is proposed starting from a mathematical model of the heart, based on oscillators, that can be used to validate pacemakers or other medical devices. Full article
(This article belongs to the Special Issue Hardware in the Loop for Electrical Systems: Techniques, Algorithm and Circuits)
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12 pages, 1808 KiB  
Article
Analysis of Resolution in Feedback Signals for Hardware-in-the-Loop Models of Power Converters
by María Sofía Martínez-García, Angel de Castro, Alberto Sanchez and Javier Garrido
Electronics 2019, 8(12), 1527; https://doi.org/10.3390/electronics8121527 - 12 Dec 2019
Cited by 12 | Viewed by 2642
Abstract
One of the main techniques for debugging power converters is hardware-in-the-loop (HIL), which is used for real-time emulation. Field programmable gate arrays (FPGA) are the most common design platforms due to their acceleration capability. In this case, the widths of the signals have [...] Read more.
One of the main techniques for debugging power converters is hardware-in-the-loop (HIL), which is used for real-time emulation. Field programmable gate arrays (FPGA) are the most common design platforms due to their acceleration capability. In this case, the widths of the signals have to be carefully chosen to optimize the area and speed. For this purpose, fixed-point arithmetic is one of the best options because although the design time is high, it allows the personalization of the number of bits in every signal. The representation of state variables in power converters has been previously studied, however other signals, such as feedback signals, can also have a big influence because they transmit the value of one state variable to the rest, and vice versa. This paper presents an analysis of the number of bits in the feedback signals of a boost converter, but the conclusions can be extended to other power converters. The purpose of this work is to study how many bits are necessary in order to avoid the loss of information, but also without wasting bits. Errors of the state variables are obtained with different sizes of feedback signals. These show that the errors in each state variable have similar patterns. When the number of bits increases, the error decreases down to a certain number of bits, where an almost constant error appears. However, when the bits decrease, the error increases linearly. Furthermore, the results show that there is a direct relation between the number of bits in feedback signals and the inputs of the converter in the global error. Finally, a design criterion is given to choose the optimum width for each feedback signal, without wasting bits. Full article
(This article belongs to the Special Issue Hardware in the Loop for Electrical Systems: Techniques, Algorithm and Circuits)
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19 pages, 7495 KiB  
Article
A Power Calculation Algorithm for Single-Phase Droop-Operated-Inverters Considering Linear and Nonlinear Loads HIL-Assessed
by Jorge El Mariachet, Jose Matas, Helena Martín, Mingshen Li, Yajuan Guan and Josep M. Guerrero
Electronics 2019, 8(11), 1366; https://doi.org/10.3390/electronics8111366 - 18 Nov 2019
Cited by 10 | Viewed by 5666
Abstract
The active and reactive powers, P and Q, are crucial variables in the parallel operation of single-phase inverters using the droop method, introducing proportional droops in the inverter output frequency and voltage amplitude references. P and Q, or P-Q, are calculated as [...] Read more.
The active and reactive powers, P and Q, are crucial variables in the parallel operation of single-phase inverters using the droop method, introducing proportional droops in the inverter output frequency and voltage amplitude references. P and Q, or P-Q, are calculated as the product of the inverter output voltage and its orthogonal version with the output current, respectively. However, when sharing nonlinear loads these powers, Pav and Qav, should be averaged by low-pass filters (LPFs) with a very low cut-off frequency to avoid the high distortion induced by these loads. This forces the droop method to operate at a very low dynamic velocity and degrades the system stability. Then, different solutions have been proposed in literature to increase the system velocity, but only considering linear loads. Therefore, this work presents a method to calculate Pav and Qav using second-order generalized integrators (SOGI) to face this problem with nonlinear loads. A double SOGI (DSOGI) approach is applied to filter the nonlinear load current and provide its fundamental component to the inverter, leading to a faster dynamic velocity of the droop-based load sharing capability and improving the stability. The proposed method is shown to be faster than others in the literature when considering nonlinear loads, while smoothly driving the system with low distortion levels. Simulations, hardware-in-loop (HIL) and experimental results are provided to validate this proposal. Full article
(This article belongs to the Special Issue Hardware in the Loop for Electrical Systems: Techniques, Algorithm and Circuits)
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16 pages, 1078 KiB  
Article
Comparison of Power Converter Models with Losses for Hardware-in-the-Loop Using Different Numerical Formats
by Elyas Zamiri, Alberto Sanchez, Angel de Castro and Maria Sofia Martínez-García
Electronics 2019, 8(11), 1255; https://doi.org/10.3390/electronics8111255 - 1 Nov 2019
Cited by 15 | Viewed by 3280
Abstract
Nowadays, the Hardware-In-the-Loop (HIL) technique is widely used to test different power electronic converters. These real-time simulations require processing large data at high speed, which makes this application very suitable for FPGAs (Field Programmable Gate Array) as they are capable of parallel processing. [...] Read more.
Nowadays, the Hardware-In-the-Loop (HIL) technique is widely used to test different power electronic converters. These real-time simulations require processing large data at high speed, which makes this application very suitable for FPGAs (Field Programmable Gate Array) as they are capable of parallel processing. This paper provides an analytical discussion on three HIL models for a full-bridge converter. The three models use different possible numerical formats, namely float and fixed-point, the latter with and without optimizing the width of signals to the embedded DSP (Digital Signal Processors) blocks of the FPGA. The optimized fixed-point model (OFPM) uses three and two times fewer DSP blocks or LUTs (Look Up Tables), and the maximum achievable clock frequency is also up to 35 % and 25 % higher than the float model and non-optimized fixed-point model (nOFPM), respectively. Furthermore, the models’ accuracy is proportional to the clock frequency, thus the OFPM is also the most accurate model. Finally, the paper shows the differences in the simulation when the models include or not losses, proving that not including losses leads to high errors, especially during transients. Full article
(This article belongs to the Special Issue Hardware in the Loop for Electrical Systems: Techniques, Algorithm and Circuits)
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14 pages, 2256 KiB  
Article
A Comparison of Filtering Approaches Using Low-Speed DACs for Hardware-in-the-Loop Implemented in FPGAs
by Marina Yushkova, Alberto Sanchez, Angel de Castro and M. Sofía Martínez-García
Electronics 2019, 8(10), 1116; https://doi.org/10.3390/electronics8101116 - 3 Oct 2019
Cited by 6 | Viewed by 3757
Abstract
The use of Hardware-in-the-Loop (HIL) systems implemented in Field Programmable Gate Arrays (FPGAs) is constantly increasing because of its advantages compared to traditional simulation techniques. This increase in usage has caused new challenges related to the improvement of their performance and features like [...] Read more.
The use of Hardware-in-the-Loop (HIL) systems implemented in Field Programmable Gate Arrays (FPGAs) is constantly increasing because of its advantages compared to traditional simulation techniques. This increase in usage has caused new challenges related to the improvement of their performance and features like the number of output channels, while the price of HIL systems is diminishing. At present, the use of low-speed Digital-to-Analog Converters (DACs) is starting to be a commercial possibility because of two reasons. One is their lower price and the other is their lower pin count, which determines the number and price of the FPGAs that are necessary to handle those DACs. This paper compares four filtering approaches for providing suitable data to low-speed DACs, which help to filter high-speed input signals, discarding the need of using expensive high-speed DACS, and therefore decreasing the total cost of HIL implementations. Results show that the selection of the appropriate filter should be based on the type of the input waveform and the relative importance of the dynamics versus the area. Full article
(This article belongs to the Special Issue Hardware in the Loop for Electrical Systems: Techniques, Algorithm and Circuits)
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23 pages, 25143 KiB  
Article
A Study on the Improved Capacitor Voltage Balancing Method for Modular Multilevel Converter Based on Hardware-In-the-Loop Simulation
by Junmin Lee, Daewook Kang and Jangmyung Lee
Electronics 2019, 8(10), 1070; https://doi.org/10.3390/electronics8101070 - 21 Sep 2019
Cited by 18 | Viewed by 3869
Abstract
In the power industry, hardware in-the-loop simulation (HILS) based on a real-time digital simulator (RTDS) is important technology for modular multilevel converter (MMC)-based high-voltage direct current (HVDC) power transmission. It is possible in real time to verify various fault situations that cannot be [...] Read more.
In the power industry, hardware in-the-loop simulation (HILS) based on a real-time digital simulator (RTDS) is important technology for modular multilevel converter (MMC)-based high-voltage direct current (HVDC) power transmission. It is possible in real time to verify various fault situations that cannot be predicted by the software-in-the-loop simulation (SILS). This paper introduces the implementation methodology of sub-module (SM) capacitor voltage balancing for a MMC-HVDC physical control system based on field-programmable gate array (FPGA), which has the advantages of high-speed parallel operation and validates the reliability and accuracy of MMC-HVDC control when this control system is operated with RTDS. The characteristics of conventional capacitor voltage balancing methods, such as the nearest level control (NLC) with full sorting method, the NLC with reduced switching frequency method, and the tolerance band (TB) method, implemented on a physical control system based on this implementation methodology, are compared and analyzed. This paper proposes the improved capacitor voltage balancing method for MMC-HVDC transmission. Finally, the proposed capacitor voltage balancing method is compared with conventional methods to analyze performance in real-time to demonstrate that the proposed method is better than the conventional methods. Full article
(This article belongs to the Special Issue Hardware in the Loop for Electrical Systems: Techniques, Algorithm and Circuits)
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Review

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23 pages, 1860 KiB  
Review
A Review of PHIL Testing for Smart Grids—Selection Guide, Classification and Online Database Analysis
by Eduardo García-Martínez, José Francisco Sanz, Jesús Muñoz-Cruzado and Juan Manuel Perié
Electronics 2020, 9(3), 382; https://doi.org/10.3390/electronics9030382 - 25 Feb 2020
Cited by 25 | Viewed by 5821
Abstract
The Smart Grid is one of the most important solutions to boost electricity sharing from renewable energy sources. Its implementation adds new functionalities to power systems, which increases the electric grid complexity. To ensure grid stability and security, systems need flexible methods in [...] Read more.
The Smart Grid is one of the most important solutions to boost electricity sharing from renewable energy sources. Its implementation adds new functionalities to power systems, which increases the electric grid complexity. To ensure grid stability and security, systems need flexible methods in order to be tested in a safe and economical way. A promising test technique is Power Hardware-In-the-Loop (PHIL), which combines the flexibility of Hardware-In-the-Loop (HIL) technique with power exchange. However, the acquisition of PHIL components usually represents a great expense for laboratories and, therefore, the setting up of the experiment involves making hard decisions. This paper provides a complete guideline and useful new tools for laboratories in order to set PHIL facilities up efficiently. First, a PHIL system selection guide is presented, which describes the selection process steps and the main system characteristics needed to perform a PHIL test. Furthermore, a classification proposal containing the desirable information to be obtained from a PHIL test paper for reproducibility purposes is given. Finally, this classification was used to develop a PHIL test online database, which was analysed, and the main gathered information with some use cases and conclusions are shown. Full article
(This article belongs to the Special Issue Hardware in the Loop for Electrical Systems: Techniques, Algorithm and Circuits)
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