A Study on the Improved Capacitor Voltage Balancing Method for Modular Multilevel Converter Based on Hardware-In-the-Loop Simulation
Junmin Lee 1
Department of Electrical Engineering, Pusan National University, Pusan 46241, Korea
2
Korea Electrotechnology Research Institute, Changwon 51543, Korea
*
Author to whom correspondence should be addressed.
Electronics 2019, 8(10), 1070; https://doi.org/10.3390/electronics8101070
Received: 21 August 2019 / Revised: 11 September 2019 / Accepted: 19 September 2019 / Published: 21 September 2019
(This article belongs to the Special Issue Hardware in the Loop for Electrical Systems: Techniques, Algorithm and Circuits)
In the power industry, hardware in-the-loop simulation (HILS) based on a real-time digital simulator (RTDS) is important technology for modular multilevel converter (MMC)-based high-voltage direct current (HVDC) power transmission. It is possible in real time to verify various fault situations that cannot be predicted by the software-in-the-loop simulation (SILS). This paper introduces the implementation methodology of sub-module (SM) capacitor voltage balancing for a MMC-HVDC physical control system based on field-programmable gate array (FPGA), which has the advantages of high-speed parallel operation and validates the reliability and accuracy of MMC-HVDC control when this control system is operated with RTDS. The characteristics of conventional capacitor voltage balancing methods, such as the nearest level control (NLC) with full sorting method, the NLC with reduced switching frequency method, and the tolerance band (TB) method, implemented on a physical control system based on this implementation methodology, are compared and analyzed. This paper proposes the improved capacitor voltage balancing method for MMC-HVDC transmission. Finally, the proposed capacitor voltage balancing method is compared with conventional methods to analyze performance in real-time to demonstrate that the proposed method is better than the conventional methods.
View Full-Text
Keywords:
modular multilevel converter (MMC); hardware in-the-loop simulation (HILS); real-time digital simulator (RTDS); field-programmable gate array (FPGA); sub-module; capacitor voltage balancing; tolerance band
▼
Show Figures
Figure 1
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited
MDPI and ACS Style
Lee, J.; Kang, D.; Lee, J. A Study on the Improved Capacitor Voltage Balancing Method for Modular Multilevel Converter Based on Hardware-In-the-Loop Simulation. Electronics 2019, 8, 1070.
Show more citation formats
Note that from the first issue of 2016, MDPI journals use article numbers instead of page numbers. See further details here.
