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A Comparison of Filtering Approaches Using Low-Speed DACs for Hardware-in-the-Loop Implemented in FPGAs
Open AccessFeature PaperArticle

Comparison of Power Converter Models with Losses for Hardware-in-the-Loop Using Different Numerical Formats

HCTLab Research Group, Universidad Autónoma de Madrid, 28049 Madrid, Spain
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Electronics 2019, 8(11), 1255; https://doi.org/10.3390/electronics8111255
Received: 8 October 2019 / Revised: 22 October 2019 / Accepted: 25 October 2019 / Published: 1 November 2019
Nowadays, the Hardware-In-the-Loop (HIL) technique is widely used to test different power electronic converters. These real-time simulations require processing large data at high speed, which makes this application very suitable for FPGAs (Field Programmable Gate Array) as they are capable of parallel processing. This paper provides an analytical discussion on three HIL models for a full-bridge converter. The three models use different possible numerical formats, namely float and fixed-point, the latter with and without optimizing the width of signals to the embedded DSP (Digital Signal Processors) blocks of the FPGA. The optimized fixed-point model (OFPM) uses three and two times fewer DSP blocks or LUTs (Look Up Tables), and the maximum achievable clock frequency is also up to 35 % and 25 % higher than the float model and non-optimized fixed-point model (nOFPM), respectively. Furthermore, the models’ accuracy is proportional to the clock frequency, thus the OFPM is also the most accurate model. Finally, the paper shows the differences in the simulation when the models include or not losses, proving that not including losses leads to high errors, especially during transients. View Full-Text
Keywords: hardware in the loop; numerical format; field programmable gate array hardware in the loop; numerical format; field programmable gate array
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Zamiri, E.; Sanchez, A.; de Castro, A.; Martínez-García, M.S. Comparison of Power Converter Models with Losses for Hardware-in-the-Loop Using Different Numerical Formats. Electronics 2019, 8, 1255.

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