# Comparison of Power Converter Models with Losses for Hardware-in-the-Loop Using Different Numerical Formats

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Application Example

#### 2.1. Model of the Plant

#### 2.2. Equations

#### 2.3. Plant Modeling Possibilities

- Real type: The converter can be modeled with the signal type which is called double precision real. The real data type is defined in the library called MATH_REAL. It is a 64-bits floating-point numeric type, which is not synthesizable but can reduce the time and complexity of the design. Therefore, real type can be used only for simulation purposes but cannot be implemented in an FPGA. In this paper, the real type model of the full-bridge is considered as the reference model and all other models are compared with this model. It is notable that the numerical error of the real model, which uses 64 bits for all signals, is negligible because of the high resolution of the variables.
- Floating-point type: A floating-point type is a numeric type consisting of real numbers represented in IEEE-754 standard. It takes shorter design time in comparison with fixed-point models because the equations of the plant can be translated directly into VHDL without considering range or precision issues. Unlike the real type, the model in float type can be implemented in hardware but it takes more hardware resources to store than the fixed-point model, as confirmed in Section 4. It is also slower than the fixed-point model which has an impact on the accuracy of the model. In this paper, when referring to floating-point, single-precision (32-bits) notation is always used because the double-precision (64-bits) version would lead to much more hardware resources and decreased speed.
- Fixed-point type: The logic circuits using floating-point hardware are more complicated than fixed-point hardware, which means that the fixed-point representation uses smaller size and achieves smaller simulation step compared with floating-point representation. The drawback is that it needs more design effort to determine the optimum signal width considering the fractional and integer part of every variable of the model. It is notable that the converter is modeled only once, thus, the longer design time is not a big problem. In fixed-point notation, the designer determines the number of bits of every variable and they are fixed when the model is implemented. When the cost is an important consideration, especially in complex systems, fixed-point hardware can result in significant savings.

## 3. Implementation

## 4. Results

## 5. Conclusions

## Author Contributions

## Funding

## Conflicts of Interest

## References

- Vijay, A.S.; Doolla, S.; Chandorkar, M.C. Real-Time Testing Approaches for Microgrids. IEEE J. Emerg. Sel. Top. Power Electron.
**2017**, 5, 1356–1376. [Google Scholar] [CrossRef] - Ghosh, S.; Giambiasi, N. Modeling and simulation of mixed-signal electronic designs—Enabling analog and discrete subsystems to be represented uniformly within a single framework. IEEE Circuits Devices Mag.
**2006**, 22, 47–52. [Google Scholar] [CrossRef] - Pecheux, F.; Lallement, C.; Vachoux, A. VHDL-AMS and Verilog-AMS as alternative hardware description languages for efficient modeling of multidiscipline systems. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.
**2005**, 24, 204–225. [Google Scholar] [CrossRef] [Green Version] - Lucia, O.; Urriza, I.; Barragan, L.A.; Navarro, D.; Jimenez, O.; Burdio, J.M. Real-Time FPGA-Based Hardware-in-the-Loop Simulation Test Bench Applied to Multiple-Output Power Converters. IEEE Trans. Ind. Appl.
**2011**, 47, 853–860. [Google Scholar] [CrossRef] - Sanchez, A.; de Castro, A.; Garrido, J. A Comparison of Simulation and Hardware-in-the- Loop Alternatives for Digital Control of Power Converters. IEEE Trans. Ind. Inform.
**2012**, 8, 491–500. [Google Scholar] [CrossRef] - Jia, J.; Yang, G.; Nielsen, A.H.; Roenne-Hansen, P. Hardware-in-the-loop tests on distance protection considering VSC fault-ride-through control strategies. J. Eng.
**2018**, 2018, 824–829. [Google Scholar] [CrossRef] - Prieto-Araujo, E.; Olivella-Rosell, P.; Cheah-Mañe, M.; Villafafila-Robles, R.; Gomis-Bellmunt, O. Renewable energy emulation concepts for microgrids. Renew. Sustain. Energy Rev.
**2015**, 50, 325–345. [Google Scholar] [CrossRef] [Green Version] - Jandaghi, B.; Dinavahi, V. Real-Time FEM Computation of Nonlinear Magnetodynamics of Moving Structures on FPGA for HIL Emulation. IEEE Trans. Ind. Electron.
**2018**, 65, 7709–7718. [Google Scholar] [CrossRef] - Jandaghi, B.; Dinavahi, V. Real-Time HIL Emulation of Faulted Electric Machines Based on Nonlinear MEC Model. IEEE Trans. Energy Convers.
**2019**. [Google Scholar] [CrossRef] - Liang, T.; Dinavahi, V. Real-Time System-on-Chip Emulation of Electrothermal Models for Power Electronic Devices via Hammerstein Configuration. IEEE J. Emerg. Sel. Top. Power Electron.
**2018**, 6, 203–218. [Google Scholar] [CrossRef] - Karimi, S.; Poure, P.; Saadate, S. An HIL-Based Reconfigurable Platform for Design, Implementation, and Verification of Electrical System Digital Controllers. IEEE Trans. Ind. Electron.
**2010**, 57, 1226–1236. [Google Scholar] [CrossRef] - Liu, C.; Ma, R.; Bai, H.; Li, Z.; Gechter, F.; Gao, F. FPGA-Based Real-Time Simulation of High-Power Electronic System With Nonlinear IGBT Characteristics. IEEE J. Emerg. Sel. Top. Power Electron.
**2019**, 7, 41–51. [Google Scholar] [CrossRef] - Montano, F.; Ould-Bachir, T.; David, J.P. An Evaluation of a High-Level Synthesis Approach to the FPGA-Based Submicrosecond Real-Time Simulation of Power Converters. IEEE Trans. Ind. Electron.
**2018**, 65, 636–644. [Google Scholar] [CrossRef] - Sanchez, A.; Todorovich, E.; de Castro, A. Exploring the Limits of Floating-Point Resolution for Hardware-In-the-Loop Implemented with FPGAs. Electronics
**2018**, 7, 219. [Google Scholar] [CrossRef] - Yushkova, M.; Sanchez, A.; de Castro, A.; Martínez-García, M.S. A Comparison of Filtering Approaches Using Low-Speed DACs for Hardware-in-the-Loop Implemented in FPGAs. Electronics
**2019**, 8, 1116. [Google Scholar] [CrossRef] - Lee, J.; Kang, D.; Lee, J. A Study on the Improved Capacitor Voltage Balancing Method for Modular Multilevel Converter Based on Hardware-In-the-Loop Simulation. Electronics
**2019**, 8, 1070. [Google Scholar] [CrossRef] - Saito, K.; Akagi, H. A Power Hardware-in-the-Loop (P-HIL) Test Bench Using Two Modular Multilevel DSCC Converters for a Synchronous Motor Drive. IEEE Trans. Ind. Appl.
**2018**, 54, 4563–4573. [Google Scholar] [CrossRef] - Fernández-Álvarez, A.; Portela-García, M.; García-Valderas, M.; López, J.; Sanz, M. HW/SW Co-Simulation System for Enhancing Hardware-in-the-Loop of Power Converter Digital Controllers. IEEE J. Emerg. Sel. Top. Power Electron.
**2017**, 5, 1779–1786. [Google Scholar] [CrossRef] - Amin, M.; Aziz, G.A.A.; Durkin, J.; Mohammed, O.A. A Hardware-in-the-Loop Realization of Speed Sensorless Control of PMa-SynRM with Steady-State and Transient Performances Enhancement. IEEE Trans. Ind. Appl.
**2019**, 55, 5331–5342. [Google Scholar] [CrossRef] - Tian, J.; Liu, J.; Shu, J.; Tang, J.; Yang, J. Engineering modelling of wind turbine applied in real-time simulation with hardware-in-loop and optimising control. IET Power Electron.
**2018**, 11, 2490–2498. [Google Scholar] [CrossRef] - Faruque, M.O.; Strasser, T.; Lauss, G.; Jalili-Marandi, V.; Forsyth, P.; Dufour, C.; Dinavahi, V.; Monti, A.; Kotsampopoulos, P.; Martinez, J.A.; et al. Real-Time Simulation Technologies for Power Systems Design, Testing, and Analysis. IEEE Power Energy Technol. Syst. J.
**2015**, 2, 63–73. [Google Scholar] [CrossRef] - Matar, M.; Paradis, D.; Iravani, R. Real-time simulation of modular multilevel converters for controller hardware-in-the-loop testing. IET Power Electron.
**2016**, 9, 42–50. [Google Scholar] [CrossRef] - Deter, M.; Ha, Q.; Plöger, M.; Puschmann, F. FPGA-Based Real-Time Simulation of a DC/DC Converter. Atzelektronik Worldw.
**2014**, 9, 32–35. [Google Scholar] [CrossRef] - Rosa, A.; Silva, M.; Campos, M.; Santana, R.; Rodrigues, W.; Morais, L. SHIL and DHIL Simulations of Nonlinear Control Methods Applied for Power Converters Using Embedded Systems. Electronics
**2018**, 7, 241. [Google Scholar] [CrossRef] - Lin, N.; Shi, B.; Dinavahi, V. Non-linear behavioural modelling of device-level transients for complex power electronic converter circuit hardware realisation on FPGA. IET Power Electron.
**2018**, 11, 1566–1574. [Google Scholar] [CrossRef] - Bai, H.; Liu, C.; Zhuo, S.; Ma, R.; Paire, D.; Gao, F. FPGA-Based Device-Level Electro-Thermal Modeling of Floating Interleaved Boost Converter for Fuel Cell Hardware-in-the-Loop Applications. IEEE Trans. Ind. Appl.
**2019**. [Google Scholar] [CrossRef] - Herrera, L.; Li, C.; Yao, X.; Wang, J. FPGA-Based Detailed Real-Time Simulation of Power Converters and Electric Machines for EV HIL Applications. IEEE Trans. Ind. Appl.
**2015**, 51, 1702–1712. [Google Scholar] [CrossRef] - Barragán, L.A.; Urriza, I.; Navarro, D.; Artigas, J.I.; Acero, J.; Burdio, J.M. Comparing simulation alternatives of FPGA-based controllers for switching converters. In Proceedings of the 2007 IEEE International Symposium on Industrial Electronics, Vigo, Spain, 4–7 June 2007; pp. 419–424. [Google Scholar]
- Ruelland, R.; Gateau, G.; Meynard, T.A.; Hapiot, J.C. Design of FPGA-based emulator for series multicell converters using co-simulation tools. IEEE Trans. Power Electron.
**2003**, 18, 455–463. [Google Scholar] [CrossRef] - Ibarra, L.; Rosales, A.; Ponce, P.; Molina, A.; Ayyanar, R. Overview of Real-Time Simulation as a Supporting Effort to Smart-Grid Attainment. Energies
**2017**, 10, 817. [Google Scholar] [CrossRef] - Sanchez, A.; de Castro, A.; Garrido, J. Parametrizable fixed-point arithmetic for HIL with small simulation steps. IEEE J. Emerg. Sel. Top. Power Electron.
**2018**. [Google Scholar] [CrossRef] - Goni, O.; Sanchez, A.; Todorovich, E.; de Castro, A. Resolution Analysis of Switching Converter Models for Hardware-in-the-Loop. IEEE Trans. Ind. Inform.
**2014**, 10, 1162–1170. [Google Scholar] [CrossRef] - Vekić, M.S.; Grabić, S.U.; Majstorović, D.P.; Čelanović, I.L.; Čelanović, N.L.; Katić, V.A. Ultralow Latency HIL Platform for Rapid Development of Complex Power Electronics Systems. IEEE Trans. Power Electron.
**2012**, 27, 4436–4444. [Google Scholar] [CrossRef] - Sanchez, A.; Todorovich, E.; de Castro, A. Impact of the hardened floating-point cores on HIL technology. Electr. Power Syst. Res.
**2018**, 165, 53–59. [Google Scholar] [CrossRef] - Majstorovic, D.; Celanovic, I.; Teslic, N.D.; Celanovic, N.; Katic, V.A. Ultralow-Latency Hardware-in-the-Loop Platform for Rapid Validation of Power Electronics Designs. IEEE Trans. Ind. Electron.
**2011**, 58, 4708–4716. [Google Scholar] [CrossRef] - Ago, Y.; Nakano, K.; Ito, Y. A Classification Processor for a Support Vector Machine with Embedded DSP Slices and Block RAMs in the FPGA. In Proceedings of the 2013 IEEE 7th International Symposium on Embedded Multicore Socs, Tokyo, Japan, 26–28 September 2013; pp. 91–96. [Google Scholar]
- 7 Series DSP48E1 Slice User Guide. Available online: https://www.xilinx.com/ support/documentation/user_guides/ug479_7Series_DSP48E1.pdf (accessed on 27 March 2018).

**Figure 1.**Full-bridge topology with and without losses. (

**a**) Ideal full-bridge converter; (

**b**) Non-ideal full-bridge converter.

**Figure 4.**Percentage error of the capacitor voltage, depending on the simulation step logarithmic scale.

Situation I | Situation II | Situation III | |
---|---|---|---|

ON Switches | ${Q}_{1}$ and ${Q}_{3}$ or ${Q}_{2}$ and ${Q}_{4}$ | All OFF | 1 MOSFET and 1 diode |

${\mathit{v}}_{\mathit{L}-\mathit{l}\mathit{o}\mathit{s}\mathit{s}}$ | $(2{R}_{dson}+{R}_{L}){i}_{L}$ | $2{V}_{D}sign\left({i}_{L}\right)+(2{R}_{D}+{R}_{L}){i}_{L}$ | ${V}_{D}sign\left({i}_{L}\right)+({R}_{dson}+{R}_{D}+{R}_{L}){i}_{L}$ |

${\mathit{v}}_{\mathit{o}-\mathit{l}\mathit{o}\mathit{s}\mathit{s}}$ | ${R}_{ESR}\phantom{\rule{4pt}{0ex}}{i}_{C}$ | ${R}_{ESR}\phantom{\rule{4pt}{0ex}}{i}_{C}$ | ${R}_{ESR}\phantom{\rule{4pt}{0ex}}{i}_{C}$ |

Number of bits | Format | Resolution | |||||
---|---|---|---|---|---|---|---|

Signal | nOFPM | OFPM | nOFPM | OFPM | nOFPM | OFPM | Unit |

${\mathit{v}}_{\mathit{i}\mathit{n}}$ | 21 | 11 | Q8.12 | Q8.2 | ${2}^{-12}$ | ${2}^{-2}$ | V |

${\mathit{i}}_{\mathit{r}}$ | 40 | 30 | Q6.33 | Q6.23 | ${2}^{-33}$ | ${2}^{-23}$ | A |

${\mathit{v}}_{\mathit{C}}/{\mathit{v}}_{\mathit{o}}$ | 40 | 40 | Q9.30 | Q9.30 | ${2}^{-30}$ | ${2}^{-30}$ | V |

${\mathit{i}}_{\mathit{L}}$ | 40 | 40 | Q6.33 | Q6.33 | ${2}^{-33}$ | ${2}^{-33}$ | A |

${\mathit{i}}_{\mathit{L}}^{\mathbf{*}}$ | 40 | 25 | Q6.33 | Q6.18 | ${2}^{-33}$ | ${2}^{-18}$ | A |

${\mathit{v}}_{\mathit{L}}$ | 40 | 25 | Q6.33 | Q9.15 | ${2}^{-33}$ | ${2}^{-15}$ | V |

${\mathit{i}}_{\mathit{C}}$ | 40 | 25 | Q6.33 | Q6.18 | ${2}^{-33}$ | ${2}^{-18}$ | A |

$\frac{\mathbf{\Delta}\mathit{t}}{\mathit{L}}$ | 27 | 18 | Q-14.41 | Q-15.32 | ${2}^{-41}$ | ${2}^{-32}$ | $\frac{s}{H}$ |

$\frac{\mathbf{\Delta}\mathit{t}}{\mathit{C}}$ | 27 | 18 | Q-11.38 | Q-12.29 | ${2}^{-38}$ | ${2}^{-29}$ | $\frac{s}{F}$ |

Transient | Steady-state | |
---|---|---|

Capacitor Voltage Error (%) | 8.4933 | 1.2862 |

Inductor Current Error (%) | 38.2581 | 1.9710 |

Output Voltage Error (%) | 8.2440 | 1.2943 |

**Table 4.**Percentage difference between the reference model with losses and the MATLAB/ Simulink model.

${\mathit{V}}_{\mathit{C}}$ | ${\mathit{i}}_{\mathit{L}}$ | ${\mathit{v}}_{\mathit{o}\mathit{u}\mathit{t}}$ | |
---|---|---|---|

Transient difference (%) | 0.0258 | 0.1289 | 0.0259 |

Steady-State difference (%) | 0.0011 | 0.0363 | 0.0011 |

Ripple | Mean value | |||
---|---|---|---|---|

Without Losses | With Losses | Without Losses | With Losses | |

Capacitor voltage (V) | 0.251 | 0.243 | 99.9965 | 98.7356 |

Inductor current (A) | 3.715 | 3.510 | 6.2381 | 6.1707 |

Output voltage (V) | 0.251 | 1.277 | 99.9965 | 98.7355 |

${\mathit{R}}_{\mathit{d}\mathit{s}\mathit{o}\mathit{n}}\left(\mathsf{\Omega}\right)$ | ${\mathit{R}}_{\mathit{L}}\left(\mathsf{\Omega}\right)$ | ${\mathit{G}}_{\mathit{L}}\left({\mathsf{\Omega}}^{-1}\right)$ | ${\mathit{R}}_{\mathit{E}\mathit{S}\mathit{R}}\left(\mathsf{\Omega}\right)$ | ${\mathit{R}}_{\mathit{D}}\left(\mathsf{\Omega}\right)$ | ${\mathit{V}}_{\mathit{D}}\left(\mathit{V}\right)$ | ${\mathit{V}}_{\mathit{O}}\left(\mathit{V}\right)$ | |
---|---|---|---|---|---|---|---|

Without losses | 0 | 0 | 0.0625 | 0 | 0 | 0 | 100.000 |

With losses | 0.1 | 0.005 | 0.0625 | 0.36 | 0.8 | 0.7 | 98.735 |

Float | nOFPM | OFPM | ||||
---|---|---|---|---|---|---|

${\mathit{T}}_{\mathit{clk}}\left(\mathit{ns}\right)$ | Transient | Steady-state | Transient | Steady-state | Transient | Steady-state |

24 | $3.8538\times {10}^{-3}$ | $1.8121\times {10}^{-4}$ | $3.8461\times {10}^{-3}$ | $9.8411\times {10}^{-5}$ | $3.9712\times {10}^{-3}$ | $1.2883\times {10}^{-4}$ |

20 | $3.2838\times {10}^{-3}$ | $1.1166\times {10}^{-4}$ | $3.1765\times {10}^{-3}$ | $8.2517\times {10}^{-5}$ | $3.2263\times {10}^{-3}$ | $1.1342\times {10}^{-4}$ |

16 | $2.4927\times {10}^{-3}$ | $1.6808\times {10}^{-4}$ | $2.5065\times {10}^{-3}$ | $6.6892\times {10}^{-5}$ | $2.6252\times {10}^{-3}$ | $9.6293\times {10}^{-5}$ |

1 | $3.5829\times {10}^{-2}$ | $1.5891\times {10}^{-2}$ | $9.0971\times {10}^{-5}$ | $8.3662\times {10}^{-5}$ | $1.9425\times {10}^{-4}$ | $2.9091\times {10}^{-5}$ |

Float | nOFPM | OFPM | ||||
---|---|---|---|---|---|---|

${\mathit{T}}_{\mathit{clk}}\left(\mathit{ns}\right)$ | Transient | Steady-state | Transient | Steady-state | Transient | Steady-state |

24 | $1.6279\times {10}^{-2}$ | $1.0107\times {10}^{-3}$ | $1.6278\times {10}^{-2}$ | $5.6759\times {10}^{-4}$ | $1.6725\times {10}^{-2}$ | $6.2125\times {10}^{-4}$ |

20 | $1.3860\times {10}^{-2}$ | $7.9861\times {10}^{-4}$ | $1.3443\times {10}^{-2}$ | $4.7458\times {10}^{-4}$ | $1.3798\times {10}^{-2}$ | $5.3714\times {10}^{-4}$ |

16 | $1.0475\times {10}^{-2}$ | $8.5086\times {10}^{-4}$ | $1.0606\times {10}^{-2}$ | $3.8393\times {10}^{-4}$ | $1.1206\times {10}^{-2}$ | $4.4490\times {10}^{-4}$ |

1 | $1.5092\times {10}^{-1}$ | $4.4609\times {10}^{-2}$ | $5.3126\times {10}^{-4}$ | $6.8676\times {10}^{-4}$ | $1.0264\times {10}^{-3}$ | $7.6533\times {10}^{-4}$ |

Float | nOFPM | OFPM | ||||
---|---|---|---|---|---|---|

${\mathit{T}}_{\mathit{clk}}\left(\mathit{ns}\right)$ | Transient | Steady-state | Transient | Steady-state | Transient | Steady-state |

24 | $3.9179\times {10}^{-3}$ | $1.7985\times {10}^{-4}$ | $3.9128\times {10}^{-3}$ | $9.7579\times {10}^{-5}$ | $4.0350\times {10}^{-3}$ | $1.2881\times {10}^{-4}$ |

20 | $3.3360\times {10}^{-3}$ | $1.0625\times {10}^{-4}$ | $3.2317\times {10}^{-3}$ | $8.1659\times {10}^{-5}$ | $3.2777\times {10}^{-3}$ | $1.1367\times {10}^{-4}$ |

16 | $2.5371\times {10}^{-3}$ | $1.6001\times {10}^{-4}$ | $2.5502\times {10}^{-3}$ | $6.5965\times {10}^{-5}$ | $2.6614\times {10}^{-3}$ | $9.6861\times {10}^{-5}$ |

1 | $3.5101\times {10}^{-2}$ | $1.5261\times {10}^{-2}$ | $7.4757\times {10}^{-5}$ | $6.6688\times {10}^{-5}$ | $1.8305\times {10}^{-4}$ | $1.3657\times {10}^{-5}$ |

**Table 10.**FPGA resources used by the design and the synthesis results with and without losses (WL/WoL).

LUTs | Flip Flops | DSPs | ${\mathit{T}}_{\mathit{c}\mathit{l}\mathit{k},\mathit{m}\mathit{i}\mathit{n}}\left(\mathit{n}\mathit{s}\right)$ | |||||
---|---|---|---|---|---|---|---|---|

WL | WoL | WL | WoL | WL | WoL | WL | WoL | |

Floating-Point | 907 | 351 | 82 | 64 | 17 | 9 | 21.283 | 17.807 |

Non-Optimized Fixed-Point | 671 | 391 | 101 | 80 | 11 | 9 | 19.754 | 17.412 |

Optimized Fixed-Point | 628 | 412 | 96 | 77 | 5 | 1 | 15.784 | 13.932 |

Floating-Point (no DSPs) | 2332 | 1182 | 93 | 63 | 0 | 0 | 21.050 | 16.489 |

Non-Optimized Fixed-Point (no DSPs) | 1546 | 754 | 100 | 62 | 0 | 0 | 17.810 | 15.646 |

Optimized Fixed-Point (no DSPs) | 752 | 472 | 94 | 77 | 0 | 0 | 17.644 | 13.023 |

MATLAB HDL translation * | 782 | 305 | 121 | 80 | 9 | 4 | 22.342 | 17.205 |

MATLAB HDL translation (No DSPs) * | 2303 | 1182 | 120 | 80 | 0 | 0 | 22.807 | 20.981 |

© 2019 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

## Share and Cite

**MDPI and ACS Style**

Zamiri, E.; Sanchez, A.; de Castro, A.; Martínez-García, M.S.
Comparison of Power Converter Models with Losses for Hardware-in-the-Loop Using Different Numerical Formats. *Electronics* **2019**, *8*, 1255.
https://doi.org/10.3390/electronics8111255

**AMA Style**

Zamiri E, Sanchez A, de Castro A, Martínez-García MS.
Comparison of Power Converter Models with Losses for Hardware-in-the-Loop Using Different Numerical Formats. *Electronics*. 2019; 8(11):1255.
https://doi.org/10.3390/electronics8111255

**Chicago/Turabian Style**

Zamiri, Elyas, Alberto Sanchez, Angel de Castro, and Maria Sofia Martínez-García.
2019. "Comparison of Power Converter Models with Losses for Hardware-in-the-Loop Using Different Numerical Formats" *Electronics* 8, no. 11: 1255.
https://doi.org/10.3390/electronics8111255