# Analysis of Resolution in Feedback Signals for Hardware-in-the-Loop Models of Power Converters

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Application Example

_{out}) and the inductor current (i

_{L}) in every time step considering the state of the switch.

_{L}) or capacitor current (i

_{C}) change. When the switch is closed (Q = 1), the diode does not conduct. On the one hand, the inductor current flows through the switch, while on the other hand the capacitor discharges through the load resistor. When the switch is open (Q = 0) and the input current is positive, the diode conducts. This mode is known as continuous conduction mode (CCM). When the input current is zero and the diode does not conduct, the discontinuous conduction mode (DCM) appears. Thus, there are three possibilities: closed switch (Q = 1), open switch (Q = 0) in CCM when i

_{L}> 0, and open switch in DCM when i

_{L}= 0), which are defined in Equations (5), (6), and (7), respectively,

- $Q=1$$${i}_{L}\left(k\right)={i}_{L}\left(k-1\right)+\frac{\Delta t}{L}\xb7{v}_{g}\left(k-1\right)\phantom{\rule{0ex}{0ex}}{v}_{out}\left(k\right)={v}_{out}\left(k-1\right)-\frac{\Delta t}{C}\xb7{i}_{R}\left(k-1\right)$$
- $Q=0\mathrm{and}{i}_{L}0$$${i}_{L}\left(k\right)={i}_{L}\left(k-1\right)+\frac{\Delta t}{L}\xb7\left({v}_{g}\left(k-1\right)-{v}_{out}\left(k-1\right)\right)\phantom{\rule{0ex}{0ex}}{v}_{out}\left(k\right)={v}_{out}\left(k-1\right)+\frac{\Delta t}{C}\xb7\left({i}_{L}\left(k-1\right)-{i}_{R}\left(k-1\right)\right)$$
- $Q=0\mathrm{and}{i}_{L}=0$$${i}_{L}\left(k\right)=0\phantom{\rule{0ex}{0ex}}{v}_{out}\left(k\right)={v}_{out}\left(k-1\right)-\frac{\Delta t}{C}\xb7{i}_{R}\left(k-1\right)$$

_{g}is the input voltage and i

_{R}is the output current. The selected parameters of the boost converter used for experimental results are shown in Table 1.

## 3. Resolution Issues and Implementation

_{L}and v

_{Out}are obtained, as will be shown later.

_{1}and X

_{2}) is chosen by adding an extra bit. In the case of multiplication, the total number of bits of the integer part is the addition of the integer parts of both operands and an extra bit (X

_{1}+ X

_{2}+ 1). To avoid loss of resolution, the addition and subtraction requires the maximum of the fractional parts in the operands (Y

_{1}and Y

_{2}), and in the case of multiplication requires the addition of both parts (Y

_{1}+ Y

_{2}).

_{L}and v

_{out}), constants (dtL and dtC), inputs (vg and ir), outputs (i

_{in}and v

_{outExt}), and feedback signals (v

_{outFeedback}and i

_{LFeedback}) are shown in red.

_{out}, is 792.7 V in the worst case simulation, whereas its increment is 20 µV. As such, the recommended width when applying Equation (9) is 26 + n (i.e., 34), but with the sign bit the total number of bits is 35. For the integer part (X), at least 10 bits are needed, with which the fractional part (Y) would be 24. Although 10 bits are enough for this specific maximum, to cover other possible critical maximums in other simulations, an extra bit is added to the integer part. Thus, the final format is Q (10 + 1).(24), that is Q11.24, with a total of 36 bits. For the current inductor, i

_{L}, the maximum is 127.3 A and its incremental value is 1.991 mA. Therefore, the recommended width would be 16 + n bits (i.e., 24), but the sign is added the numbers of bit would be 25. As 7 bits are needed for the integer part (X), then the fractional part (Y) would be 17 bits. Although 7 bits is enough for the integer part, one extra is added to avoid overflow situations. Thus, the final format is Q (7 + 1).17, that is, Q8.17, with a total width of 26 bits.

_{outFeedback}and i

_{LFeedback}, without losing important information and avoiding wasting bits. This is the main contribution of the paper. These signals have the same information as the state variables. The only difference is that they do not need to accurately store the small increments, ∆x, which are already stored in the state variables themselves. The information that they have to transmit to the rest of the model is the present value of the state variable, so it can be used to calculate the increment of the other state variable.

_{outFeedback}is subtracted from v

_{g}in order to calculate the next increment in the inductor current. The same is true when i

_{LFeedback}and i

_{R}are used to calculate the next increment in the output voltage. Therefore, there doubt over whether using more bits in the feedback signals than in their associated inputs is useful or not, and to which extent. This doubt will be solved in the Results section by studying the condition in the width of the feedback signals that should be reached; that is, whether reaching the condition Y (feedback) > Y (input) is enough, if X (feedback) + Y (feedback) > X (input) + Y (input) is the real need, or if some other condition must be reached.

_{outFeedback}is used to calculate the next value of i

_{L}, and i

_{LFeedback}is then used to calculate the next value of v

_{out}, closing the loop. As a consequence, the signal with the highest error is finally responsible for the error of the circuit. Therefore, the following experiment is performed. All the variables are increased in 24 fractional bits, except for one input, which is maintained at 13 bits, along with its associated feedback signal. In this last signal, the fractional bits, Y, are removed to study the relation between the overall error and Y. The removal is done by decreasing Y until the error is near 100%.

## 4. Results

_{outFeedback}or i

_{LFeedback}). The error is calculated from a reference or golden model, which should ideally be exactly the same as the fixed-point model but with infinite resolution. This is modelled through the implementation of the same model using the real VHSIC Hardware Description Language (VHDL) data type, which is a floating point containing 64 bits. Then, the difference between the fixed-point model with each value of Y and the real model is represented through the mean average error (MAE) divided by the typical values, which are 0.75 A and 400 V for i

_{L}and v

_{out}, respectively.

_{out}= 400 V and i

_{L}= 0 A. The waveforms of the inputs and feedback signals are shown in Figure 3. Here, i

_{R}has the same kind of waveform as v

_{out}because a resistive load is simulated. Regarding v

_{g}, which is an independent input, as this application example is a DC–DC conversion, it could be a constant. However, if it was constant, it would be difficult to study the necessary number of bits in its associated feedback signal (v

_{outFeedback}), as will be explained later. That is why white noise is superimposed to the average value of 200 V, as shown in Figure 3.

_{out}changes between approximately 397 and 403 V. Its maximum variation is 6 V, so a total of log

_{2}(6) bits, rounded up to 3, are changed. Then, the number of integer bits that really change in v

_{out}is 3, which will be noted as Xmov (v

_{out}) = 3. However, the total number of changing bits in v

_{out}is Xmov + Y = 3 + Y, since all the fractional bits will also change. Using the same reasoning, for v

_{g}(represented with Q9.3 bits) with a variation of 5 V, Xmov (v

_{g}) = 3, but its total moving bits are Xmov + Y = 3 + 3 = 6 in v

_{g}. For i

_{R}, that is Q2.10 bits, a variation of 0.01125 A is obtained, so Xmov + Y = (−6) + 10 = 4 bits are changing, and finally for the i

_{LFeedback}that varies 3 A, the changing bits are Xmov + Y = 2 + Y.

_{g}and v

_{outFeedback}. Here, v

_{g}is set to Q9.3, while v

_{outFeedback}is Q11.Y with variable Y. Therefore, these two signals should be the main ones responsible for the error. The relative MAE in each state variable for this case is represented in Figure 4a for v

_{out}and Figure 4b for i

_{L}. The vertical axis is the relative MAE in logarithmic scale (so 0 means 100% error) and the horizontal axis is Y, the number of fractional bits of v

_{outFeedback}. Y is moved from a maximum of 48 bits (24 of the original v

_{out}in Figure 2 plus the 24 extra bits) down to −3, when the relative error of the inductor current approaches 100%. The relative error of the output voltage is smaller, but in accordance with the smaller relative change of this state variable, as seen in Figure 3. Regardless, the behavior in both state variables follows the same pattern. This agrees with the fact that the model is a loop in which the error in any point propagates to the rest of the model. The second conclusion is that the error stops decreasing after a certain number of Y bits is used (flat area of each series in the graphs). This reflects the fact that the signal with the highest error is responsible for almost all the error, and a slightly decrease of the error in other signals leads does not produce positive results. However, the left part of each series in the graphs shows that the error decreases as the number of Y bits increases almost linearly. Therefore, the error in that part of each series is mainly caused by the signal, which changes its number of bits, v

_{outFeedback}, while the error in the flat part is mainly caused by another signal. As all other signals except v

_{g}and v

_{outFeedback}have 24 bits more than theoretically necessary, the signal causing the error in this right part is v

_{g}. Figure 4 also shows the frontier between both error-dominant parts, which is when Y (v

_{outFeedback}) = 3. This is also the number of fractional bits of its associated input, v

_{g}.

_{out}and i

_{L}, is done in Figure 5. In this case, the other feedback signal, i

_{LFeedback}, changes its number of fractional bits (Q8.Y) and i

_{R}is set to Q2.10, so only these two signals can be the cause of the error, since the rest of the signals have 24 bits more than they need. In this case, Y is moved from 41 (17 + 24) down to −4. The same general conclusions can be extracted, while the frontier between error-dominant parts is around Y (i

_{LFeedback}) = 0. However, the number of fractional bits in i

_{R}is 10. This discards the possibility that the necessary number of fractional bits in each feedback signal must be equal to the number of fractional bits in its associated input. However, when analyzing the number of changing bits in both signals it can be seen that they are very similar in the error frontier: Xmov (i

_{LFeedback}) + Y (i

_{LFeedback}) = 2 + 0 = 2 bits, while Xmov (i

_{R}) + Y (i

_{R}) = −6 + 10 = 4 bits.

_{outFeedback}) + Y (v

_{outFeedback}) = 3 + 3 = 6 bits in the error frontier, while Xmov (v

_{g}) + Y (v

_{g}) = 3 + 3 = 6 bits. However, in order to confirm this hypothesis, additional results are desirable. These are extracted from a similar experiment with other simulation results.

_{out}= 0 V and i

_{L}= 0 A is used. The waveforms of the four signals under study are represented in Figure 6 with these initial conditions, in contrast to Figure 3, which shows the waveforms under other set of initial conditions. However, very different limits are reached in these new simulations, which significantly change Xmov. The new obtained values are Xmov (v

_{g}) = 3, Xmov (v

_{outFeedback}) = 10, Xmov (i

_{R}) = 2, and Xmov (i

_{LFeedback}) = 7.

_{outFeedback}, while v

_{g}is set to Q9.3. The rest of the signals have 24 additional bits to discard if they are the source of error. Figure 7 shows the relative MAE in both state variables. In this case, the error frontier is Y (v

_{outFeedback}) = −5 or −3, depending on the state variable. Analyzing the total number of changing bits in the error frontier, Xmov (v

_{outFeedback}) + Y (v

_{outFeedback}) = 10 + (−5) = 5 or 10 + (−3) = 7 bits, while Xmov (v

_{g}) + Y (v

_{g}) = 3 + 3 = 6 bits, so the results are in agreement with the hypothesis.

_{LFeedback}and i

_{R}, an additional consideration must be taken into account. The number of moving bits of i

_{LFeedback}is very different in two parts of the simulation. In the start-up, which lasts for 2 ms (marked in red color in Figure 6), Xmov (i

_{LFeedback}) = 7, since the current reaches 127.3 A starting from 0 A. However, after that short abrupt transient phase, the current dramatically decreases and in fact enters the DCM for a long time. Not only is the number of changing bits dramatically decreased, but the possible error is reset to 0 every switching period, since the current is forced to be 0 A. Therefore, the error comparison should be made only during that part of the simulation (first 2 ms) to avoid biased results because of the DCM mode resetting the error of i

_{LFeedback}every switching period.

_{LFeedback}) = 4, so Xmov (i

_{LFeedback}) + Y (i

_{LFeedback}) = 7 + 4 = 11 bits, while Xmov (i

_{R}) + Y (i

_{R}) = 2 + 10 = 12 bits, which is in good agreement with the hypothesis.

## 5. Discussion and Proposed Design Criteria

- Y (feedback) ≥ Y (input)
- X (feedback) + Y (feedback) ≥ X (input) + Y (input)
- Max error (feedback) < 2
^{−Y(feedback)}

## 6. Conclusions

## Author Contributions

## Funding

## Conflicts of Interest

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**Figure 3.**Inputs and feedback signal waveforms with initial conditions v

_{out}= 400 V and i

_{L}= 0.

**Figure 4.**Relative mean average error (MAE) in each state variable when removing the number of fractional bits of v

_{outFeedback}. Initial conditions are v

_{out}= 400 V and i

_{L}= 0 A. (

**a**) MAE in v

_{out}. (

**b**) MAE in i

_{L}.

**Figure 5.**Relative MAE in each state variable when sweeping the number of fractional bits of i

_{LFeedback}. The initial conditions are v

_{out}= 400 V and i

_{L}= 0 A. (

**a**) MAE in v

_{out}. (

**b**) MAE in i

_{L}.

**Figure 6.**Inputs and feedback signals waveforms with initial conditions v

_{out}= 0 V and i

_{L}= 0.

**Figure 7.**Relative MAE in each state variable when sweeping the number of fractional bits of v

_{outFeedback}. Initial conditions are v

_{out}= 0 V and i

_{L}= 0 A. (

**a**) MAE in v

_{out}. (

**b**) MAE in i

_{L}.

**Figure 8.**Relative MAE in each state variable when sweeping the number of fractional bits of i

_{LFeedback}. Initial conditions are v

_{out}= 0 V and i

_{L}= 0 A, time considered is 2 ms. (

**a**) MAE in v

_{out}. (

**b**) MAE in i

_{L}.

Parameter | Value |
---|---|

f_{sw} | 100 kHz |

L | 1 mH |

C | 100 µF |

P | 300 W |

v_{out} | 400 V |

v_{g} | 200 V |

© 2019 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

## Share and Cite

**MDPI and ACS Style**

Martínez-García, M.S.; de Castro, A.; Sanchez, A.; Garrido, J. Analysis of Resolution in Feedback Signals for Hardware-in-the-Loop Models of Power Converters. *Electronics* **2019**, *8*, 1527.
https://doi.org/10.3390/electronics8121527

**AMA Style**

Martínez-García MS, de Castro A, Sanchez A, Garrido J. Analysis of Resolution in Feedback Signals for Hardware-in-the-Loop Models of Power Converters. *Electronics*. 2019; 8(12):1527.
https://doi.org/10.3390/electronics8121527

**Chicago/Turabian Style**

Martínez-García, María Sofía, Angel de Castro, Alberto Sanchez, and Javier Garrido. 2019. "Analysis of Resolution in Feedback Signals for Hardware-in-the-Loop Models of Power Converters" *Electronics* 8, no. 12: 1527.
https://doi.org/10.3390/electronics8121527