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Open AccessFeature PaperArticle

A Comparison of Filtering Approaches Using Low-Speed DACs for Hardware-in-the-Loop Implemented in FPGAs

HCTLab Research Group, Universidad Autonoma de Madrid, 28049 Madrid, Spain
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Electronics 2019, 8(10), 1116; https://doi.org/10.3390/electronics8101116
Received: 25 August 2019 / Revised: 26 September 2019 / Accepted: 1 October 2019 / Published: 3 October 2019
The use of Hardware-in-the-Loop (HIL) systems implemented in Field Programmable Gate Arrays (FPGAs) is constantly increasing because of its advantages compared to traditional simulation techniques. This increase in usage has caused new challenges related to the improvement of their performance and features like the number of output channels, while the price of HIL systems is diminishing. At present, the use of low-speed Digital-to-Analog Converters (DACs) is starting to be a commercial possibility because of two reasons. One is their lower price and the other is their lower pin count, which determines the number and price of the FPGAs that are necessary to handle those DACs. This paper compares four filtering approaches for providing suitable data to low-speed DACs, which help to filter high-speed input signals, discarding the need of using expensive high-speed DACS, and therefore decreasing the total cost of HIL implementations. Results show that the selection of the appropriate filter should be based on the type of the input waveform and the relative importance of the dynamics versus the area.
Keywords: Hardware-in-the-Loop; real-time simulation; FPGA; low-speed DAC; adaptive filtering Hardware-in-the-Loop; real-time simulation; FPGA; low-speed DAC; adaptive filtering
MDPI and ACS Style

Yushkova, M.; Sanchez, A.; de Castro, A.; Martínez-García, M.S. A Comparison of Filtering Approaches Using Low-Speed DACs for Hardware-in-the-Loop Implemented in FPGAs. Electronics 2019, 8, 1116.

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