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Open AccessEditor’s ChoiceArticle

A Latency-Insensitive Design Approach to Programmable FPGA-Based Real-Time Simulators

1
Department of Electrical Engineering, Polytechnique Montréal, Montréal, QC H3T 1J4, Canada
2
MOTCE Laboratory, Department of Computer Engineering, Polytechnique Montréal, Montréal, QC H3T 1J4, Canada
*
Authors to whom correspondence should be addressed.
Electronics 2020, 9(11), 1838; https://doi.org/10.3390/electronics9111838
Received: 5 October 2020 / Revised: 26 October 2020 / Accepted: 30 October 2020 / Published: 3 November 2020
This paper presents a methodology for the design of field-programmable gate array (FPGA)-based real-time simulators (RTSs) for power electronic circuits (PECs). The programmability of the simulator results from the use of an efficient and scalable overlay architecture (OA). The proposed OA relies on a latency-insensitive design (LID) paradigm. LID consists of connecting small processing units that automatically synchronize and exchange data when appropriate. The use of such data-driven architecture aims to ease the design process while achieving a higher computational efficiency. The benefits of the proposed approach is evaluated by assessing the performance of the proposed solver in the simulation of a two-stage AC–AC power converter. The minimum achievable time-step and FPGA resource consumption for a wide range of power converter sizes is also evaluated. The proposed overlays are parametrizable in size, they are cost-effective, they provide sub-microsecond time-steps, and they offer a high computational performance with a reported peak performance of 300 GFLOPS. View Full-Text
Keywords: real-time simulation; HIL; power electronic circuits; FPGA; latency-insensitive design; data-driven architectures real-time simulation; HIL; power electronic circuits; FPGA; latency-insensitive design; data-driven architectures
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MDPI and ACS Style

Montaño, F.; Ould-Bachir, T.; David, J.P. A Latency-Insensitive Design Approach to Programmable FPGA-Based Real-Time Simulators. Electronics 2020, 9, 1838. https://doi.org/10.3390/electronics9111838

AMA Style

Montaño F, Ould-Bachir T, David JP. A Latency-Insensitive Design Approach to Programmable FPGA-Based Real-Time Simulators. Electronics. 2020; 9(11):1838. https://doi.org/10.3390/electronics9111838

Chicago/Turabian Style

Montaño, Federico; Ould-Bachir, Tarek; David, Jean P. 2020. "A Latency-Insensitive Design Approach to Programmable FPGA-Based Real-Time Simulators" Electronics 9, no. 11: 1838. https://doi.org/10.3390/electronics9111838

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