Special Issue "Real-Time Embedded Systems"

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: closed (31 January 2018).

Printed Edition Available!
A printed edition of this Special Issue is available here.

Special Issue Editors

Guest Editor
Dr. Christos Koulamas

Industrial Systems Institute / “Athena” Research Center, PSP Bldg, Stadiou Strt, 26504, Patras, Greece
Website | E-Mail
Interests: real-time distributed embedded systems; wired/wireless industrial networks; Industrial IoT; WSN/ RFID systems
Guest Editor
Dr. Mihai T. Lazarescu

Dipartimento di Elettronica e Telecomunicazioni Politecnico di Torino Turin, Italy
E-Mail
Interests: cost- and energy-efficient design of wireless sensor nodes; high-level synthesis of wireless sensor applications; distributed data processing on embedded devices, learning, adaptability; efficient and secure communication, privacy

Special Issue Information

Dear Colleagues,

Real-time and networked embedded systems are crucial bridges between the physical and the information worlds in the ever growing embedded intelligence pervasiveness in industry, infrastructure, and in public and private spaces. They have been identified as society and economy emerging “neural systems”, and as one of the next big concepts supporting societal changes and economic growth. Intelligence is increasingly embedded in everyday life connected objects, fostered by cost/performance improvements and by the spread to wider application fields of the specialized technologies and engineering disciplines once tightened in silo domains. While this process gradually builds the IoT, it starts to expose non trivial timing and other extra functional requirements and system properties, which are less common to typical computing.

This Special Issue is dedicated to the specificities of cyberphysical and real time embedded systems that are present both in traditional relevant application domains, such as industrial automation and control, energy management, automotive, aerospace and defense systems, as well as in emerging domains, such as in medical devices, household appliances, mobile multimedia, gaming, and entertainment systems. We solicit state-of-the-art original research contributions in topics that include, but are not limited to:

  • Industrial use-cases and applications of real-time embedded systems: design, implementation and performance evaluation
  • Modeling, formal methods, simulation and development tools for real-time and networked embedded systems
  • Real-time embedded systems design: energy management, dynamic reconfiguration, QoS, heterogeneity and interoperability
  • Formal methods, timing analysis, scheduling design, analysis and verification
  • Hardware/software co-design, synthesis, reconfigurable hardware, real-time network- and system on chip
  • Wireless sensor networks (WSNs), RFID and time-sensitive components and applications
  • Real-time networks, network management and time synchronization
  • Real-time embedded operating systems (RTOS) and middleware, resource management, resource usage optimization
  • Real-time virtualization and hypervisors, real-time Java and Linux for embedded systems
  • Security, dependability and fault tolerance of real-time and distributed embedded systems

Dr. Christos Koulamas
Dr. Mihai Teodor Lazarescu
Guest Editors

Manuscript Submission Information

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Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Published Papers (11 papers)

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Editorial

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Open AccessEditorial
Real-Time Embedded Systems: Present and Future
Electronics 2018, 7(9), 205; https://doi.org/10.3390/electronics7090205
Received: 10 September 2018 / Accepted: 14 September 2018 / Published: 18 September 2018
Cited by 4 | PDF Full-text (152 KB) | HTML Full-text | XML Full-text
(This article belongs to the Special Issue Real-Time Embedded Systems) Printed Edition available

Research

Jump to: Editorial

Open AccessArticle
Energy-Efficient Scheduling of Periodic Applications on Safety-Critical Time-Triggered Multiprocessor Systems
Electronics 2018, 7(6), 98; https://doi.org/10.3390/electronics7060098
Received: 9 May 2018 / Revised: 12 June 2018 / Accepted: 14 June 2018 / Published: 19 June 2018
Cited by 1 | PDF Full-text (603 KB) | HTML Full-text | XML Full-text
Abstract
Energy optimization for periodic applications running on safety/time-critical time-triggered multiprocessor systems has been studied recently. An interesting feature of the applications on the systems is that some tasks are strictly periodic while others are non-strictly periodic, i.e., the start time interval between any [...] Read more.
Energy optimization for periodic applications running on safety/time-critical time-triggered multiprocessor systems has been studied recently. An interesting feature of the applications on the systems is that some tasks are strictly periodic while others are non-strictly periodic, i.e., the start time interval between any two successive instances of the same task is not fixed as long as task deadlines can be met. Energy-efficient scheduling of such applications on the systems has, however, been rarely investigated. In this paper, we focus on the problem of static scheduling multiple periodic applications consisting of both strictly and non-strictly periodic tasks on safety/time-critical time-triggered multiprocessor systems for energy minimization. The challenge of the problem is that both strictly and non-strictly periodic tasks must be intelligently addressed in scheduling to optimize energy consumption. We introduce a new practical task model to characterize the unique feature of specific tasks, and formulate the energy-efficient scheduling problem based on the model. Then, an improved Mixed Integer Linear Programming (MILP) method is proposed to obtain the optimal scheduling solution by considering strict and non-strict periodicity of the specific tasks. To decrease the high complexity of MILP, we also develop a heuristic algorithm to efficiently find a high-quality solution in reasonable time. Extensive evaluation results demonstrate the proposed MILP and heuristic methods can on average achieve about 14.21% and 13.76% energy-savings respectively compared with existing work. Full article
(This article belongs to the Special Issue Real-Time Embedded Systems) Printed Edition available
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Open AccessArticle
Real-Time Ventricular Fibrillation Detection Using an Embedded Microcontroller in a Pervasive Environment
Electronics 2018, 7(6), 88; https://doi.org/10.3390/electronics7060088
Received: 1 May 2018 / Revised: 26 May 2018 / Accepted: 30 May 2018 / Published: 3 June 2018
Cited by 2 | PDF Full-text (6059 KB) | HTML Full-text | XML Full-text
Abstract
Many healthcare problems are life threatening and need real-time detection to improve patient safety. Heart attack or ventricular fibrillation (VF) is a common problem worldwide. Most previous research on VF detection has used ECG devices to capture data and sent to other higher [...] Read more.
Many healthcare problems are life threatening and need real-time detection to improve patient safety. Heart attack or ventricular fibrillation (VF) is a common problem worldwide. Most previous research on VF detection has used ECG devices to capture data and sent to other higher performance units for processing and has relied on domain experts and/or sophisticated algorithms for detection. In this case, it delayed the response time and consumed much more energy of the ECG module. In this study, we propose a prototype that an embedded microcontroller where an ECG sensor is used to capture, filter and process data, run VF detection algorithms, and only transmit the detected event to the smartphone for alert and call for services. We discuss how to adapt a common filtering and scale process and five light-weighted algorithms from open literature to realize the idea. We also develop an integrated prototype, which emulates the VF process from existing data sets, to evaluate the detection capability of the framework and algorithms. Our results show that (1) TD outperforms the other four algorithms considered with sensitivity reaching 96.56% and specificity reaching 81.53% in the MIT-BIH dataset. Our evaluations confirm that with some adaptation the conventional filtering process and detection algorithms can be efficiently deployed in a microcontroller with good detection accuracy while saving battery power, shortening response time, and conserving the network bandwidth. Full article
(This article belongs to the Special Issue Real-Time Embedded Systems) Printed Edition available
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Open AccessArticle
Automated Scalable Address Generation Patterns for 2-Dimensional Folding Schemes in Radix-2 FFT Implementations
Electronics 2018, 7(3), 33; https://doi.org/10.3390/electronics7030033
Received: 30 December 2017 / Revised: 19 February 2018 / Accepted: 1 March 2018 / Published: 3 March 2018
Cited by 2 | PDF Full-text (1573 KB) | HTML Full-text | XML Full-text
Abstract
Hardware-based implementations of the Fast Fourier Transform (FFT) are highly regarded as they provide improved performance characteristics with respect to software-based sequential solutions. Due to the high number of operations involved in calculations, most hardware-based FFT approaches completely or partially fold their structure [...] Read more.
Hardware-based implementations of the Fast Fourier Transform (FFT) are highly regarded as they provide improved performance characteristics with respect to software-based sequential solutions. Due to the high number of operations involved in calculations, most hardware-based FFT approaches completely or partially fold their structure to achieve an efficient use of resources. A folding operation requires a permutation block, which is typically implemented using either permutation logic or address generation. Addressing schemes offer resource-efficient advantages when compared to permutation logic. We propose a systematic and scalable procedure for generating permutation-based address patterns for any power-of-2 transform size algorithm and any folding factor in FFT cores. To support this procedure, we develop a mathematical formulation based on Kronecker products algebra for address sequence generation and data flow pattern in FFT core computations, a well-defined procedure for scaling address generation schemes, and an improved approach in the overall automated generation of FFT cores. We have also performed an analysis and comparison of the proposed hardware design performance with respect to a similar strategy reported in the recent literature in terms of clock latency, performance, and hardware resources. Evaluations were carried on a Xilinx Virtex-7 FPGA (Field Programmable Gate Array) used as implementation target. Full article
(This article belongs to the Special Issue Real-Time Embedded Systems) Printed Edition available
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Open AccessArticle
An Energy Box in a Cloud-Based Architecture for Autonomous Demand Response of Prosumers and Prosumages
Electronics 2017, 6(4), 98; https://doi.org/10.3390/electronics6040098
Received: 11 September 2017 / Revised: 2 November 2017 / Accepted: 9 November 2017 / Published: 16 November 2017
Cited by 8 | PDF Full-text (7264 KB) | HTML Full-text | XML Full-text
Abstract
The interest in the implementation of demand response programs for domestic customers within the framework of smart grids is increasing, both from the point of view of scientific research and from the point of view of real applications through pilot projects. A fundamental [...] Read more.
The interest in the implementation of demand response programs for domestic customers within the framework of smart grids is increasing, both from the point of view of scientific research and from the point of view of real applications through pilot projects. A fundamental element of any demand response program is the introduction at customer level of a device, generally named energy box, able to allow interaction between customers and the aggregator. This paper proposes two laboratory prototypes of a low-cost energy box, suitable for cloud-based architectures for autonomous demand response of prosumers and prosumages. Details on how these two prototypes have been designed and built are provided in the paper. Both prototypes are tested in the laboratory along with a demonstration panel of a residential unit, equipped with a real home automation system. Laboratory tests demonstrate the feasibility of the proposed prototypes and their capability in executing the customers’ loads scheduling returned by the solution of the demand-response problem. A personal computer and Matlab software implement the operation of the aggregator, i.e., the intermediary of the energy-integrated community constituted by the customers themselves, who participate in the demand response program. Full article
(This article belongs to the Special Issue Real-Time Embedded Systems) Printed Edition available
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Open AccessArticle
μRTZVisor: A Secure and Safe Real-Time Hypervisor
Electronics 2017, 6(4), 93; https://doi.org/10.3390/electronics6040093
Received: 29 September 2017 / Accepted: 24 October 2017 / Published: 30 October 2017
Cited by 3 | PDF Full-text (2123 KB) | HTML Full-text | XML Full-text
Abstract
Virtualization has been deployed as a key enabling technology for coping with the ever growing complexity and heterogeneity of modern computing systems. However, on its own, classical virtualization is a poor match for modern endpoint embedded system requirements such as safety, security and [...] Read more.
Virtualization has been deployed as a key enabling technology for coping with the ever growing complexity and heterogeneity of modern computing systems. However, on its own, classical virtualization is a poor match for modern endpoint embedded system requirements such as safety, security and real-time, which are our main target. Microkernel-based approaches to virtualization have been shown to bridge the gap between traditional and embedded virtualization. This notwithstanding, existent microkernel-based solutions follow a highly para-virtualized approach, which inherently requires a significant software engineering effort to adapt guest operating systems (OSes) to run as userland components. In this paper, we present μ RTZVisor as a new TrustZone-assisted hypervisor that distinguishes itself from state-of-the-art TrustZone solutions by implementing a microkernel-like architecture while following an object-oriented approach. Contrarily to existing microkernel-based solutions, μ RTZVisor is able to run nearly unmodified guest OSes, while, contrarily to existing TrustZone-assisted solutions, it provides a high degree of functionality and configurability, placing strong emphasis on the real-time support. Our hypervisor was deployed and evaluated on a Xilinx Zynq-based platform. Experiments demonstrate that the hypervisor presents a small trusted computing base size (approximately 60KB), and a performance overhead of less than 2% for a 10 ms guest-switching rate. Full article
(This article belongs to the Special Issue Real-Time Embedded Systems) Printed Edition available
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Open AccessFeature PaperArticle
Pipelined Architecture of Multi-Band Spectral Subtraction Algorithm for Speech Enhancement
Electronics 2017, 6(4), 73; https://doi.org/10.3390/electronics6040073
Received: 29 August 2017 / Revised: 26 September 2017 / Accepted: 27 September 2017 / Published: 29 September 2017
Cited by 3 | PDF Full-text (3823 KB) | HTML Full-text | XML Full-text
Abstract
In this paper, a new pipelined architecture of the multi-band spectral subtraction algorithm has been proposed for real-time speech enhancement. The proposed hardware has been implemented on field programmable gate array (FPGA) device using Xilinx system generator (XSG), high-level programming tool, and Nexys-4 [...] Read more.
In this paper, a new pipelined architecture of the multi-band spectral subtraction algorithm has been proposed for real-time speech enhancement. The proposed hardware has been implemented on field programmable gate array (FPGA) device using Xilinx system generator (XSG), high-level programming tool, and Nexys-4 development board. The multi-band algorithm has been developed to reduce the additive colored noise that does not uniformly affect the entire frequency band of useful signal. All the algorithm steps have been successfully implemented on hardware. Pipelining has been employed on this hardware architecture to increase the data throughput. Speech enhancement performances obtained by the hardware architecture are compared to those obtained by MATLAB simulation using simulated and actual noises. The resource utilization, the maximum operating frequency, and power consumption are reported for a low-cost Artix-7 FPGA device. Full article
(This article belongs to the Special Issue Real-Time Embedded Systems) Printed Edition available
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Open AccessArticle
A Formally Reliable Cognitive Middleware for the Security of Industrial Control Systems
Electronics 2017, 6(3), 58; https://doi.org/10.3390/electronics6030058
Received: 31 May 2017 / Revised: 21 July 2017 / Accepted: 8 August 2017 / Published: 11 August 2017
Cited by 1 | PDF Full-text (312 KB) | HTML Full-text | XML Full-text
Abstract
In this paper, we present our results on the formal reliability analysis of the behavioral correctness of our cognitive middleware ARMET. The formally assured behavioral correctness of a software system is a fundamental prerequisite for the system’s security. Therefore, the goal of this [...] Read more.
In this paper, we present our results on the formal reliability analysis of the behavioral correctness of our cognitive middleware ARMET. The formally assured behavioral correctness of a software system is a fundamental prerequisite for the system’s security. Therefore, the goal of this study is to, first, formalize the behavioral semantics of the middleware and, second, to prove its behavioral correctness. In this study, we focus only on the core and critical component of the middleware: the execution monitor. The execution monitor identifies inconsistencies between runtime observations of an industrial control system (ICS) application and predictions of the specification of the application. As a starting point, we have defined the formal (denotational) semantics of the observations (produced by the application at run-time), and predictions (produced by the executable specification of the application). Then, based on the formal semantices, we have formalized the behavior of the execution monitor. Finally, based on the semantics, we have proved soundness (absence of false alarms) and completeness (detection of arbitrary attacks) to assure the behavioral correctness of the monitor. Full article
(This article belongs to the Special Issue Real-Time Embedded Systems) Printed Edition available
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Open AccessArticle
A Data Compression Hardware Accelerator Enabling Long-Term Biosignal Monitoring Based on Ultra-Low Power IoT Platforms
Electronics 2017, 6(3), 54; https://doi.org/10.3390/electronics6030054
Received: 31 May 2017 / Revised: 20 July 2017 / Accepted: 27 July 2017 / Published: 31 July 2017
Cited by 2 | PDF Full-text (1950 KB) | HTML Full-text | XML Full-text
Abstract
For highly demanding scenarios such as continuous bio-signal monitoring, transmitting excessive volumes of data wirelessly comprises one of the most critical challenges. This is due to the resource limitations posed by typical hardware and communication technologies. Driven by such shortcomings, this paper aims [...] Read more.
For highly demanding scenarios such as continuous bio-signal monitoring, transmitting excessive volumes of data wirelessly comprises one of the most critical challenges. This is due to the resource limitations posed by typical hardware and communication technologies. Driven by such shortcomings, this paper aims at addressing the respective deficiencies. The main axes of this work include (a) data compression, and (b) the presentation of a complete, efficient and practical hardware accelerator design able to be integrated in any Internet of Things (IoT) platform for addressing critical challenges of data compression. On one hand, the developed algorithm is presented and evaluated on software, exhibiting significant benefits compared to respective competition. On the other hand, the algorithm is fully implemented on hardware providing a further proof of concept regarding the implementation feasibility with respect to state-of-the art hardware design approaches. Finally, system-level performance benefits, regarding data transmission delay and energy saving, are highlighted, taking into consideration the characteristics of prominent IoT platforms. Concluding, this paper presents a holistic approach based on data compression that is able to drastically enhance an IoT platform’s performance and tackle efficiently a notorious challenge of highly demanding IoT applications such as real-time bio-signal monitoring. Full article
(This article belongs to the Special Issue Real-Time Embedded Systems) Printed Edition available
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Open AccessArticle
Exploiting Hardware Vulnerabilities to Attack Embedded System Devices: a Survey of Potent Microarchitectural Attacks
Electronics 2017, 6(3), 52; https://doi.org/10.3390/electronics6030052
Received: 31 May 2017 / Revised: 29 June 2017 / Accepted: 4 July 2017 / Published: 13 July 2017
Cited by 6 | PDF Full-text (223 KB) | HTML Full-text | XML Full-text
Abstract
Cyber-Physical system devices nowadays constitute a mixture of Information Technology (IT) and Operational Technology (OT) systems that are meant to operate harmonically under a security critical framework. As security IT countermeasures are gradually been installed in many embedded system nodes, thus securing them [...] Read more.
Cyber-Physical system devices nowadays constitute a mixture of Information Technology (IT) and Operational Technology (OT) systems that are meant to operate harmonically under a security critical framework. As security IT countermeasures are gradually been installed in many embedded system nodes, thus securing them from many well-know cyber attacks there is a lurking danger that is still overlooked. Apart from the software vulnerabilities that typical malicious programs use, there are some very interesting hardware vulnerabilities that can be exploited in order to mount devastating software or hardware attacks (typically undetected by software countermeasures) capable of fully compromising any embedded system device. Real-time microarchitecture attacks such as the cache side-channel attacks are such case but also the newly discovered Rowhammer fault injection attack that can be mounted even remotely to gain full access to a device DRAM (Dynamic Random Access Memory). Under the light of the above dangers that are focused on the device hardware structure, in this paper, an overview of this attack field is provided including attacks, threat directives and countermeasures. The goal of this paper is not to exhaustively overview attacks and countermeasures but rather to survey the various, possible, existing attack directions and highlight the security risks that they can pose to security critical embedded systems as well as indicate their strength on compromising the Quality of Service (QoS) such systems are designed to provide. Full article
(This article belongs to the Special Issue Real-Time Embedded Systems) Printed Edition available
Open AccessArticle
Real-Time and High-Accuracy Arctangent Computation Using CORDIC and Fast Magnitude Estimation
Electronics 2017, 6(1), 22; https://doi.org/10.3390/electronics6010022
Received: 11 February 2017 / Revised: 9 March 2017 / Accepted: 13 March 2017 / Published: 16 March 2017
Cited by 4 | PDF Full-text (1959 KB) | HTML Full-text | XML Full-text
Abstract
This paper presents an improved VLSI (Very Large Scale of Integration) architecture for real-time and high-accuracy computation of trigonometric functions with fixed-point arithmetic, particularly arctangent using CORDIC (Coordinate Rotation Digital Computer) and fast magnitude estimation. The standard CORDIC implementation suffers of a loss [...] Read more.
This paper presents an improved VLSI (Very Large Scale of Integration) architecture for real-time and high-accuracy computation of trigonometric functions with fixed-point arithmetic, particularly arctangent using CORDIC (Coordinate Rotation Digital Computer) and fast magnitude estimation. The standard CORDIC implementation suffers of a loss of accuracy when the magnitude of the input vector becomes small. Using a fast magnitude estimator before running the standard algorithm, a pre-processing magnification is implemented, shifting the input coordinates by a proper factor. The entire architecture does not use a multiplier, it uses only shift and add primitives as the original CORDIC, and it does not change the data path precision of the CORDIC core. A bit-true case study is presented showing a reduction of the maximum phase error from 414 LSB (angle error of 0.6355 rad) to 4 LSB (angle error of 0.0061 rad), with small overheads of complexity and speed. Implementation of the new architecture in 0.18 µm CMOS technology allows for real-time and low-power processing of CORDIC and arctangent, which are key functions in many embedded DSP systems. The proposed macrocell has been verified by integration in a system-on-chip, called SENSASIP (Sensor Application Specific Instruction-set Processor), for position sensor signal processing in automotive measurement applications. Full article
(This article belongs to the Special Issue Real-Time Embedded Systems) Printed Edition available
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