Special Issue "Radiation Tolerant Electronics"

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Microelectronics and Optoelectronics".

Deadline for manuscript submissions: closed (30 April 2019).

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Special Issue Editor

Prof. Dr. Paul Leroux
Website
Guest Editor
Advanced Integrated Sensing Lab (ADVISE), KU Leuven, Leuven, Belgium
Interests: radiation hardening by design; IC design; analog; mixed-signal; RF
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Special Issue Information

Dear Colleagues,

Research on radiation tolerant electronics has increased rapidly over the last few years, resulting in many interesting approaches to model radiation effects and design radiation hardened integrated circuits and embedded systems. This research is strongly driven by the growing need for radiation hardened electronics for space applications, high-energy physics experiments such as those on the large hadron collider at CERN, and many terrestrial nuclear applications, including nuclear energy and safety management. With the progressive scaling of integrated circuit technologies and the growing complexity of electronic systems, their ionizing radiation susceptibility has raised many exciting challenges which are expected to drive research in the coming decade. Even though total ionizing dose effects in bulk CMOS is well known, still little is known on the radiation performance of advanced (FD-)SOI and FinFET technologies. Regarding single-event effects, the continued scaling has drastically increased the number of multiple-transistor or multiple-cell upsets which requires new solutions to reduce the error rate in digital and mixed-signal ASICs but also for FPGAs. Radiation hardness assurance of complex systems with multiple components in mixed technologies also necessitates new testing paradigms and verification methodologies to limit the time and cost for evaluation.

The main aim of this Special Issue is to seek high-quality submissions that highlight emerging applications, address recent breakthroughs in modeling radiation effects in advanced electronic devices and circuits, the design of radiation hardened analog, mixed-signal, RF and digital integrated circuits and radiation hardness testing methodologies. The topics of interest include, but are not limited to:

  • Basic mechanisms of radiation effects in electronic devices
  • Compact modeling of radiation effects and circuit/layout level optimization (TID and SEE)
  • Radiation effects in power devices/circuits
  • Design of radiation hardened integrated circuits (analog/RF/mixed-signal/digital)
  • Radiation hardening and fault tolerance in FPGAs
  • Radiation hardness assurance testing

Prof. Dr. Paul Leroux
Guest Editor

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Published Papers (16 papers)

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Editorial

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Open AccessEditorial
Radiation Tolerant Electronics
Electronics 2019, 8(7), 730; https://doi.org/10.3390/electronics8070730 - 27 Jun 2019
Cited by 3
Abstract
Research on radiation tolerant electronics has increased rapidly over the last few years, resulting in many interesting approaches to model radiation effects and design radiation hardened integrated circuits and embedded systems [...] Full article
(This article belongs to the Special Issue Radiation Tolerant Electronics) Printed Edition available

Research

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Open AccessArticle
RHBD Techniques to Mitigate SEU and SET in CMOS Frequency Synthesizers
Electronics 2019, 8(6), 690; https://doi.org/10.3390/electronics8060690 - 19 Jun 2019
Cited by 3
Abstract
This paper presents a thorough study of radiation effects on a frequency synthesizer designed in a 0.18 μm CMOS technology. In CMOS devices, the effect of a high energy particle impact can be modeled by a current pulse connected to the drain [...] Read more.
This paper presents a thorough study of radiation effects on a frequency synthesizer designed in a 0.18 μ m CMOS technology. In CMOS devices, the effect of a high energy particle impact can be modeled by a current pulse connected to the drain of the transistors. The effects of SET (single event transient) and SEU (single event upset) were analyzed connecting current pulses to the drains of all the transistors and analyzing the amplitude variations and phase shifts obtained at the output nodes. Following this procedure, the most sensitive circuits were detected. This paper proposes a combination of radiation hardening-by-design techniques (RHBD) such as resistor–capacitor (RC) filtering or local circuit-redundancy to mitigate the effects of radiation. The proposed modifications make the frequency synthesizer more robust against radiation. Full article
(This article belongs to the Special Issue Radiation Tolerant Electronics) Printed Edition available
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Open AccessArticle
Mechanism of Degradation Rate on the Irradiated Double-Polysilicon Self-Aligned Bipolar Transistor
Electronics 2019, 8(6), 657; https://doi.org/10.3390/electronics8060657 - 11 Jun 2019
Cited by 2
Abstract
The latent enhanced low dose rate sensitivity (ELDRS) effect is observed in the double-polysilicon self-aligned (DPSA) technology PNP bipolar junction transistor (BJT) irradiated with a high and low dose rate gamma ray, which is discussed from the perspective of the three-stage degradation rate [...] Read more.
The latent enhanced low dose rate sensitivity (ELDRS) effect is observed in the double-polysilicon self-aligned (DPSA) technology PNP bipolar junction transistor (BJT) irradiated with a high and low dose rate gamma ray, which is discussed from the perspective of the three-stage degradation rate of the excess base current. The great degradation rate as a result of the high dose irradiation of the first stage is dominantly ascribed to the positive oxide trap charges accumulated during a short irradiation, and then due to the competition between the recombination of electrons and capture of the hole by the traps. It declined sharply into a degradation rate saturated region of the second stage. However, for the low dose rate, the small increase in the degradation rate in the first stage is caused by the holes escaping from the initial recombination and being transported to the interface to form the interface states. Then, the competition between the steadily increasing interfacial trap charge and the continuously annealed shallow level oxide trap charge leads to the stable increase of degradation under low dose irradiation. Finally, in stage three, the increases of the degradation rates for high and low dose irradiation result from the different amounts of the hydrogen molecules generated by the hole reactive with depassiviated Si suspended bonds, which can interact with the deep level defects and release protons, causing an increase of interfacial trap charges with prolonged irradiation. Full article
(This article belongs to the Special Issue Radiation Tolerant Electronics) Printed Edition available
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Open AccessArticle
A Compact Model to Evaluate the Effects of High Level C++ Code Hardening in Radiation Environments
Electronics 2019, 8(6), 653; https://doi.org/10.3390/electronics8060653 - 10 Jun 2019
Cited by 4
Abstract
A high-level C++ hardening library is designed for the protection of critical software against the harmful effects of radiation environments that can damage systems. A mathematical and empirical model to predict system behavior in the presence of radiation induced faults is also presented. [...] Read more.
A high-level C++ hardening library is designed for the protection of critical software against the harmful effects of radiation environments that can damage systems. A mathematical and empirical model to predict system behavior in the presence of radiation induced faults is also presented. This model generates a quick evaluation and adjustment of several reliability vs. performance trade-offs, to optimize radiation hardening based on the proposed C++ hardening library. Several simulations and irradiation campaigns with protons and neutrons are used to build the model and to tune it. Finally, the effects of our hardening approach are compared with other hardened and non-hardened approaches. Full article
(This article belongs to the Special Issue Radiation Tolerant Electronics) Printed Edition available
Open AccessArticle
Single Event Transients in CMOS Ring Oscillators
Electronics 2019, 8(6), 618; https://doi.org/10.3390/electronics8060618 - 01 Jun 2019
Cited by 2
Abstract
In this paper, a time-variant analysis is made on Single-Event Transients (SETs) in integrated CMOS ring oscillators. The Impulse Sensitive Function (ISF) of the oscillator is used to analyze the impact of the relative moment when a particle hits the circuit. The analysis [...] Read more.
In this paper, a time-variant analysis is made on Single-Event Transients (SETs) in integrated CMOS ring oscillators. The Impulse Sensitive Function (ISF) of the oscillator is used to analyze the impact of the relative moment when a particle hits the circuit. The analysis is based on simulations and verified experimentally with a Two-Photon Absorption (TPA) laser setup. The experiments are done using a 65 nm CMOS test chip. Full article
(This article belongs to the Special Issue Radiation Tolerant Electronics) Printed Edition available
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Open AccessArticle
Optimization of the Cell Structure for Radiation-Hardened Power MOSFETs
Electronics 2019, 8(6), 598; https://doi.org/10.3390/electronics8060598 - 28 May 2019
Cited by 3
Abstract
Power MOSFETs specially designed for space power systems are expected to simultaneously meet the requirements of electrical performance and radiation hardness. Radiation-hardened (rad-hard) power MOSFET design can be achieved via cell structure optimization. This paper conducts an investigation of the cell geometrical parameters [...] Read more.
Power MOSFETs specially designed for space power systems are expected to simultaneously meet the requirements of electrical performance and radiation hardness. Radiation-hardened (rad-hard) power MOSFET design can be achieved via cell structure optimization. This paper conducts an investigation of the cell geometrical parameters with major impacts on radiation hardness, and a rad-hard power MOSFET is designed and fabricated. The experimental results validate the devices’ total ionizing dose (TID) and single event effects (SEE) hardness to suitably satisfy most space power system requirements while maintaining acceptable electrical performance. Full article
(This article belongs to the Special Issue Radiation Tolerant Electronics) Printed Edition available
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Open AccessArticle
Low-Power, Subthreshold Reference Circuits for the Space Environment: Evaluated with γ-rays, X-rays, Protons and Heavy Ions
Electronics 2019, 8(5), 562; https://doi.org/10.3390/electronics8050562 - 21 May 2019
Cited by 2
Abstract
The radiation tolerance of subthreshold reference circuits for space microelectronics is presented. The assessment is supported by measured results of total ionization dose and single event transient radiation-induced effects under γ-rays, X-rays, protons and heavy ions (silicon, krypton and xenon). A high [...] Read more.
The radiation tolerance of subthreshold reference circuits for space microelectronics is presented. The assessment is supported by measured results of total ionization dose and single event transient radiation-induced effects under γ -rays, X-rays, protons and heavy ions (silicon, krypton and xenon). A high total irradiation dose with different radiation sources was used to evaluate the proposed topologies for a wide range of applications operating in harsh environments similar to the space environment. The proposed custom designed integrated circuits (IC) circuits utilize only CMOS transistors, operating in the subthreshold regime, and poly-silicon resistors without using any external components such as compensation capacitors. The circuits are radiation hardened by design (RHBD) and they were fabricated using TowerJazz Semiconductor’s 0.18 μm standard CMOS technology. The proposed voltage references are shown to be suitable for high-precision and low-power space applications. It is demonstrated that radiation hardened microelectronics operating in subthreshold regime are promising candidates for significantly reducing the size and cost of space missions due to reduced energy requirements. Full article
(This article belongs to the Special Issue Radiation Tolerant Electronics) Printed Edition available
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Open AccessFeature PaperArticle
Radiation Assessment of a 15.6ps Single-Shot Time-to-Digital Converter in Terms of TID
Electronics 2019, 8(5), 558; https://doi.org/10.3390/electronics8050558 - 18 May 2019
Cited by 4
Abstract
This article presents a radiation tolerant single-shot time-to-digital converter (TDC) with a resolution of 15.6 ps, fabricated in a 65 nm complementary metal oxide semiconductor (CMOS) technology. The TDC is based on a multipath pseudo differential ring oscillator with reduced phase delay, without [...] Read more.
This article presents a radiation tolerant single-shot time-to-digital converter (TDC) with a resolution of 15.6 ps, fabricated in a 65 nm complementary metal oxide semiconductor (CMOS) technology. The TDC is based on a multipath pseudo differential ring oscillator with reduced phase delay, without the need for calibration or interpolation. The ring oscillator is placed inside a Phase Locked Loop (PLL) to compensate for Process, Voltage and Temperature (PVT) variations- and variations due to ionizing radiation. Measurements to evaluate the performance of the TDC in terms of the total ionizing dose (TID) were done. Two different samples were irradiated up to a dose of 2.2 MGy SiO 2 while still maintaining a resolution of 15.6 ps. The TDC has a differential non-linearity (DNL) and integral non-linearity (INL) of 0.22 LSB rms and 0.34 LSB rms respectively. Full article
(This article belongs to the Special Issue Radiation Tolerant Electronics) Printed Edition available
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Open AccessArticle
Proton Induced Single Event Effect Characterization on a Highly Integrated RF-Transceiver
Electronics 2019, 8(5), 519; https://doi.org/10.3390/electronics8050519 - 09 May 2019
Cited by 3
Abstract
Radio frequency (RF) systems in space applications are usually designed for a single task and its requirements. Flexibility is mostly limited to software-defined adaption of the signal processing in digital signal processors (DSP) or field-programmable gate arrays (FPGA). RF specifications, such as frequency [...] Read more.
Radio frequency (RF) systems in space applications are usually designed for a single task and its requirements. Flexibility is mostly limited to software-defined adaption of the signal processing in digital signal processors (DSP) or field-programmable gate arrays (FPGA). RF specifications, such as frequency band selection or RF filter bandwidth are thereby restricted to the specific application requirements. New radio frequency integrated circuit (RFIC) devices also allow the software-based reconfiguration of various RF specifications. A transfer of this RFIC technology to space systems would have a massive impact to future radio systems for space applications. The benefit of this RFIC technology allows a selection of different RF radio applications, independent of their RF parameters, to be executed on a single unit and, thus, reduces the size and weight of the whole system. Since most RF application sin space system require a high level of reliability and the RFIC is not designed for the harsh environment in space, a characterization under these special environmental conditions is mandatory. In this paper, we present the single event effect (SEE) characterization of a selected RFIC device under proton irradiation. The RFIC being tested is immune to proton induced single event latch-up and other destructive events and shows a very low response to single failure interrupts. Thus, the device is defined as a good candidate for future, highly integrated radio system in space applications. Full article
(This article belongs to the Special Issue Radiation Tolerant Electronics) Printed Edition available
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Open AccessFeature PaperArticle
A Novel Modular Radiation Hardening Approach Applied to a Synchronous Buck Converter
Electronics 2019, 8(5), 513; https://doi.org/10.3390/electronics8050513 - 08 May 2019
Cited by 2
Abstract
Radiation and extreme temperature are the main inhibitors for the use of electronic devices in space applications. Radiation challenges the normal and stable operation of DC-DC converters, used as power supply for onboard systems in satellites and spacecrafts. In this situation, special design [...] Read more.
Radiation and extreme temperature are the main inhibitors for the use of electronic devices in space applications. Radiation challenges the normal and stable operation of DC-DC converters, used as power supply for onboard systems in satellites and spacecrafts. In this situation, special design techniques known as radiation hardening or radiation tolerant designs have to be employed. In this work, a module level design approach for radiation hardening is addressed. A module in this sense is a constituent of a digital controller, which includes an analog to digital converter (ADC), a digital proportional-integral-derivative (PID) controller, and a digital pulse width modulator (DPWM). As a new Radiation Hardening by Design technique (RHBD), a four module redundancy technique is proposed and applied to the digital voltage mode controller driving a synchronous buck converter, which has been implemented as hardware-in-the-loop (HIL) simulation block in MATLAB/Simulink using Xilinx system generator based on the Zynq-7000 development board (ZYBO). The technique is compared, for reliability and hardware resources requirement, with triple modular redundancy (TMR), five modular redundancy (FMR) and the modified triplex–duplex architecture. Furthermore, radiation induced failures are emulated by switching all duplicated modules inputs to different signals, or to ground during simulation. The simulation results show that the proposed technique has 25% and 30%longer expected life compared to TMR and FMR techniques, respectively, and has the lowest hardware resource requirement compared to FMR and the modified triplex–duplex techniques. Full article
(This article belongs to the Special Issue Radiation Tolerant Electronics) Printed Edition available
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Open AccessFeature PaperArticle
Optimal Physical Implementation of Radiation Tolerant High-Speed Digital Integrated Circuits in Deep-Submicron Technologies
Electronics 2019, 8(4), 432; https://doi.org/10.3390/electronics8040432 - 14 Apr 2019
Cited by 3
Abstract
This paper presents a novel scalable physical implementation method for high-speed Triple Modular Redundant (TMR) digital integrated circuits in radiation-hard designs. The implementation uses a distributed placement strategy compared to a commonly used bulk 3-bank constraining method. TMR netlist information is used to [...] Read more.
This paper presents a novel scalable physical implementation method for high-speed Triple Modular Redundant (TMR) digital integrated circuits in radiation-hard designs. The implementation uses a distributed placement strategy compared to a commonly used bulk 3-bank constraining method. TMR netlist information is used to optimally constrain the placement of both sequential cells and combinational cells. This approach significantly reduces routing complexity, net lengths and dynamic power consumption with more than 60% and 20% respectively. The technique was simulated in a 65 nm Complementary Metal-Oxide Semiconductor (CMOS) technology. Full article
(This article belongs to the Special Issue Radiation Tolerant Electronics) Printed Edition available
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Open AccessArticle
Heavy-Ion Induced Single Event Upsets in Advanced 65 nm Radiation Hardened FPGAs
Electronics 2019, 8(3), 323; https://doi.org/10.3390/electronics8030323 - 14 Mar 2019
Cited by 6
Abstract
The 65 nm Static Random Access Memory (SRAM) based Field Programmable Gate Array (FPGA) was designed and manufactured, which employed tradeoff radiation hardening techniques in Configuration RAMs (CRAMs), Embedded RAMs (EBRAMs) and flip-flops. This radiation hardened circuits include large-spacing interlock CRAM cells, area [...] Read more.
The 65 nm Static Random Access Memory (SRAM) based Field Programmable Gate Array (FPGA) was designed and manufactured, which employed tradeoff radiation hardening techniques in Configuration RAMs (CRAMs), Embedded RAMs (EBRAMs) and flip-flops. This radiation hardened circuits include large-spacing interlock CRAM cells, area saving debugging logics, the redundant flip-flops cells, and error mitigated 6-T EBRAMs. Heavy ion irradiation test result indicates that the hardened CRAMs had a high linear energy transfer threshold of upset ∼18 MeV/(mg/cm 2 ) with an extremely low saturation cross-section of 6.5 × 10 13 cm 2 /bit, and 71% of the upsets were single-bit upsets. The combinational use of triple modular redundancy and check code could decline ∼86.5% upset errors. Creme tools were used to predict the CRAM upset rate, which was merely 8.46 × 10 15 /bit/day for the worst radiation environment. The effectiveness of radiation tolerance has been verified by the irradiation and prediction results. Full article
(This article belongs to the Special Issue Radiation Tolerant Electronics) Printed Edition available
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Open AccessArticle
Fine-Grain Circuit Hardening Through VHDL Datatype Substitution
Electronics 2019, 8(1), 24; https://doi.org/10.3390/electronics8010024 - 25 Dec 2018
Cited by 4
Abstract
Radiation effects can induce, amongst other phenomena, logic errors in digital circuits and systems. These logic errors corrupt the states of the internal memory elements of the circuits and can propagate to the primary outputs, affecting other onboard systems. In order to avoid [...] Read more.
Radiation effects can induce, amongst other phenomena, logic errors in digital circuits and systems. These logic errors corrupt the states of the internal memory elements of the circuits and can propagate to the primary outputs, affecting other onboard systems. In order to avoid this, Triple Modular Redundancy is typically used when full robustness against these phenomena is needed. When full triplication of the complete design is not required, selective hardening can be applied to the elements in which a radiation-induced upset is more likely to propagate to the main outputs of the circuit. The present paper describes a new approach for selectively hardening digital electronic circuits by design, which can be applied to digital designs described in the VHDL Hardware Description Language. When the designer changes the datatype of a signal or port to a hardened type, the necessary redundancy is automatically inserted. The automatically hardening features have been compiled into a VHDL package, and have been validated both in simulation and by means of fault injection. Full article
(This article belongs to the Special Issue Radiation Tolerant Electronics) Printed Edition available
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Open AccessArticle
A Radiation-Hardened Instrumentation Amplifier for Sensor Readout Integrated Circuits in Nuclear Fusion Applications
Electronics 2018, 7(12), 429; https://doi.org/10.3390/electronics7120429 - 12 Dec 2018
Cited by 4
Abstract
A nuclear fusion reactor requires a radiation-hardened sensor readout integrated circuit (IC), whose operation should be tolerant against harsh radiation effects up to MGy or higher. This paper proposes radiation-hardening circuit design techniques for an instrumentation amplifier (IA), which is one of the [...] Read more.
A nuclear fusion reactor requires a radiation-hardened sensor readout integrated circuit (IC), whose operation should be tolerant against harsh radiation effects up to MGy or higher. This paper proposes radiation-hardening circuit design techniques for an instrumentation amplifier (IA), which is one of the most sensitive circuits in the sensor readout IC. The paper studied design considerations for choosing the IA topology for radiation environments and proposes a radiation-hardened IA structure with total-ionizing-dose (TID) effect monitoring and adaptive reference control functions. The radiation-hardened performance of the proposed IA was verified through model-based circuit simulations by using compact transistor models that reflected the TID effects into complementary metal–oxide–semiconductor (CMOS) parameters. The proposed IA was designed with the 65 nm standard CMOS process and provides adjustable voltage gain between 3 and 15, bandwidth up to 400 kHz, and power consumption of 34.6 μW, while maintaining a stable performance over TID effects up to 1 MGy. Full article
(This article belongs to the Special Issue Radiation Tolerant Electronics) Printed Edition available
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Open AccessArticle
Protecting Image Processing Pipelines against Configuration Memory Errors in SRAM-Based FPGAs
Electronics 2018, 7(11), 322; https://doi.org/10.3390/electronics7110322 - 15 Nov 2018
Cited by 3
Abstract
Image processing systems are widely used in space applications, so different radiation-induced malfunctions may occur in the system depending on the device that is implementing the algorithm. SRAM-based FPGAs are commonly used to speed up the image processing algorithm, but then the system [...] Read more.
Image processing systems are widely used in space applications, so different radiation-induced malfunctions may occur in the system depending on the device that is implementing the algorithm. SRAM-based FPGAs are commonly used to speed up the image processing algorithm, but then the system could be vulnerable to configuration memory errors caused by single event upsets (SEUs). In those systems, the captured image is streamed pixel by pixel from the camera to the FPGA. Certain local operations such as median or rank filters need to process the image locally instead of pixel by pixel, so some particular pixel caching structures such as line-buffer-based pipelines can be used to accelerate the filtering process. However, an SRAM-based FPGA implementation of these pipelines may have malfunctions due to the mentioned configuration memory errors, so an error mitigation technique is required. In this paper, a novel method to protect line-buffer-based pipelines against SRAM-based FPGA configuration memory errors is presented. Experimental results show that, using our protection technique, considerable savings in terms of FPGA resources can be achieved while maintaining the SEU protection coverage provided by other classic pipeline protection schemes. Full article
(This article belongs to the Special Issue Radiation Tolerant Electronics) Printed Edition available
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Open AccessArticle
Total Ionizing Dose Effects on a Delay-Based Physical Unclonable Function Implemented in FPGAs
Electronics 2018, 7(9), 163; https://doi.org/10.3390/electronics7090163 - 24 Aug 2018
Cited by 5
Abstract
Physical Unclonable Functions (PUFs) are hardware security primitives that are increasingly being used for authentication and key generation in ICs and FPGAs. For space systems, they are a promising approach to meet the needs for secure communications at low cost. To this purpose, [...] Read more.
Physical Unclonable Functions (PUFs) are hardware security primitives that are increasingly being used for authentication and key generation in ICs and FPGAs. For space systems, they are a promising approach to meet the needs for secure communications at low cost. To this purpose, it is essential to determine if they are reliable in the space radiation environment. In this work we evaluate the Total Ionizing Dose effects on a delay-based PUF implemented in SRAM-FPGA, namely a Ring Oscillator PUF. Several major quality metrics have been used to analyze the evolution of the PUF response with the total ionizing dose. Experimental results demonstrate that total ionizing dose has a perceptible effect on the quality of the PUF response, but it could still be used for space applications by making some appropriate corrections. Full article
(This article belongs to the Special Issue Radiation Tolerant Electronics) Printed Edition available
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