FPGAs and Reconfigurable Systems: Theory, Methods and Applications

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: 30 November 2025 | Viewed by 1058

Special Issue Editors


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Guest Editor
School of Automation Engineering, University of Electronic Science and Technology of China, Chengdu 611731, China
Interests: ultra-wideband high-speed data acquisition system; high-speed real-time data processing based on FPGA

E-Mail Website
Guest Editor
School of Automation Engineering, University of Electronic Science and Technology of China, Chengdu 611731, China
Interests: high-speed and high-precision data acquisition and processing; digital storage (3D) oscilloscopes; wireless sensing systems

E-Mail Website
Guest Editor
School of Microelectronics, Tianjin University, Tianjin 300072, China
Interests: reconfigurable computing; VLSI design automation and optimization; high-speed and low-power design; IC security

Special Issue Information

Dear Colleagues,

Field-programmable gate arrays (FPGAs) and reconfigurable systems have demonstrated significant value in various fields such as telecommunications, artificial intelligence, image processing, automotive electronics, defense industries, and medical imaging. While traditional general-purpose processors often struggle to meet the high-performance computing demands required for highly parallel, customized, and real-time applications, FPGAs and reconfigurable systems can overcome these bottlenecks by offering flexible and efficient solutions. These technologies play a critical role in enabling industries to achieve intelligent upgrades and transformations in complex environments that demand dynamic adaptability, scalability, and high-performance computing.

The purpose of this Special Issue is to rapidly disseminate the latest theories and research findings across a broad spectrum of topics, with a particular focus on the latest advancements, practical applications, and future trends of FPGAs and reconfigurable systems. We encourage scholars to submit papers on performance improvements, architecture optimization, and case applications related to FPGAs and reconfigurable systems, whether in research articles, technical communications, review papers, or brief reports. We especially welcome interdisciplinary contributions that explore how to bridge the gap between methodology and metrology and how to drive innovative applications of FPGAs across various fields. The close connections and synergies between different research domains provide substantial opportunities for the advancement of these technologies. Through this Special Issue, we aim to bring together cutting-edge research and technological innovations to accelerate the development and application of FPGAs and reconfigurable systems across diverse sectors. We look forward to your contributions as we collectively push forward this exciting area of research.

Prof. Dr. Kuojun Yang
Dr. Wuhuang Huang
Prof. Dr. Qiang Liu
Guest Editors

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Keywords

  • FPGA (field programmable gate array)
  • reconfigurable systems
  • high performance computing
  • parallel processing
  • real-time signal processing
  • dynamic reconfigurable
  • hardware acceleration
  • artificial intelligence
  • 5G/6G communications
  • image processing
  • adaptive systems
  • signal processing

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Published Papers (1 paper)

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Research

26 pages, 9948 KB  
Article
Comprehensive RTL-to-GDSII Workflow for Custom Embedded FPGA Architectures Using Open-Source Tools
by Emilio Isaac Baungarten-Leon, Susana Ortega-Cisneros, Gerardo Leyva, Héctor Emmanuel Muñoz Zapata, Erick Guzmán-Quezada, Francisco J. Alvarado-Rodríguez and Juan Jose Raygoza-Panduro
Electronics 2025, 14(19), 3866; https://doi.org/10.3390/electronics14193866 - 29 Sep 2025
Viewed by 832
Abstract
The main objective of this work is to provide a comprehensive explanation of the Register Transfer Level (RTL) to Graphic Data System II (GDSII) flow for designing custom Field-Programmable Gate Array (FPGA) architectures at the 130 nm technology node using the SKY130 Process [...] Read more.
The main objective of this work is to provide a comprehensive explanation of the Register Transfer Level (RTL) to Graphic Data System II (GDSII) flow for designing custom Field-Programmable Gate Array (FPGA) architectures at the 130 nm technology node using the SKY130 Process Design Kit (PDK). By leveraging open-source tools—specifically OpenLane and OpenFPGA—this study details the methodology and implementation steps required to generate a GDSII layout of a custom FPGA. OpenLane offers an integrated RTL-to-GDSII flow by combining multiple Electronic Design Automation (EDA) tools, while OpenFPGA enables the construction of flexible and customizable FPGA architectures. The article covers key aspects of the RTL-to-GDSII workflow, including RTL file configuration, the utilization of configuration variables for physical design, hierarchical chip design, macro and core implementation, chip-level integration, and gate-level simulation. Experimental results validate the proposed workflow, showcasing the successful transformation from RTL to GDSII. The findings of this research provide valuable insights for researchers and engineers in the FPGA design field, advancing the state of the art in FPGA architecture development. Full article
(This article belongs to the Special Issue FPGAs and Reconfigurable Systems: Theory, Methods and Applications)
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